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Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 33852a5ffca8..a3fe1eea6aec 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -38,6 +38,7 @@ properties: - qcom,sm8450-cci - qcom,sm8550-cci - qcom,sm8650-cci + - qcom,sm8750-cci - qcom,x1e80100-cci - const: qcom,msm8996-cci # CCI v2 =20 @@ -132,6 +133,7 @@ allOf: enum: - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,sm8750-cci then: properties: clocks: --=20 2.34.1 From nobody Mon Dec 1 23:33:40 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3D81308F38 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:05 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:35 -0800 Subject: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-2-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX51FmdqvCzVIr b8MERmv+yLwc6stONfJAU6+0WwBznzjNQDaFsSfHFU+0JeZ+8bNQpfIS1dIA8AmjxXmvOnAB+gG i+f6v7leuOYgdQbzF9HCoXish405NO6ynUBm14PlL1NKP5OV9sUe7Zd9DaJs02RS8pUMy/gWBll ECjJ1wtX80JtsL051B9dWzOM2enoT/5/CfToBt+FgkDeEW62H/mWQ4k+sIg05ekEHdyhEZ94yh6 waJj8MNq0sccq+j0FZFdMEtRvOH0v3XD3SrOcKf57LI3sR/LrrWyfoFssb6txNxJ0x7Bs0iXuJ5 V7GRVqTgQ1FbhZaLUNhmvUV2VS/OOFBlKQlcryQb1NENRfzOhQJzdnrJ6csbYN5LwqzmNoRLxdF Ez9EpSYC1vDByUCwx84D4Y9W81o0aQ== X-Proofpoint-GUID: kPZ-EH3L7XdlDM-gWyjGetGm6TxQ4OQL X-Proofpoint-ORIG-GUID: kPZ-EH3L7XdlDM-gWyjGetGm6TxQ4OQL X-Authority-Analysis: v=2.4 cv=feugCkQF c=1 sm=1 tr=0 ts=6926caf8 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=dpxBiYkotQz7p_VYlh4A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add the compatible string "qcom,sm8750-camss" to support the Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform. The SM8750 platform provides: - 3 x VFE, 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID - 2 x CSID Lite - 6 x CSIPHY - 2 x ICP - 1 x IPE - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE - 5 x RT CDM - 3 x TPG Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++= ++++ 1 file changed, 664 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml= b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml new file mode 100644 index 000000000000..6b2b0b5a7e19 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml @@ -0,0 +1,664 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + This binding describes the camera subsystem hardware found on SM8750 Qua= lcomm + SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID + (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engine= s and + their associated configuration modules, as well as non-real-time engines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,sm8750-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP SYS 0 + - description: Registers for ICP 1 + - description: Registers for ICP SYS 1 + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler 0 + - description: Registers for JPEG Encoder 0 + - description: Registers for JPEG DMA & Downscaler 1 + - description: Registers for JPEG Encoder 1 + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma0 + - const: jpeg_enc0 + - const: jpeg_dma1 + - const: jpeg_enc1 + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 61 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cam_top_ahb + - const: cam_top_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_hf_axi + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_sf_axi + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg0 + - const: jpeg1 + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 32 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma0 + - const: jpeg_enc0 + - const: jpeg_dma1 + - const: jpeg_enc1 + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_icp_mnoc + - const: sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + VFE0 GDSC - Global Distributed Switch Controller for VFE0. + - description: + VFE1 GDSC - Global Distributed Switch Controller for VFE1. + - description: + VFE2 GDSC - Global Distributed Switch Controller for VFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@ad27000 { + compatible =3D "qcom,sm8750-camss"; + + reg =3D <0x0 0x0ad27000 0x0 0x2b00>, + <0x0 0x0ad2a000 0x0 0x2b00>, + <0x0 0x0ad2d000 0x0 0x2b00>, + <0x0 0x0ad6d000 0x0 0xa00>, + <0x0 0x0ad72000 0x0 0xa00>, + <0x0 0x0ada9000 0x0 0x2000>, + <0x0 0x0adab000 0x0 0x2000>, + <0x0 0x0adad000 0x0 0x2000>, + <0x0 0x0adaf000 0x0 0x2000>, + <0x0 0x0adb1000 0x0 0x2000>, + <0x0 0x0adb3000 0x0 0x2000>, + <0x0 0x0ac86000 0x0 0x10000>, + <0x0 0x0ac96000 0x0 0x10000>, + <0x0 0x0aca6000 0x0 0x10000>, + <0x0 0x0ad6e000 0x0 0x1800>, + <0x0 0x0ad73000 0x0 0x1800>, + <0x0 0x0ac06000 0x0 0x1000>, + <0x0 0x0ac05000 0x0 0x1000>, + <0x0 0x0ac16000 0x0 0x1000>, + <0x0 0x0ac15000 0x0 0x1000>, + <0x0 0x0ac42000 0x0 0x18000>, + <0x0 0x0ac26000 0x0 0x1000>, + <0x0 0x0ac25000 0x0 0x1000>, + <0x0 0x0ac28000 0x0 0x1000>, + <0x0 0x0ac27000 0x0 0x1000>, + <0x0 0x0ac2a000 0x0 0x18000>, + <0x0 0x0ac7f000 0x0 0x580>, + <0x0 0x0ac80000 0x0 0x580>, + <0x0 0x0ac81000 0x0 0x580>, + <0x0 0x0ac82000 0x0 0x580>, + <0x0 0x0ac83000 0x0 0x580>, + <0x0 0x0ad8b000 0x0 0x400>, + <0x0 0x0ad8c000 0x0 0x400>, + <0x0 0x0ad8d000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_0_clk>, + <&camcc_cam_cc_jpeg_1_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cam_top_ahb", + "cam_top_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_hf_axi", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_sf_axi", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg0", + "jpeg1", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_nrt_icp_sf QCOM_ICC_T= AG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_icp_mnoc", + "sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:06 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:36 -0800 Subject: [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-3-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=KerfcAYD c=1 sm=1 tr=0 ts=6926caf8 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=gE60Ov1lhapgyOv8Ur0A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: nTvJLMamlyFpHIinPo5VyoY9LBC5ahH- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX40SCzdB5R1dY h0zUOcTfMI2IQpMkHZV6MUF/tNRC7BJDS4FagGVeR3Xtf4yj24zZF8rAqweIagP6jXIlMV8yF05 Ast5SGzlfhlFNoKZ3ZlQcxvqCHxcvG0wVkx31fNa/VfHZkofETCjKKN0Qh1mUJ1KjKheIdpnFeM rTssPvMpgNxGdKrhS3Z3fjc+q44KMDM1HnQ7H8CyrPyLldbBoCqKyh/KaBo0uBv27n6TT8pqhGE 1k5jKgt6o13jkgHHDOlI9Bwz0LayeGV1suI4OECfIBwESHYwwMNPJSdPv85IUw+TLhlxnuRseP5 ycHnUchsvaeu8LS5uWHkh8YN2Phy5P4zaMyvyogqXo27sgT+8u06oVPxPO9M9jRs/tlayl5WGqp 7UtDY6fJ8aqi7B7IMl0gOwM8MZR8kA== X-Proofpoint-ORIG-GUID: nTvJLMamlyFpHIinPo5VyoY9LBC5ahH- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add support for SM8750 in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 5ee43c8a9ae4..805e2fbd97dd 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3870,6 +3870,20 @@ static const struct resources_icc icc_res_sa8775p[] = =3D { }, }; =20 +static const struct resources_icc icc_res_sm8750[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 471860, + .icc_bw_tbl.peak =3D 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_x1e80100[] =3D { /* CSIPHY0 */ { @@ -5283,6 +5297,13 @@ static const struct camss_resources sm8650_resources= =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_sm8650), }; =20 +static const struct camss_resources sm8750_resources =3D { + .version =3D CAMSS_8750, + .pd_name =3D "top", + .icc_res =3D icc_res_sm8750, + .icc_path_num =3D ARRAY_SIZE(icc_res_sm8750), +}; + static const struct camss_resources x1e80100_resources =3D { .version =3D CAMSS_X1E80100, .pd_name =3D "top", @@ -5314,6 +5335,7 @@ static const struct of_device_id camss_dt_match[] =3D= { { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, { .compatible =3D "qcom,sm8550-camss", .data =3D &sm8550_resources }, { .compatible =3D "qcom,sm8650-camss", .data =3D &sm8650_resources }, + { .compatible =3D "qcom,sm8750-camss", .data =3D &sm8750_resources }, { .compatible =3D "qcom,x1e80100-camss", .data =3D &x1e80100_resources }, { } }; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index b1cc4825f027..f87b615ad1a9 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -91,6 +91,7 @@ enum camss_version { CAMSS_845, CAMSS_8550, CAMSS_8650, + CAMSS_8750, CAMSS_8775P, CAMSS_KAANAPALI, CAMSS_X1E80100, --=20 2.34.1 From nobody Mon Dec 1 23:33:40 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249BD3164BD for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:07 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:37 -0800 Subject: [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-4-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=C53kCAP+ c=1 sm=1 tr=0 ts=6926caf9 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=UiSUrLz6K6kVaq6zp58A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX9QmE0FG9gZsC dKOsqmBTUdAwuFp6GV2d4Lk88DFzjKOjWXT1AXGbSPcK7Ik1HkZxX/nLyDZbYH+D8hABrmgIAa+ 7wqlzY4q2uWHfr0RDuFD3P4xQGU8VhnXAPYAw5S5/e1LCVotcE/vzxz2uGNNuZKX8u2eDd3FXzh OgRKzjCZObt+lUWMcd+JozeLp7bv5Ji7xme65FWlZ4ZAPNOs1/O7KB61wZeuGn09VX62nolI36C YOotp3F+/uNu5wTMXIJWZ3qJJPjTUWGKjlgMqWxl5CUS1Bph6Lts+3TuajJ70gYNKVCRSt+l3wz Se1EfPJNCpqhko31n12lL5jVz03bgPnrhpdwuWwewVcLwFFwkNlGfYgE/qsg9pPL6FuD5zy+dZu LYek4gVTqVJ7+Sr2Tkyba4ifG+RVoA== X-Proofpoint-ORIG-GUID: zXs6y7kdGHcrqrYiSWlFClWK1tQs4KiR X-Proofpoint-GUID: zXs6y7kdGHcrqrYiSWlFClWK1tQs4KiR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.3.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Additionally, generalize the struct name for the lane configuration that had been added for Kaanapali and use it for SM8750 as well as they share the settings. Signed-off-by: Hangxiang Ma --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 11 ++- drivers/media/platform/qcom/camss/camss.c | 107 +++++++++++++++++= ++++ 2 files changed, 114 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index f9db7e195dfe..157e946f67db 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -684,9 +684,9 @@ csiphy_lane_regs lane_regs_sm8650[] =3D { {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */ static const struct -csiphy_lane_regs lane_regs_kaanapali[] =3D { +csiphy_lane_regs lane_regs_v_2_3[] =3D { /* LN 0 */ {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -1134,6 +1134,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: @@ -1250,9 +1251,11 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_sa8775p[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_8750: case CAMSS_KAANAPALI: - regs->lane_regs =3D &lane_regs_kaanapali[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_kaanapali); + /* CSPHY v2.4.0 is backward compatible with v2.3.0 settings */ + regs->lane_regs =3D &lane_regs_v_2_3[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_v_2_3); regs->offset =3D 0x1000; regs->common_status_offset =3D 0x138; break; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 805e2fbd97dd..bfc942635682 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3870,6 +3870,111 @@ static const struct resources_icc icc_res_sa8775p[]= =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_8750[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { "vdd-csiphy0-0p88", "vdd-csiphy0-1p2" }, + .clock =3D { "csiphy0", "csiphy0_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { "vdd-csiphy1-0p88", "vdd-csiphy1-1p2" }, + .clock =3D { "csiphy1", "csiphy1_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { "vdd-csiphy2-0p88", "vdd-csiphy2-1p2" }, + .clock =3D { "csiphy2", "csiphy2_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { "vdd-csiphy3-0p88", "vdd-csiphy3-1p2" }, + .clock =3D { "csiphy3", "csiphy3_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators =3D { "vdd-csiphy4-0p88", "vdd-csiphy4-1p2" }, + .clock =3D { "csiphy4", "csiphy4_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy4" }, + .interrupt =3D { "csiphy4" }, + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators =3D { "vdd-csiphy5-0p88", "vdd-csiphy5-1p2" }, + .clock =3D { "csiphy5", "csiphy5_timer", + "cam_top_ahb", "cam_top_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy5" }, + .interrupt =3D { "csiphy5" }, + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, +}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:08 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:38 -0800 Subject: [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-5-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX9ozUev5EvZg6 9y0zacnsxy6W5FEgnqtmN0OkD27p9HzjCTDnwfSCGR2JePkJYHhshYbMOnWv7nZJHP0QIkSPLld FO2tspX7z1FVS8VFwqO+Vrx9nw0tWIP0OlKjNAwWzG19Cqz+axAh2KttoXB4/1a2oLZGWgUNTjY wduxpT9X+Aw/FVPtb6ow9iPR0jy/7Yk3dudtU5eb2JzS8JonOwTTvkucb4GwFC0LKXWA6Vt2qxY G0zwG7+yKwQdZwCd8oeo1SPciPNu+jlE3YjPWy80jZ6P7akBKkjcjPHlhChqwOwqjtvlTOOXzdI iBHWwssD+gcM6CQ+4RHPkeY/C4gjw7wpJFWzrUB9gLG0kw4VDFxCoDqL6PEkZ66+8jYjWNNNDHo aXsJG6TFN/en/yy13uE3Y24c/e0WHg== X-Proofpoint-GUID: KzSmMJZmP0-g38E5-teO0rsKy01lqhul X-Proofpoint-ORIG-GUID: KzSmMJZmP0-g38E5-teO0rsKy01lqhul X-Authority-Analysis: v=2.4 cv=feugCkQF c=1 sm=1 tr=0 ts=6926cafb cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=LS_ThhxF8Vayi6Dnku4A:9 a=Z-sH2BZsVlbqz-yA:21 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add more detailed resource information for CSID devices along with the driver for CSID 980 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. In SM8750, RUP and AUP updates for the CSID Full modules are split into two registers along with a SET register. However, CSID Lite modules still use a single register to update RUP and AUP without the additional SET register. Handled the difference in the driver. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-980.c | 428 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 1 + drivers/media/platform/qcom/camss/camss.c | 80 ++++ 4 files changed, 510 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index a0abbca2b83d..74e12ec65427 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -8,6 +8,7 @@ qcom-camss-objs +=3D \ camss-csid-4-7.o \ camss-csid-340.o \ camss-csid-680.o \ + camss-csid-980.o \ camss-csid-1080.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/m= edia/platform/qcom/camss/camss-csid-980.c new file mode 100644 index 000000000000..0656a912505a --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-980.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0xC +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10 +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x14 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x18 +#define CSID_AUP_CMD 0x1C +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x20 +#define RUP_SET BIT(0) +#define MUP BIT(4) + +#define CSID_LITE_RUP_AUP_CMD 0x18 +#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi)) +#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi)) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84) +#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88) +#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C) +#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90) +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4) +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16) +#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8) +#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC) +#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0) + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4) +#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8) +#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC) +#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0) + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400) +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404) +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5) + +#define CSID_RDI_CFG0(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \ + 0xE00 + 0x200 * _rdi; \ + }) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_DT_ID 27 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \ + 0xE04 + 0x200 * _rdi; \ + }) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \ + 0xE10 + 0x200 * _rdi; \ + }) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \ + (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi)) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \ + (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi)) +#define INFO_RUP_DONE BIT(23) + +static void __csid_full_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + if (!csid_is_lite(csid)) { + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_full_aup_rup_trigger(csid); + } else { + csid->reg_update |=3D CSID_LITE_AUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } +} + +static void __csid_rup_update(struct csid_device *csid, int port_id) +{ + if (!csid_is_lite(csid)) { + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_full_aup_rup_trigger(csid); + } else { + csid->reg_update |=3D CSID_LITE_RUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + if (csid_is_lite(csid)) { + csid->reg_update &=3D ~CSID_LITE_RUP_RDI(port_id); + csid->reg_update &=3D ~CSID_LITE_AUP_RDI(port_id); + } else { + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + } +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + u32 rdi_ctrl_offset =3D CSID_RDI_CTRL(rdi); + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + rdi_ctrl_offset); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + u32 val; + u8 lane_cnt =3D csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + /* + * DT_ID is a two bit bitfield that is concatenated with + * the four least significant bits of the five bit VC + * bitfield to generate an internal CID value. + * + * CSID_RDI_CFG0(vc) + * DT_ID : 28:27 + * VC : 26:22 + * DT : 21:16 + * + * CID : VC 3:0 << 2 | DT_ID 1:0 + */ + u8 dt_id =3D vc & 0x03; + u32 rdi_cfg0_offset =3D CSID_RDI_CFG0(vc); + u32 rdi_cfg1_offset =3D CSID_RDI_CFG1(vc); + u32 rdi_ctrl_offset =3D CSID_RDI_CTRL(vc); + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + val |=3D dt_id << RDI_CFG0_DT_ID; + writel(val, csid->base + rdi_cfg0_offset); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + rdi_cfg1_offset); + + /* Configure pixel store using dedicated register in 980 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val =3D 0; + writel(val, csid->base + rdi_ctrl_offset); + + val =3D readl(csid->base + rdi_cfg0_offset); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + rdi_cfg0_offset); +} + +static void csid_configure_stream_980(struct csid_device *csid, u8 enable) +{ + u8 vc, i; + + __csid_configure_rx(csid, &csid->phy); + + for (vc =3D 0; vc < MSM_CSID_MAX_SRC_STREAMS_980; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) { + __csid_aup_update(csid, vc); + __csid_rup_update(csid, vc); + } + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern_980(struct csid_device *csid, + s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update_980(struct csid_device *csid, int port_= id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr_980(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update_980(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset_980(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init_980(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_980 =3D { + .configure_stream =3D csid_configure_stream_980, + .configure_testgen_pattern =3D csid_configure_testgen_pattern_980, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr_980, + .reset =3D csid_reset_980, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init_980, + .reg_update =3D csid_subdev_reg_update_980, +}; + diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index 6c214b487003..c77c61ab9c3a 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -223,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; +extern const struct csid_hw_ops csid_ops_980; extern const struct csid_hw_ops csid_ops_1080; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index bfc942635682..9dea343c1ac5 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3975,6 +3975,84 @@ static const struct camss_subdev_resources csiphy_re= s_8750[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_8750[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_sm8750[] =3D { { .name =3D "ahb", @@ -5406,8 +5484,10 @@ static const struct camss_resources sm8750_resources= =3D { .version =3D CAMSS_8750, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8750, + .csid_res =3D csid_res_8750, .icc_res =3D icc_res_sm8750, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8750), + .csid_num =3D ARRAY_SIZE(csid_res_8750), .icc_path_num =3D ARRAY_SIZE(icc_res_sm8750), }; =20 --=20 2.34.1 From nobody Mon Dec 1 23:33:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 464EA31BC8F for ; Wed, 26 Nov 2025 09:40:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764150017; cv=none; b=orBAVdF5YW5ipxeO4NRxaoirttk7JTxdXk3qVll9vRAxLoNOUVbIlVXlKft+isMAnQS/7Y+7ORVhtmnZDI4KokDGbdsH9+FCXyXp62p//WfY+u3TzdE8i5/2JUE0A2lMydVt3eJ3A5K/1nPCWtnlld9WNLyScljtGKchSoCWIRQ= ARC-Message-Signature: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:09 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:39 -0800 Subject: [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-6-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=KerfcAYD c=1 sm=1 tr=0 ts=6926cafb cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BHla8BSFx5Mbbv4c_UwA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: rG-yqvloDhiF4MkFs8KMnUgNfdTWNPwY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX2d4EPsxgOY/s G1c+IDCcIez6RXTjjmXOCRp+E1jq4SOEkURWauxEE6RxUaNGkfaZagIVdhmwgkmGtsSwnrnxpJQ GSxk1UoQMLUxpbKcDJGDGfzGfkwH5eaNRKi4aRYfTgoTvGJ9lec4c+GKPswarNw8WY3IpY0hUMU 9y3nfkmdNoCN7h3vd8CKo4w6gIivnB9wzhtJ+YyjMkURe2tpAkaZV5AbdhFdcemA2k57kCKsx81 6JJnRyoGR+v2Ga+hQ2zFdIklG9CCnAbCExfed18n+t+sZH4j+YSevjFGYNntQBa6MWnzKEsVo1m 8KL6Nd3vW0WLwME+up3szoZUB6G1YoaYbXqB9HZ20Bn8/Zyp817D5coemiTeqlBXBaTsQsPEmvA HaSfO0kF9P0j4Chj5fWooN8adP53yg== X-Proofpoint-ORIG-GUID: rG-yqvloDhiF4MkFs8KMnUgNfdTWNPwY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add support for Video Front End (VFE) that is on the SM8750 SoCs. The bus_wr configuration and the registers offsets closely match with the driver that had been added for Kaanapali. Hence, rename the previously added driver as 'gen4' and use that for both to avoid redundancy. Handle the minor differences in the driver using the chipset version. This change limits SM8750 VFE output lines to 3 for now as constrained by the CAMSS driver framework. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 4 +- .../camss/{camss-vfe-1080.c =3D> camss-vfe-gen4.c} | 60 +++++---- drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss-vfe.h | 2 +- drivers/media/platform/qcom/camss/camss.c | 150 +++++++++++++++++= +++- 5 files changed, 182 insertions(+), 36 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 74e12ec65427..6e54d2d11ed3 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -23,9 +23,9 @@ qcom-camss-objs +=3D \ camss-vfe-340.o \ camss-vfe-480.o \ camss-vfe-680.o \ - camss-vfe-1080.o \ - camss-vfe-gen3.o \ camss-vfe-gen1.o \ + camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe-vbif.o \ camss-vfe.o \ camss-video.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/m= edia/platform/qcom/camss/camss-vfe-gen4.c similarity index 75% rename from drivers/media/platform/qcom/camss/camss-vfe-1080.c rename to drivers/media/platform/qcom/camss/camss-vfe-gen4.c index 9ad3dee2e80b..d0218950c05c 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-1080.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * camss-vfe-1080.c + * camss-vfe-gen4.c * - * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080 + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4 * * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ @@ -13,8 +13,12 @@ #include "camss.h" #include "camss-vfe.h" =20 -/* VFE-1080 Bus Register Base Addresses */ -#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) +#define IS_VFE_980(vfe) ((vfe)->camss->res->version =3D=3D CAMSS_8750) + +#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800) +#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000) +#define BUS_REG_BASE \ + (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080) =20 #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) @@ -55,7 +59,7 @@ * DISPLAY_DS2_C 6 * FD_Y 7 * FD_C 8 - * PIXEL_RAW 9 + * RAW_OUT(1080)/IR_OUT(980) 9 * STATS_AEC_BG 10 * STATS_AEC_BHIST 11 * STATS_TINTLESS_BG 12 @@ -86,7 +90,7 @@ */ #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) =20 -static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_li= ne *line) +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *l= ine) { struct v4l2_pix_format_mplane *pix =3D &line->video_out.active_fmt.fmt.pix_mp; @@ -121,14 +125,14 @@ static void vfe_wm_start_1080(struct vfe_device *vfe,= u8 wm, struct vfe_line *li writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); } =20 -static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm) +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) { wm =3D RDI_WM(wm); writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); } =20 -static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr, - struct vfe_line *line) +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) { wm =3D RDI_WM(wm); writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); @@ -136,62 +140,62 @@ static void vfe_wm_update_1080(struct vfe_device *vfe= , u8 wm, u32 addr, dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); } =20 -static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id l= ine_id) +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_i= d) { int port_id =3D line_id; =20 camss_reg_update(vfe->camss, vfe->id, port_id, false); } =20 -static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe, - enum vfe_line_id line_id) +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) { int port_id =3D line_id; =20 camss_reg_update(vfe->camss, vfe->id, port_id, true); } =20 -static const struct camss_video_ops vfe_video_ops_1080 =3D { +static const struct camss_video_ops vfe_video_ops =3D { .queue_buffer =3D vfe_queue_buffer_v2, .flush_buffers =3D vfe_flush_buffers, }; =20 -static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vf= e) +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) { - vfe->video_ops =3D vfe_video_ops_1080; + vfe->video_ops =3D vfe_video_ops; } =20 -static void vfe_global_reset_1080(struct vfe_device *vfe) +static void vfe_global_reset(struct vfe_device *vfe) { vfe_isr_reset_ack(vfe); } =20 -static irqreturn_t vfe_isr_1080(int irq, void *dev) +static irqreturn_t vfe_isr(int irq, void *dev) { /* nop */ return IRQ_HANDLED; } =20 -static int vfe_halt_1080(struct vfe_device *vfe) +static int vfe_halt(struct vfe_device *vfe) { /* rely on vfe_disable_output() to stop the VFE */ return 0; } =20 -const struct vfe_hw_ops vfe_ops_1080 =3D { - .global_reset =3D vfe_global_reset_1080, +const struct vfe_hw_ops vfe_ops_gen4 =3D { + .global_reset =3D vfe_global_reset, .hw_version =3D vfe_hw_version, - .isr =3D vfe_isr_1080, + .isr =3D vfe_isr, .pm_domain_off =3D vfe_pm_domain_off, .pm_domain_on =3D vfe_pm_domain_on, - .reg_update =3D vfe_reg_update_1080, - .reg_update_clear =3D vfe_reg_update_clear_1080, - .subdev_init =3D vfe_subdev_init_1080, + .reg_update =3D vfe_reg_update, + .reg_update_clear =3D vfe_reg_update_clear, + .subdev_init =3D vfe_subdev_init, .vfe_disable =3D vfe_disable, .vfe_enable =3D vfe_enable_v2, - .vfe_halt =3D vfe_halt_1080, - .vfe_wm_start =3D vfe_wm_start_1080, - .vfe_wm_stop =3D vfe_wm_stop_1080, + .vfe_halt =3D vfe_halt, + .vfe_wm_start =3D vfe_wm_start, + .vfe_wm_stop =3D vfe_wm_stop, .vfe_buf_done =3D vfe_buf_done, - .vfe_wm_update =3D vfe_wm_update_1080, + .vfe_wm_update =3D vfe_wm_update, }; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 399be8b70fed..b8aa4b7d1a8d 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -350,6 +350,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: @@ -2012,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/= platform/qcom/camss/camss-vfe.h index 118cac5daf37..c402ef170c81 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -249,8 +249,8 @@ extern const struct vfe_hw_ops vfe_ops_170; extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; -extern const struct vfe_hw_ops vfe_ops_1080; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; =20 int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 9dea343c1ac5..48d8f282d780 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -245,7 +245,7 @@ static const struct camss_subdev_resources vfe_res_kaan= apali[] =3D { .reg_update_after_csid_config =3D true, .has_pd =3D true, .pd_name =3D "vfe0", - .hw_ops =3D &vfe_ops_1080, + .hw_ops =3D &vfe_ops_gen4, .formats_rdi =3D &vfe_formats_rdi_845, .formats_pix =3D &vfe_formats_pix_845 } @@ -274,7 +274,7 @@ static const struct camss_subdev_resources vfe_res_kaan= apali[] =3D { .reg_update_after_csid_config =3D true, .has_pd =3D true, .pd_name =3D "vfe1", - .hw_ops =3D &vfe_ops_1080, + .hw_ops =3D &vfe_ops_gen4, .formats_rdi =3D &vfe_formats_rdi_845, .formats_pix =3D &vfe_formats_pix_845 } @@ -303,7 +303,7 @@ static const struct camss_subdev_resources vfe_res_kaan= apali[] =3D { .reg_update_after_csid_config =3D true, .has_pd =3D true, .pd_name =3D "vfe2", - .hw_ops =3D &vfe_ops_1080, + .hw_ops =3D &vfe_ops_gen4, .formats_rdi =3D &vfe_formats_rdi_845, .formats_pix =3D &vfe_formats_pix_845 } @@ -327,7 +327,7 @@ static const struct camss_subdev_resources vfe_res_kaan= apali[] =3D { .line_num =3D 4, .is_lite =3D true, .reg_update_after_csid_config =3D true, - .hw_ops =3D &vfe_ops_1080, + .hw_ops =3D &vfe_ops_gen4, .formats_rdi =3D &vfe_formats_rdi_845, .formats_pix =3D &vfe_formats_pix_845 } @@ -351,7 +351,7 @@ static const struct camss_subdev_resources vfe_res_kaan= apali[] =3D { .line_num =3D 4, .is_lite =3D true, .reg_update_after_csid_config =3D true, - .hw_ops =3D &vfe_ops_1080, + .hw_ops =3D &vfe_ops_gen4, .formats_rdi =3D &vfe_formats_rdi_845, .formats_pix =3D &vfe_formats_pix_845 } @@ -4053,6 +4053,144 @@ static const struct camss_subdev_resources csid_res= _8750[] =3D { } }; =20 +static const struct camss_subdev_resources vfe_res_8750[] =3D { + /* VFE0 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "vfe0", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "vfe1", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "vfe2", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + } +}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:10 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:40 -0800 Subject: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-7-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-GUID: WXHN-p9mS0qj3JfDA2WGoi-kMtY1sZVH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX+8DQzOUKFZp6 PUGg2Dh8mSSWjSwjM0OPtuVGvmifYgLUoz1YontqxJago+dXBmsDjogP/RnNXYTSBX2uYC4evet j9d1F/ZYBjG0dcAISZpaRINdJnzAPgwcV4psryfP9tP1+npb0wrQxc33Y75OFGxfMHYm6dLmr2n UZz+O5yUawLac96OdyyvIGFbGHZLwD3cQUsR6GAke1WCIbHu8LB1iD98WG8XVqFtHLYuqfJAhs1 eljXvmENWlJl3LfhAFRBnKVMbtUqoRLq38qOLuzKJE+yj+Big6ULlio1MLUE0ye3kz7bs6rNVOX hYhMt7C4xvUXYXwDdgOWuNMGkTJMIyq2fo0kp9/75ekKy650OtgujrZaXpX7eAQp5Ob+33GUUu+ YQGA7hBls3Q5+YDIXMc2lLxISJAKeg== X-Authority-Analysis: v=2.4 cv=H4LWAuYi c=1 sm=1 tr=0 ts=6926cafc cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=OOGx0pUHP5hP6dmBc4UA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: WXHN-p9mS0qj3JfDA2WGoi-kMtY1sZVH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add support for the camera subsystem on the SM8750 Qualcomm SoC. This includes bringing up the CSIPHY, CSID, VFE/RDI interfaces. This change also introduces the necessary modules for enabling future extended functionalities. The SM8750 platform provides: - 3 x VFE, 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE - 3 x CSID - 2 x CSID Lite - 6 x CSI PHY - 2 x ICP - 1 x IPE - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE - 5 x RT CDM - 3 x TPG Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 599 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 1937b48fac5a..b83389c3456b 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3332,6 +3332,605 @@ data-pins { bias-pull-up; }; }; + + cci0_0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio115"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio116"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio115"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio116"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio117"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio118"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio117"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio118"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio164"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio164"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio153"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio153"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins =3D "gpio119"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + + scl-pins { + pins =3D "gpio120"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins =3D "gpio119"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio120"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + }; + + cci0: cci@ac7b000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7b000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac7c000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7c000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac7d000 { + compatible =3D "qcom,sm8750-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac7d000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "ahb", "cci"; + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + camss: isp@ad27000 { + compatible =3D "qcom,sm8750-camss"; + + reg =3D <0x0 0x0ad27000 0x0 0x2b00>, + <0x0 0x0ad2a000 0x0 0x2b00>, + <0x0 0x0ad2d000 0x0 0x2b00>, + <0x0 0x0ad6d000 0x0 0xa00>, + <0x0 0x0ad72000 0x0 0xa00>, + <0x0 0x0ada9000 0x0 0x2000>, + <0x0 0x0adab000 0x0 0x2000>, + <0x0 0x0adad000 0x0 0x2000>, + <0x0 0x0adaf000 0x0 0x2000>, + <0x0 0x0adb1000 0x0 0x2000>, + <0x0 0x0adb3000 0x0 0x2000>, + <0x0 0x0ac86000 0x0 0x10000>, + <0x0 0x0ac96000 0x0 0x10000>, + <0x0 0x0aca6000 0x0 0x10000>, + <0x0 0x0ad6e000 0x0 0x1800>, + <0x0 0x0ad73000 0x0 0x1800>, + <0x0 0x0ac06000 0x0 0x1000>, + <0x0 0x0ac05000 0x0 0x1000>, + <0x0 0x0ac16000 0x0 0x1000>, + <0x0 0x0ac15000 0x0 0x1000>, + <0x0 0x0ac42000 0x0 0x18000>, + <0x0 0x0ac26000 0x0 0x1000>, + <0x0 0x0ac25000 0x0 0x1000>, + <0x0 0x0ac28000 0x0 0x1000>, + <0x0 0x0ac27000 0x0 0x1000>, + <0x0 0x0ac2a000 0x0 0x18000>, + <0x0 0x0ac7f000 0x0 0x580>, + <0x0 0x0ac80000 0x0 0x580>, + <0x0 0x0ac81000 0x0 0x580>, + <0x0 0x0ac82000 0x0 0x580>, + <0x0 0x0ac83000 0x0 0x580>, + <0x0 0x0ad8b000 0x0 0x400>, + <0x0 0x0ad8c000 0x0 0x400>, + <0x0 0x0ad8d000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cam_top_ahb", + "cam_top_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_hf_axi", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_sf_axi", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg0", + "jpeg1", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_icp_mnoc", + "sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1860 0x00>; + + power-domains =3D <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&camcc CAM_CC_IPE_0_GDSC>, + <&camcc CAM_CC_OFE_GDSC>; + power-domain-names =3D "vfe0", + "vfe1", + "vfe2", + "top", + "ipe", + "ofe"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + }; + }; =20 tcsrcc: clock-controller@f204008 { --=20 2.34.1