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Tue, 25 Nov 2025 14:45:48 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/4] arm64: dts: renesas: r9a09g056: Add ICU node Date: Tue, 25 Nov 2025 22:45:30 +0000 Message-ID: <20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251125224533.294235-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251125224533.294235-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index ac8b4a4f5fb7..5a2a4056b7cc 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -183,12 +183,104 @@ soc: soc { #size-cells =3D <2>; ranges; =20 + icu: interrupt-controller@10400000 { + compatible =3D "renesas,r9a09g056-icu", "renesas,r9a09g057-icu"; + reg =3D <0 0x10400000 0 0x10000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks =3D <&cpg CPG_MOD 0x5>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible =3D "renesas,r9a09g056-pinctrl"; reg =3D <0 0x10410000 0 0x10000>; clocks =3D <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; gpio-controller; #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&icu>; gpio-ranges =3D <&pinctrl 0 0 96>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; --=20 2.52.0