From nobody Mon Dec 1 23:59:44 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 930DD1A23B9 for ; Tue, 25 Nov 2025 21:50:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764107453; cv=none; b=sE/0PtRMiwkduq63C/GgQrxCPdG4EBj7NCcxCCSHl3DQ16o88sZrP7PSGZAljd6w/QjgzE+t75tHXlgpIG4SZVLKCty4x550deIybispaCh598y8jfs4VXKOyQfsXfvzvDVTna1ZbPe1tpl6T1uidnzA+9KI/g17hCxCnPdn5/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764107453; c=relaxed/simple; bh=DjibwioIovEPRFE6dFSW5vCVrtE7SRdONGeWus0jthA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=iyq//oqLSyV7F/rFQyPk9uME5eFPAh8cNjndvD3F+7uGZji7nEAoRgQs6zbtvcorN19nTewCglFuM+ulWt8G+QH00MeG+qytSINduIfi4K/rjDabYrYaHv9ixIYii/5iQyZ5FwGfsj41s6grTdWfrbv0NfCQ3lOyPUXG4gaSn4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cD596zK7; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BBv8OQ8z; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cD596zK7"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BBv8OQ8z" Message-ID: <20251125214631.170499997@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1764107450; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YkfxTMic4k5ai/PaYAmYfJhncvxgcF3Eey2WLa9e9XI=; b=cD596zK7nsugzfV7ZRTZLWiunC1a0YqpUxjHlqCgVsK3bNjL7tB7YfDKHTMbQypvKRn8cz y1ko6XbWhWStiyx6uEsizHTPHOWRBZ3mKH9NZIgiZ4jYNl3Upog3rAhPuMkeOwr0iwkaeD treI3OdPN92hIIWq6zcAflAQX07AcETyYQwbHoRhDM6xcBQgYT8WOi6j1k3Dl5uOTMI+7L Ci2mF3ZZ26v9kBIJzzs62jD3FZz5g7obB+J4wrz8ScmGO0AtGsI7IyEsejSDWSPhJl9xHg NEYqoSqdXN4waScpNXuYIR7UWvpJgWn8xNMbxt9PZNGdVMiARcJnZSPDHjbDJg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1764107450; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YkfxTMic4k5ai/PaYAmYfJhncvxgcF3Eey2WLa9e9XI=; b=BBv8OQ8zj/40TWAA3IrZD1S1pKeCnExMuuJ3V7CdhyDzcutCoit40GabRHYmwgeSTZkTy0 i2UvNkODRGGEGuDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Luigi Rizzo Subject: [patch V2 3/3] x86/irq_remapping: Sanitize posted_msi_supported() References: <20251125214446.766096680@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 25 Nov 2025 22:50:49 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" posted_msi_supported() is a misnomer as it actually checks whether it is enabled or not. Aside of that this does not take CONFIG_X86_POSTED_MSI into account which is required to actually use it. Rename it to posted_msi_enabled() and make the return value depend on CONFIG_X86_POSTED_MSI, which allows the compiler to eliminate the related dead code and data if disabled: text data bss dec hex filename 10046 701 3296 14043 36db drivers/iommu/intel/irq_remapping.o 9904 413 3296 13613 352d drivers/iommu/intel/irq_remapping.o Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/irq_remapping.h | 5 +++-- drivers/iommu/intel/irq_remapping.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -67,9 +67,10 @@ static inline struct irq_domain *arch_ge =20 extern bool enable_posted_msi; =20 -static inline bool posted_msi_supported(void) +static inline bool posted_msi_enabled(void) { - return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); + return IS_ENABLED(CONFIG_X86_POSTED_MSI) && + enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); } =20 #else /* CONFIG_IRQ_REMAP */ --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1368,7 +1368,7 @@ static void intel_irq_remapping_prepare_ break; case X86_IRQ_ALLOC_TYPE_PCI_MSI: case X86_IRQ_ALLOC_TYPE_PCI_MSIX: - if (posted_msi_supported()) { + if (posted_msi_enabled()) { prepare_irte_posted(irte); data->irq_2_iommu.posted_msi =3D 1; } @@ -1460,7 +1460,7 @@ static int intel_irq_remapping_alloc(str =20 irq_data->hwirq =3D (index << 16) + i; irq_data->chip_data =3D ird; - if (posted_msi_supported() && + if (posted_msi_enabled() && ((info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSI) || (info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSIX))) irq_data->chip =3D &intel_ir_chip_post_msi;