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Tue, 25 Nov 2025 12:23:12 -0800 (PST) From: Francesco Lavra To: Lorenzo Bianconi , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andy Shevchenko Subject: [PATCH v3 3/9] iio: imu: st_lsm6dsx: move wakeup event enable mask to event_src Date: Tue, 25 Nov 2025 21:23:01 +0100 Message-Id: <20251125202307.4033346-4-flavra@baylibre.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125202307.4033346-1-flavra@baylibre.com> References: <20251125202307.4033346-1-flavra@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7475; i=flavra@baylibre.com; h=from:subject; bh=h/L2zhPfn2Gbd634jm4+Ta6MvmpxMumLED/InTCkazs=; b=owEB7QES/pANAwAKAe3xO3POlDZfAcsmYgBpJhADIWxqnj1iMqMM7C1xI7zGHft1pA3TgJ8Du 3wXagqwTE6JAbMEAAEKAB0WIQSGV4VPlTvcox7DFObt8TtzzpQ2XwUCaSYQAwAKCRDt8TtzzpQ2 X3tHC/4xczSi8fr+pIP4kEK6iyJ+Yvg3q24BTBTB577oKwktl+HXXniqS4L5JOQkoaDNr9CbqsG w+Pvp2Lp/QPT1xUwgnrC0Clu23KFi9ClxWqxx7o2i+7RKvQ+u7yRZmAw7qa+jXxwq/7rrNfITm8 yvhIloTrc0OiFJPKIHQlISrxJ/4Gzxzl+sxzz2h1XQjlFPnTVf1BPL56IAwrUhFNP5/VQBAsTmf rDBWlURRwzPtoUbiVjtqtmcIg6br9cZ0w2aKXhEU3OnRGt76PZWSbaPCKsWtoaA7DDi9e0Sh0UK bWbfBeHmZ/W48gv+Gz1nmzvhdRmPRp99NAtURAkOw3yA3lDd7vcx72o141c5LYNg7L7AGDQhERK 1ludZpK9vZ2ga3RhSUpkPrSaGWVyeVDugFFr3NwqBD8EkU90s6CEqLBlQW0zud945n2+BRRQ/Md vguVr3zP5CNlBLHTpI2h+RFi13TbYWQqT2bHiPRVnwovxjO7Tmc+xH6bCPKo9vJsH5geM= X-Developer-Key: i=flavra@baylibre.com; a=openpgp; fpr=8657854F953BDCA31EC314E6EDF13B73CE94365F Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mask value being assigned to the irq1_func and irq2_func fields of the irq_config struct is specific to a single event source (i.e. the wakeup event), and as such it should be separate from the definition of the interrupt function registers, which cover multiple event sources. In preparation for adding support for more event types, change the irq1_func and irq2_func type from an {address, mask} pair to an address, and move the mask value to a new field of struct st_lsm6dsx_event_src. No functional changes. Signed-off-by: Francesco Lavra Reviewed-by: Andy Shevchenko Acked-by: Lorenzo Bianconi --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 7 +- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 80 +++++++------------- 2 files changed, 30 insertions(+), 57 deletions(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_l= sm6dsx/st_lsm6dsx.h index 80bc5686454b..4200e5231950 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -249,6 +249,7 @@ enum st_lsm6dsx_event_id { =20 struct st_lsm6dsx_event_src { struct st_lsm6dsx_reg value; + u8 enable_mask; struct st_lsm6dsx_reg status; u8 status_x_mask; u8 status_y_mask; @@ -343,8 +344,8 @@ struct st_lsm6dsx_settings { struct { struct st_lsm6dsx_reg irq1; struct st_lsm6dsx_reg irq2; - struct st_lsm6dsx_reg irq1_func; - struct st_lsm6dsx_reg irq2_func; + u8 irq1_func; + u8 irq2_func; struct st_lsm6dsx_reg lir; struct st_lsm6dsx_reg clear_on_read; struct st_lsm6dsx_reg hla; @@ -443,7 +444,7 @@ struct st_lsm6dsx_hw { u8 ts_sip; u8 sip; =20 - const struct st_lsm6dsx_reg *irq_routing; + u8 irq_routing; u8 event_threshold; u8 enable_event; =20 diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu= /st_lsm6dsx/st_lsm6dsx_core.c index e8f0a2ff91be..ba163dd2ab82 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -328,14 +328,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -394,6 +388,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x1b, .mask =3D BIT(3), @@ -500,14 +495,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -566,6 +555,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x1b, .mask =3D BIT(3), @@ -702,14 +692,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -809,6 +793,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x1b, .mask =3D BIT(3), @@ -957,14 +942,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -1052,6 +1031,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x1b, .mask =3D BIT(3), @@ -1176,14 +1156,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -1239,6 +1213,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x1b, .mask =3D BIT(3), @@ -1357,14 +1332,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x03, .mask =3D BIT(4), @@ -1451,6 +1420,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status =3D { .addr =3D 0x45, .mask =3D BIT(3), @@ -1911,10 +1881,11 @@ static int st_lsm6dsx_write_raw(struct iio_dev *iio= _dev, static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state) { const struct st_lsm6dsx_reg *reg; + const struct st_lsm6dsx_event_src *src; unsigned int data; int err; =20 - if (!hw->settings->irq_config.irq1_func.addr) + if (!hw->irq_routing) return -ENOTSUPP; =20 reg =3D &hw->settings->event_settings.enable_reg; @@ -1927,9 +1898,10 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_= hw *hw, bool state) } =20 /* Enable wakeup interrupt */ - data =3D ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); - return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, - hw->irq_routing->mask, data); + src =3D &hw->settings->event_settings.sources[ST_LSM6DSX_EVENT_WAKEUP]; + data =3D ST_LSM6DSX_SHIFT_VAL(state, src->enable_mask); + return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing, + src->enable_mask, data); } =20 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, @@ -2183,11 +2155,11 @@ st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, =20 switch (drdy_pin) { case 1: - hw->irq_routing =3D &hw->settings->irq_config.irq1_func; + hw->irq_routing =3D hw->settings->irq_config.irq1_func; *drdy_reg =3D &hw->settings->irq_config.irq1; break; case 2: - hw->irq_routing =3D &hw->settings->irq_config.irq2_func; + hw->irq_routing =3D hw->settings->irq_config.irq2_func; *drdy_reg =3D &hw->settings->irq_config.irq2; break; default: --=20 2.39.5