From nobody Tue Dec 2 00:44:28 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 669D733B96F; Tue, 25 Nov 2025 20:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101829; cv=none; b=mlkrww9l+fa54/nkSoefumUjFPejGP78dM7KNG2BQzKm9eXNRJ0fFBnZlpepFxJ/PHhbfyLYsvJ5HZuICV6g8wOARQb6i1MrYT/49uvvhmGNU0Hc2Zon8DtdwLJFVc+wOMSXVqKZsp5yxBA+US2dqD+XFN+vPK5SJERn+3NkvR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101829; c=relaxed/simple; bh=EDgcFOpf3aoa20OJoxvVZuGmOunJzs1WRN5pUegudW0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JWq2fZrhwLFIEHdsvQMWNFdLhd9rz4zaXW1sHzhAYeWpBh0vKE2B1xJ6Qr42jJQnCY+g6D1Ci2pv68l9uj6hiGei3miM7bbwEAEdFhPx5U30iSQ5qDFhvRh9Kujb6Hu1qc4Lt6lwynkuvHd7jEuiWqFGzauaJh3tRUHYrA4OH6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L0hvBRr3; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L0hvBRr3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764101828; x=1795637828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EDgcFOpf3aoa20OJoxvVZuGmOunJzs1WRN5pUegudW0=; b=L0hvBRr3dtrHlAN301YS7PpKNYq50D/puaJ2jHH/WGhjmx4gNwIoHSnv 0Li2f8pprLJxMFjd7EGPyAnTKiwgOqEzs4vwTrty7v384HywEQw99yKye PugFndmTHqByoShD1+vqMmiDX15sPo+A1CN/oMDLZS3a2tFOWXsJ9LOu8 q0IvaBoud75OTOsUOMxZ1jbhiZmKefWmrLx5QxCKscCEprwStVjDSl9Sa hY8+A7ljReAZ/8TK2rD8/m02aQPtXh1xXWrmSgmM0ovES9PeFVBNU9jBo 4nzB3gBc1kgHXKCof1iNEfrE4Cvh3VXXl4piogHQHTrThXFVqzBVIi6mT g==; X-CSE-ConnectionGUID: aCixAK82TXyeKx0tH0Isuw== X-CSE-MsgGUID: n0izv5U/T96NqJYIP3GrFg== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="69990028" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="69990028" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:05 -0800 X-CSE-ConnectionGUID: EwdbiN2BTDqJ/iafwBjF5g== X-CSE-MsgGUID: bkItGjpFRJGAdGwFhSgaGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="223720984" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:03 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 4B039A2; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 2/7] spi: microchip-core: Make use of device properties Date: Tue, 25 Nov 2025 21:15:32 +0100 Message-ID: <20251125201700.1901959-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 08ccdc5f0cc9..d2d1e86568a3 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -12,9 +12,10 @@ #include #include #include +#include #include -#include #include +#include #include =20 #define MCHP_CORESPI_MAX_CS (8) @@ -296,6 +297,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, static int mchp_corespi_probe(struct platform_device *pdev) { const char *protocol =3D "motorola"; + struct device *dev =3D &pdev->dev; struct spi_controller *host; struct mchp_corespi *spi; struct resource *res; @@ -310,7 +312,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) =20 platform_set_drvdata(pdev, host); =20 - if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + if (device_property_read_u32(dev, "num-cs", &num_cs)) num_cs =3D MCHP_CORESPI_MAX_CS; =20 /* @@ -318,20 +320,18 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * CoreSPI can be configured for Motorola, TI or NSC. * The current driver supports only Motorola mode. */ - ret =3D of_property_read_string(pdev->dev.of_node, "microchip,protocol-co= nfiguration", - &protocol); - if (ret && ret !=3D -EINVAL) - return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configurat= ion\n"); - if (strcmp(protocol, "motorola") !=3D 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "CoreSPI: protocol '%s' not supported by this driver\n", - protocol); + ret =3D device_property_match_property_string(dev, "microchip,protocol-co= nfiguration", + &protocol, 1); + if (ret =3D=3D -ENOENT) + return dev_err_probe(dev, ret, "CoreSPI: protocol is not supported by th= is driver\n"); + if (ret < 0) + return dev_err_probe(dev, ret, "Error reading protocol-configuration\n"); =20 /* * Motorola mode (0-3): CFG_MOT_MODE * Mode is fixed in the IP configurator. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode"= , &mode); + ret =3D device_property_read_u32(dev, "microchip,motorola-mode", &mode); if (ret) mode =3D MCHP_CORESPI_DEFAULT_MOTOROLA_MODE; else if (mode > 3) @@ -343,7 +343,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * The hardware allows frame sizes <=3D APB data width. * However, this driver currently only supports 8-bit frames. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &= frame_size); + ret =3D device_property_read_u32(dev, "microchip,frame-size", &frame_size= ); if (!ret && frame_size !=3D 8) return dev_err_probe(&pdev->dev, -EINVAL, "CoreSPI: frame size %u not supported by this driver\n", @@ -355,7 +355,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * To prevent CS deassertion when TX FIFO drains, the ssel-active property * keeps CS asserted for the full SPI transfer. */ - assert_ssel =3D of_property_read_bool(pdev->dev.of_node, "microchip,ssel-= active"); + assert_ssel =3D device_property_read_bool(dev, "microchip,ssel-active"); if (!assert_ssel) return dev_err_probe(&pdev->dev, -EINVAL, "hardware must enable 'microchip,ssel-active' to keep CS asserted= for the SPI transfer\n"); @@ -369,9 +369,10 @@ static int mchp_corespi_probe(struct platform_device *= pdev) host->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(4, 32); host->transfer_one =3D mchp_corespi_transfer_one; host->set_cs =3D mchp_corespi_set_cs; - host->dev.of_node =3D pdev->dev.of_node; =20 - ret =3D of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_= depth); + device_set_node(&host->dev, dev_fwnode(dev)); + + ret =3D device_property_read_u32(dev, "fifo-depth", &spi->fifo_depth); if (ret) spi->fifo_depth =3D MCHP_CORESPI_DEFAULT_FIFO_DEPTH; =20 @@ -421,24 +422,23 @@ static void mchp_corespi_remove(struct platform_devic= e *pdev) * Platform driver data structure */ =20 -#if defined(CONFIG_OF) static const struct of_device_id mchp_corespi_dt_ids[] =3D { { .compatible =3D "microchip,corespi-rtl-v5" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids); -#endif =20 static struct platform_driver mchp_corespi_driver =3D { .probe =3D mchp_corespi_probe, .driver =3D { .name =3D "microchip-corespi", .pm =3D MICROCHIP_SPI_PM_OPS, - .of_match_table =3D of_match_ptr(mchp_corespi_dt_ids), + .of_match_table =3D mchp_corespi_dt_ids, }, .remove =3D mchp_corespi_remove, }; module_platform_driver(mchp_corespi_driver); + MODULE_DESCRIPTION("Microchip CoreSPI controller driver"); MODULE_AUTHOR("Prajna Rajendra Kumar "= ); MODULE_LICENSE("GPL"); --=20 2.50.1