From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4624D33ADA7; Tue, 25 Nov 2025 20:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101827; cv=none; b=E80sOhFf+8sF3qjYn3XQXiyk7B5yFLKIeRR5u4dIEwD+jiZTVDpkGZWVtgvqOsFnxrYJo5E7UgbdfC/fdn0ogH9BsA1XNCdMJBGXSliMvS/zWds5ARNDc9MQuMKQ5de3jrsySomA+S7MEg0whPeBG/rodIHRjPVOn4J134la6Ho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101827; c=relaxed/simple; bh=i348gRZwFs1j437kjQtd2OZNYyRNL6pS+Luhhms/cVs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i8rc4rMX5j9eziTql4U3O/wMMxi3T0tzPDmk1V3sT54aMKYjkSlOhnagIHU8PmZjrwoQ52Htw6lzF1M5qc5fwdZr2YDk9J2EbkmK2LhfI9AHhLJ60gD4Wr8I0B1j/EmFvRYJD5jlQcSRzvQEWzuD4aENBYpsPE4xPLyoDFAXdSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OYiBoCpw; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OYiBoCpw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764101826; x=1795637826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i348gRZwFs1j437kjQtd2OZNYyRNL6pS+Luhhms/cVs=; b=OYiBoCpw9XOWpTyqWKObdp5rBtz/Ps5NA+/s80YlT0QiuyncVYfCRO2F sgDdO+uenKilSLD+W2M7lUmgxiFmTcjk3XyQc91jxZHUQmD8uveRYzFxJ p1GF0j+DXyB8weNE2T5DsHkeI3rFtcb2IwyUzIckQGwhyyNPk74GqPHBl MIkvquBWFklR9k0V7OBZGaCo/XulB5tRi5tC38I74+2A5zKNTrgIMp4/J 8ONqppFV/ixOqmD5CTAp6zJGtkSkA5TYkk+xLbvhq8KjeE+I/IuvvgdBJ AHLLh6KWz1YiFktk5jSv8GpKG1E9LiI7ywEmYD6Xi6LebHq1TJg3YOq7e w==; X-CSE-ConnectionGUID: TT6dfz3RRFuTvYVTwlAuVw== X-CSE-MsgGUID: TR76kcVLTxqcsrU+ttnkzQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="69990024" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="69990024" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:05 -0800 X-CSE-ConnectionGUID: sEj+fqk5QMeyiqHbsenffA== X-CSE-MsgGUID: dQEvqoEmRNqyCFAXmcnKlQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="223720983" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:03 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 46821A1; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 1/7] spi: microchip-core: use min() instead of min_t() Date: Tue, 25 Nov 2025 21:15:31 +0100 Message-ID: <20251125201700.1901959-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" min_t(int, a, b) casts an 'unsigned int' to 'int'. This might lead to the cases when big number is wrongly chosen. On the other hand, the SPI transfer length is unsigned and driver uses signed type for an unknown reason. Change the type of the transfer length to be unsigned and convert use min() instead of min_t(). Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 16e0885474a0..08ccdc5f0cc9 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -74,8 +74,8 @@ struct mchp_corespi { u8 *rx_buf; u32 clk_gen; int irq; - int tx_len; - int rx_len; + unsigned int tx_len; + unsigned int rx_len; u32 fifo_depth; }; =20 @@ -214,7 +214,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "RX OVERFLOW: rxlen: %d, txlen: %d\n", + "RX OVERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -223,7 +223,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "TX UNDERFLOW: rxlen: %d, txlen: %d\n", + "TX UNDERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -283,7 +283,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, spi->rx_len =3D xfer->len; =20 while (spi->tx_len) { - int fifo_max =3D min_t(int, spi->tx_len, spi->fifo_depth); + unsigned int fifo_max =3D min(spi->tx_len, spi->fifo_depth); =20 mchp_corespi_write_fifo(spi, fifo_max); mchp_corespi_read_fifo(spi, fifo_max); --=20 2.50.1 From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 669D733B96F; Tue, 25 Nov 2025 20:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101829; cv=none; b=mlkrww9l+fa54/nkSoefumUjFPejGP78dM7KNG2BQzKm9eXNRJ0fFBnZlpepFxJ/PHhbfyLYsvJ5HZuICV6g8wOARQb6i1MrYT/49uvvhmGNU0Hc2Zon8DtdwLJFVc+wOMSXVqKZsp5yxBA+US2dqD+XFN+vPK5SJERn+3NkvR4= ARC-Message-Signature: i=1; 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d="scan'208";a="223720984" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:03 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 4B039A2; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 2/7] spi: microchip-core: Make use of device properties Date: Tue, 25 Nov 2025 21:15:32 +0100 Message-ID: <20251125201700.1901959-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 08ccdc5f0cc9..d2d1e86568a3 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -12,9 +12,10 @@ #include #include #include +#include #include -#include #include +#include #include =20 #define MCHP_CORESPI_MAX_CS (8) @@ -296,6 +297,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, static int mchp_corespi_probe(struct platform_device *pdev) { const char *protocol =3D "motorola"; + struct device *dev =3D &pdev->dev; struct spi_controller *host; struct mchp_corespi *spi; struct resource *res; @@ -310,7 +312,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) =20 platform_set_drvdata(pdev, host); =20 - if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + if (device_property_read_u32(dev, "num-cs", &num_cs)) num_cs =3D MCHP_CORESPI_MAX_CS; =20 /* @@ -318,20 +320,18 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * CoreSPI can be configured for Motorola, TI or NSC. * The current driver supports only Motorola mode. */ - ret =3D of_property_read_string(pdev->dev.of_node, "microchip,protocol-co= nfiguration", - &protocol); - if (ret && ret !=3D -EINVAL) - return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configurat= ion\n"); - if (strcmp(protocol, "motorola") !=3D 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "CoreSPI: protocol '%s' not supported by this driver\n", - protocol); + ret =3D device_property_match_property_string(dev, "microchip,protocol-co= nfiguration", + &protocol, 1); + if (ret =3D=3D -ENOENT) + return dev_err_probe(dev, ret, "CoreSPI: protocol is not supported by th= is driver\n"); + if (ret < 0) + return dev_err_probe(dev, ret, "Error reading protocol-configuration\n"); =20 /* * Motorola mode (0-3): CFG_MOT_MODE * Mode is fixed in the IP configurator. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode"= , &mode); + ret =3D device_property_read_u32(dev, "microchip,motorola-mode", &mode); if (ret) mode =3D MCHP_CORESPI_DEFAULT_MOTOROLA_MODE; else if (mode > 3) @@ -343,7 +343,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * The hardware allows frame sizes <=3D APB data width. * However, this driver currently only supports 8-bit frames. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &= frame_size); + ret =3D device_property_read_u32(dev, "microchip,frame-size", &frame_size= ); if (!ret && frame_size !=3D 8) return dev_err_probe(&pdev->dev, -EINVAL, "CoreSPI: frame size %u not supported by this driver\n", @@ -355,7 +355,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * To prevent CS deassertion when TX FIFO drains, the ssel-active property * keeps CS asserted for the full SPI transfer. */ - assert_ssel =3D of_property_read_bool(pdev->dev.of_node, "microchip,ssel-= active"); + assert_ssel =3D device_property_read_bool(dev, "microchip,ssel-active"); if (!assert_ssel) return dev_err_probe(&pdev->dev, -EINVAL, "hardware must enable 'microchip,ssel-active' to keep CS asserted= for the SPI transfer\n"); @@ -369,9 +369,10 @@ static int mchp_corespi_probe(struct platform_device *= pdev) host->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(4, 32); host->transfer_one =3D mchp_corespi_transfer_one; host->set_cs =3D mchp_corespi_set_cs; - host->dev.of_node =3D pdev->dev.of_node; =20 - ret =3D of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_= depth); + device_set_node(&host->dev, dev_fwnode(dev)); + + ret =3D device_property_read_u32(dev, "fifo-depth", &spi->fifo_depth); if (ret) spi->fifo_depth =3D MCHP_CORESPI_DEFAULT_FIFO_DEPTH; =20 @@ -421,24 +422,23 @@ static void mchp_corespi_remove(struct platform_devic= e *pdev) * Platform driver data structure */ =20 -#if defined(CONFIG_OF) static const struct of_device_id mchp_corespi_dt_ids[] =3D { { .compatible =3D "microchip,corespi-rtl-v5" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids); 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d="scan'208";a="192836171" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 25 Nov 2025 12:17:03 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 4F424A3; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 3/7] spi: microchip-core: Refactor FIFO read and write handlers Date: Tue, 25 Nov 2025 21:15:33 +0100 Message-ID: <20251125201700.1901959-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make both handlers to be shorter and easier to understand. While at it, unify their style. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 32 +++++++++------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index d2d1e86568a3..9620aa886912 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -92,21 +92,14 @@ static inline void mchp_corespi_disable(struct mchp_cor= espi *spi) static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi, u32 fi= fo_max) { for (int i =3D 0; i < fifo_max; i++) { - u32 data; - while (readb(spi->regs + MCHP_CORESPI_REG_STAT) & MCHP_CORESPI_STATUS_RXFIFO_EMPTY) ; =20 - data =3D readb(spi->regs + MCHP_CORESPI_REG_RXDATA); + if (spi->rx_buf) + *spi->rx_buf++ =3D readb(spi->regs + MCHP_CORESPI_REG_RXDATA); =20 spi->rx_len--; - if (!spi->rx_buf) - continue; - - *spi->rx_buf =3D data; - - spi->rx_buf++; } } =20 @@ -128,23 +121,18 @@ static void mchp_corespi_disable_ints(struct mchp_cor= espi *spi) =20 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 f= ifo_max) { - int i =3D 0; - - while ((i < fifo_max) && - !(readb(spi->regs + MCHP_CORESPI_REG_STAT) & - MCHP_CORESPI_STATUS_TXFIFO_FULL)) { - u32 word; - - word =3D spi->tx_buf ? *spi->tx_buf : 0xaa; - writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA); + for (int i =3D 0; i < fifo_max; i++) { + if (readb(spi->regs + MCHP_CORESPI_REG_STAT) & + MCHP_CORESPI_STATUS_TXFIFO_FULL) + break; =20 if (spi->tx_buf) - spi->tx_buf++; + writeb(*spi->tx_buf++, spi->regs + MCHP_CORESPI_REG_TXDATA); + else + writeb(0xaa, spi->regs + MCHP_CORESPI_REG_TXDATA); =20 - i++; + spi->tx_len--; } - - spi->tx_len -=3D i; } =20 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) --=20 2.50.1 From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D695E33B958; Tue, 25 Nov 2025 20:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101828; cv=none; b=Tnun8Oqw/4qirXLk17mFUjqGN6Pftiu0ifkrOI4P7LVE+Zri01gu5EI9pBm4GqJGmZGBYccz21NXjNJIZsRbbzrf8eXaG9U29a7MYA4Gky64Gd89X8Tayxc/F4GOQs4nXwRb7HHR5eVS1P+ZbeDOgICGbznX1VFcUp1kVGP3hWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101828; c=relaxed/simple; bh=g7W+a0KDvDNZx8EWxNLukegMDKmdtcKPYfpsSu925Os=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FdflcZg6ueQ6aaI5p4HIX/KrDoKY2l0O/Cm3oNkZ2IeCI5xdINlk5MLNh+z82jggNH9GjVfiSEAIgMUcnf96aOKAFT+XTGy7yopNKKaY5spJszlFcda/Bl/ye86c75c/fDOHbE51G506iN9PXrJp2HyZ304oP4xYV873f/Xp43s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hcL7USQz; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hcL7USQz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764101827; x=1795637827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g7W+a0KDvDNZx8EWxNLukegMDKmdtcKPYfpsSu925Os=; b=hcL7USQznq6U2ldIS2mqHcvvW1blToKWnjRpZpa+IzLbmQYcZjlC21An ArtnZ8C6NEFU3wkZCPHedw2lb5NTLSnA48ak/77QAZzgNQRzY7VwRYr9L NCjt6WKCmZxGHZsvNHzh+/6uGttQpV95ECAGlUDVHLYbRpmLpStyYJ1s4 63EMAUnLS8mKBME487FNgiKhzaTvzcvWwoU/lWM9jAn2LWH5diVNhvnih BunT1OVfgGhM1Ucf7xynEwTzMO2LONwi1k369uHEmMIUXFIuW3/PW8+jV pc0Qq3qBgINAFIBN2K7IEflUd9oa/3ELcTwSjMyd9CV3Owi+ED4+xDRq5 g==; X-CSE-ConnectionGUID: ePeINc8TSKSbrgZE4xNXKg== X-CSE-MsgGUID: 16907jWjS2i+NVRwmnUi4A== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="69990026" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="69990026" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:05 -0800 X-CSE-ConnectionGUID: 3wUjezJsTHSVB77fsgUjLA== X-CSE-MsgGUID: ZrBFGRlCQT+Og3T8FVdqyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="223720982" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:03 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 533B0A4; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 4/7] spi: microchip-core: Replace dead code (-ENOMEM error message) Date: Tue, 25 Nov 2025 21:15:34 +0100 Message-ID: <20251125201700.1901959-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" First of all, the convention in the kernel that we do not issue error messages for -ENOMEM. Second, it's ignored by dev_err_probe(). Replace dead code by a simple return statement. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 9620aa886912..dbbfb395c272 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -295,8 +295,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); if (!host) - return dev_err_probe(&pdev->dev, -ENOMEM, - "unable to allocate host for SPI controller\n"); + return -ENOMEM; =20 platform_set_drvdata(pdev, host); =20 --=20 2.50.1 From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB98933BBA7; Tue, 25 Nov 2025 20:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101829; cv=none; b=nsJM9IsP4+DscyzM/l6z3JqUqLY5VRZcayW88QjZGXLRD3yD02NRXsqKnX2/MMfKrK5Qe+pDyXU/frCE9SF9izLYz+vZg3RVL9msGNKIb2hENTBd5MG8CGaUzzoxX6j3Zlk869m6tm7KVaCXRoxk7i4N6TTa4QX9PgUjsbljTLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101829; c=relaxed/simple; bh=d4PsKh6CfSpqCwuGvqiqnLvYump1yPnP29Hq84e6xbw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qxfcj50WMgRsDwX4ogbvl95pyA7frHbX4djnky6S3rKPTiZZhjA38LqCXlGnylL40+iy/tzhjadk8hkOdQDU6sT/cNtLibaIMC4W8Xaziyi5Kkh5k5sSXFRl+Qwkh59qmN//2jIjL7FMBSKmhWCsPWHgtHv0Iq0TQueySqY3FOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hKOFPxSQ; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hKOFPxSQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764101828; x=1795637828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d4PsKh6CfSpqCwuGvqiqnLvYump1yPnP29Hq84e6xbw=; b=hKOFPxSQECO9nC0ArxNIDEmFFIN5nWSeKG+Ic8oSs9GtVs+DMOlMKJqj GLnW7pF4bwPHMitG3naYa/SDu5fkYI/UgjqBQ5GJdtAnNrZMnIU0RGo0H Cetx8VFPFE/B3vyl86VbOcQEGKyRhGEekze4KARjHa5NJB/OweJfksSo8 YfyYkKYlN+LV20gdH9q4VIZuXWqPqBCsNHtRKgvyXXByItIozYGdOqqBW /9jA9+b0xeZNDu373V8xwRKFsI+m5cjHQgQKx2JevYzEuhuJpV/qzGQZ9 IWveZ9ANNk5Ss/CpFUKO6k8KjqQw+DdxjNclwC6eHAacQKyiDIP0YX3ed w==; X-CSE-ConnectionGUID: Ry3swFX7Qh2/vpJxASdDZQ== X-CSE-MsgGUID: OxJw/Vc+R5yHqqnQfQwLtQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="53699533" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="53699533" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:07 -0800 X-CSE-ConnectionGUID: JvFPd3MgSBywod2MiG1YfA== X-CSE-MsgGUID: gYvEP7leTEmX8NuU7DKh0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="192836181" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 25 Nov 2025 12:17:05 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 5751BA5; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 5/7] spi: microchip-core: Utilise temporary variable for struct device Date: Tue, 25 Nov 2025 21:15:35 +0100 Message-ID: <20251125201700.1901959-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We have a temporary variable to keep a pointer to struct device. Utilise it where it makes sense. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index dbbfb395c272..68b136157fac 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -293,7 +293,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) bool assert_ssel; int ret =3D 0; =20 - host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); + host =3D devm_spi_alloc_host(dev, sizeof(*spi)); if (!host) return -ENOMEM; =20 @@ -322,7 +322,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) if (ret) mode =3D MCHP_CORESPI_DEFAULT_MOTOROLA_MODE; else if (mode > 3) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "invalid 'microchip,motorola-mode' value %u\n", mode); =20 /* @@ -332,7 +332,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) */ ret =3D device_property_read_u32(dev, "microchip,frame-size", &frame_size= ); if (!ret && frame_size !=3D 8) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "CoreSPI: frame size %u not supported by this driver\n", frame_size); =20 @@ -344,7 +344,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) */ assert_ssel =3D device_property_read_bool(dev, "microchip,ssel-active"); if (!assert_ssel) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "hardware must enable 'microchip,ssel-active' to keep CS asserted= for the SPI transfer\n"); =20 spi =3D spi_controller_get_devdata(host); @@ -371,24 +371,21 @@ static int mchp_corespi_probe(struct platform_device = *pdev) if (spi->irq < 0) return spi->irq; =20 - ret =3D devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, - IRQF_SHARED, dev_name(&pdev->dev), host); + ret =3D devm_request_irq(dev, spi->irq, mchp_corespi_interrupt, IRQF_SHAR= ED, + dev_name(dev), host); if (ret) - return dev_err_probe(&pdev->dev, ret, - "could not request irq\n"); + return dev_err_probe(dev, ret, "could not request irq\n"); =20 - spi->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + spi->clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(spi->clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), - "could not get clk\n"); + return dev_err_probe(dev, PTR_ERR(spi->clk), "could not get clk\n"); =20 mchp_corespi_init(host, spi); =20 - ret =3D devm_spi_register_controller(&pdev->dev, host); + ret =3D devm_spi_register_controller(dev, host); if (ret) { mchp_corespi_disable(spi); - return dev_err_probe(&pdev->dev, ret, - "unable to register host for CoreSPI controller\n"); + return dev_err_probe(dev, ret, "unable to register host for CoreSPI cont= roller\n"); } =20 return 0; --=20 2.50.1 From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72FE33C190; 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X-CSE-ConnectionGUID: N+fzLTSsTR2i0WXBscxM6w== X-CSE-MsgGUID: 9qIc46zuRCWbTfxHiCMAkQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="69990035" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="69990035" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:07 -0800 X-CSE-ConnectionGUID: EXIQCvywTjqoaUc/RZ7eRQ== X-CSE-MsgGUID: iqLyzyxDS0eT3MjWOIjXsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="223720990" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:05 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 5B22CA6; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 6/7] spi: microchip-core: Use SPI_MODE_X_MASK Date: Tue, 25 Nov 2025 21:15:36 +0100 Message-ID: <20251125201700.1901959-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use SPI_MODE_X_MASK instead of open coded variant. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 68b136157fac..2d7ee556eafd 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -149,8 +149,6 @@ static void mchp_corespi_set_cs(struct spi_device *spi,= bool disable) =20 static int mchp_corespi_setup(struct spi_device *spi) { - u32 dev_mode =3D spi->mode & (SPI_CPOL | SPI_CPHA); - if (spi_get_csgpiod(spi, 0)) return 0; =20 @@ -159,7 +157,7 @@ static int mchp_corespi_setup(struct spi_device *spi) return -EOPNOTSUPP; } =20 - if (dev_mode & ~spi->controller->mode_bits) { + if (spi->mode & SPI_MODE_X_MASK & ~spi->controller->mode_bits) { dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Moto= rola mode\n"); return -EINVAL; } --=20 2.50.1 From nobody Tue Dec 2 00:02:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09DB833C501; Tue, 25 Nov 2025 20:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101830; cv=none; b=hAJq5elLNMcomUtB1UtMbVxvhoK5eYtdbCN1t3hPROoOxH68IM07Fj11vwjcmSBaXyqBIbJW10mi3VqiyUqZAJZXiTrtjJRe26CMpcjvRSJpX/GoKEuns93UnpiYHO3uqiO4IYphbDBBr4ifeVOH1gztbY+930FWyLM6IIs5C74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764101830; c=relaxed/simple; bh=dVygpC8z48vE1wJBxn3Ie6b0CmMawZBV6k+F8SVts2M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DSnwSzOi9DpQ5gThEMWQ2ZG5ZBtEsgo5xUifKlF6IWxeY6+cPHF/Vv0PavTHF4WNaiRCK8j/Dc8iSr+Zq7eqTzUIpPZDkncaZVm7G49ikrHH8QcC3op2iJ1dMDgeUTnuzm7KmGiZjAU4wcFvmJajvI2AsjwU0fsq062VOG2is7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OXcu6u6H; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OXcu6u6H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764101829; x=1795637829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dVygpC8z48vE1wJBxn3Ie6b0CmMawZBV6k+F8SVts2M=; b=OXcu6u6HWHXDi2HRIva3nEbobR/DHHOzLdAuIo2NPh0Uq/hiOXzmUJn6 Q1/RM20nG+V8qJDe3NYJ2v3mvNyeWvIEFvtu9WaRoV1m2MH7I4Y8nEq0k QJlvp8bWnXl3usx/iwUBpss3Y9l04gkRaySPLAY5nqo2bs6asMUUZW0Ns xT1af0l9gg2PRedPjpAi124SSoxLvzZg+S5JuNZun6Upw/4nFigvhAwEy bOEsrJvqStVjQ7xfSUzV+2lDG4/754jYR92yV1eYFc/dqfVs81e7FufjY e3qFFnyPSbPaPtMSiZsSgZ72vU5fEXKsLzUId0dCNsmBTZfHkouYHkLpk w==; X-CSE-ConnectionGUID: bvjVzgF/QSexsnIe8OB67w== X-CSE-MsgGUID: rKUO/oTGSo+hIYEPKin6nA== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="69990038" X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="69990038" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 12:17:07 -0800 X-CSE-ConnectionGUID: ftkyYuzzRmGy3iSy6b2AQQ== X-CSE-MsgGUID: pBcYdko0T3ule96QtWrxPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,226,1758610800"; d="scan'208";a="223720991" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 25 Nov 2025 12:17:05 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 5EA55A7; Tue, 25 Nov 2025 21:17:02 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 7/7] spi: microchip-core: Remove unneeded PM related macro Date: Tue, 25 Nov 2025 21:15:37 +0100 Message-ID: <20251125201700.1901959-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> References: <20251125201700.1901959-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Static declaration by default are 0 or NULL, no need to initialise them explicitly. Remove unneeded PM related macro. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 2d7ee556eafd..d09daa25984c 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -398,8 +398,6 @@ static void mchp_corespi_remove(struct platform_device = *pdev) mchp_corespi_disable(spi); } =20 -#define MICROCHIP_SPI_PM_OPS (NULL) - /* * Platform driver data structure */ @@ -414,7 +412,6 @@ static struct platform_driver mchp_corespi_driver =3D { .probe =3D mchp_corespi_probe, .driver =3D { .name =3D "microchip-corespi", - .pm =3D MICROCHIP_SPI_PM_OPS, .of_match_table =3D mchp_corespi_dt_ids, }, .remove =3D mchp_corespi_remove, --=20 2.50.1