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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:38.6727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d43bd22-7b82-4466-d18f-08de2c4859c2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9422 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Take out the implementation to map the VMA to the PTE/PMD/PUD as a separate function. Export the function to be used by nvgrace-gpu module. cc: Shameer Kolothum cc: Alex Williamson cc: Jason Gunthorpe Reviewed-by: Shameer Kolothum Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/vfio_pci_core.c | 50 ++++++++++++++++++++------------ include/linux/vfio_pci_core.h | 3 ++ 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_c= ore.c index 7dcf5439dedc..c445a53ee12e 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1640,31 +1640,21 @@ static unsigned long vma_to_pfn(struct vm_area_stru= ct *vma) return (pci_resource_start(vdev->pdev, index) >> PAGE_SHIFT) + pgoff; } =20 -static vm_fault_t vfio_pci_mmap_huge_fault(struct vm_fault *vmf, - unsigned int order) +vm_fault_t vfio_pci_vmf_insert_pfn(struct vfio_pci_core_device *vdev, + struct vm_fault *vmf, + unsigned long pfn, + unsigned int order) { - struct vm_area_struct *vma =3D vmf->vma; - struct vfio_pci_core_device *vdev =3D vma->vm_private_data; - unsigned long addr =3D vmf->address & ~((PAGE_SIZE << order) - 1); - unsigned long pgoff =3D (addr - vma->vm_start) >> PAGE_SHIFT; - unsigned long pfn =3D vma_to_pfn(vma) + pgoff; - vm_fault_t ret =3D VM_FAULT_SIGBUS; + vm_fault_t ret; =20 - if (order && (addr < vma->vm_start || - addr + (PAGE_SIZE << order) > vma->vm_end || - pfn & ((1 << order) - 1))) { - ret =3D VM_FAULT_FALLBACK; - goto out; - } - - down_read(&vdev->memory_lock); + lockdep_assert_held_read(&vdev->memory_lock); =20 if (vdev->pm_runtime_engaged || !__vfio_pci_memory_enabled(vdev)) - goto out_unlock; + return VM_FAULT_SIGBUS; =20 switch (order) { case 0: - ret =3D vmf_insert_pfn(vma, vmf->address, pfn); + ret =3D vmf_insert_pfn(vmf->vma, vmf->address, pfn); break; #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP case PMD_ORDER: @@ -1680,7 +1670,29 @@ static vm_fault_t vfio_pci_mmap_huge_fault(struct vm= _fault *vmf, ret =3D VM_FAULT_FALLBACK; } =20 -out_unlock: + return ret; +} +EXPORT_SYMBOL_GPL(vfio_pci_vmf_insert_pfn); + +static vm_fault_t vfio_pci_mmap_huge_fault(struct vm_fault *vmf, + unsigned int order) +{ + struct vm_area_struct *vma =3D vmf->vma; + struct vfio_pci_core_device *vdev =3D vma->vm_private_data; + unsigned long addr =3D vmf->address & ~((PAGE_SIZE << order) - 1); + unsigned long pgoff =3D (addr - vma->vm_start) >> PAGE_SHIFT; + unsigned long pfn =3D vma_to_pfn(vma) + pgoff; + vm_fault_t ret =3D VM_FAULT_SIGBUS; + + if (order && (addr < vma->vm_start || + addr + (PAGE_SIZE << order) > vma->vm_end || + pfn & ((1 << order) - 1))) { + ret =3D VM_FAULT_FALLBACK; + goto out; + } + + down_read(&vdev->memory_lock); + ret =3D vfio_pci_vmf_insert_pfn(vdev, vmf, pfn, order); up_read(&vdev->memory_lock); out: dev_dbg_ratelimited(&vdev->pdev->dev, diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index f541044e42a2..6f7c6c0d4278 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -119,6 +119,9 @@ ssize_t vfio_pci_core_read(struct vfio_device *core_vde= v, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __us= er *buf, size_t count, loff_t *ppos); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:35.3335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0622f0d-47eb-4c87-7941-08de2c4857bc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0F9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6293 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal NVIDIA's Grace based systems have large device memory. The device memory is mapped as VM_PFNMAP in the VMM VMA. The nvgrace-gpu module could make use of the huge PFNMAP support added in mm [1]. To make use of the huge pfnmap support, fault/huge_fault ops based mapping mechanism needs to be implemented. Currently nvgrace-gpu module relies on remap_pfn_range to do the mapping during VM bootup. Replace it to instead rely on fault and use vfio_pci_vmf_insert_pfn to setup the mapping. Moreover to enable huge pfnmap, nvgrace-gpu module is updated by adding huge_fault ops implementation. The implementation establishes mapping according to the order request. Note that if the PFN or the VMA address is unaligned to the order, the mapping fallbacks to the PTE level. Link: https://lore.kernel.org/all/20240826204353.2228736-1-peterx@redhat.co= m/ [1] cc: Shameer Kolothum cc: Alex Williamson cc: Jason Gunthorpe cc: Vikram Sethi Signed-off-by: Ankit Agrawal Reviewed-by: Zhi Wang --- drivers/vfio/pci/nvgrace-gpu/main.c | 84 +++++++++++++++++++++-------- 1 file changed, 62 insertions(+), 22 deletions(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index e346392b72f6..8a982310b188 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -130,6 +130,62 @@ static void nvgrace_gpu_close_device(struct vfio_devic= e *core_vdev) vfio_pci_core_close_device(core_vdev); } =20 +static unsigned long addr_to_pgoff(struct vm_area_struct *vma, + unsigned long addr) +{ + u64 pgoff =3D vma->vm_pgoff & + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); + + return ((addr - vma->vm_start) >> PAGE_SHIFT) + pgoff; +} + +static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(struct vm_fault *vmf, + unsigned int order) +{ + struct vm_area_struct *vma =3D vmf->vma; + struct nvgrace_gpu_pci_core_device *nvdev =3D vma->vm_private_data; + struct vfio_pci_core_device *vdev =3D &nvdev->core_device; + unsigned int index =3D + vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); + vm_fault_t ret =3D VM_FAULT_SIGBUS; + struct mem_region *memregion; + unsigned long pfn, addr; + + memregion =3D nvgrace_gpu_memregion(index, nvdev); + if (!memregion) + return ret; + + addr =3D vmf->address & ~((PAGE_SIZE << order) - 1); + pfn =3D PHYS_PFN(memregion->memphys) + addr_to_pgoff(vma, addr); + + if (order && (addr < vma->vm_start || + addr + (PAGE_SIZE << order) > vma->vm_end || + pfn & ((1 << order) - 1))) + return VM_FAULT_FALLBACK; + + scoped_guard(rwsem_read, &vdev->memory_lock) + ret =3D vfio_pci_vmf_insert_pfn(vdev, vmf, pfn, order); + + dev_dbg_ratelimited(&vdev->pdev->dev, + "%s order =3D %d pfn 0x%lx: 0x%x\n", + __func__, order, pfn, + (unsigned int)ret); + + return ret; +} + +static vm_fault_t nvgrace_gpu_vfio_pci_fault(struct vm_fault *vmf) +{ + return nvgrace_gpu_vfio_pci_huge_fault(vmf, 0); +} + +static const struct vm_operations_struct nvgrace_gpu_vfio_pci_mmap_ops =3D= { + .fault =3D nvgrace_gpu_vfio_pci_fault, +#ifdef CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP + .huge_fault =3D nvgrace_gpu_vfio_pci_huge_fault, +#endif +}; + static int nvgrace_gpu_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma) { @@ -137,10 +193,8 @@ static int nvgrace_gpu_mmap(struct vfio_device *core_v= dev, container_of(core_vdev, struct nvgrace_gpu_pci_core_device, core_device.vdev); struct mem_region *memregion; - unsigned long start_pfn; u64 req_len, pgoff, end; unsigned int index; - int ret =3D 0; =20 index =3D vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); =20 @@ -157,17 +211,18 @@ static int nvgrace_gpu_mmap(struct vfio_device *core_= vdev, ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); =20 if (check_sub_overflow(vma->vm_end, vma->vm_start, &req_len) || - check_add_overflow(PHYS_PFN(memregion->memphys), pgoff, &start_pfn) || check_add_overflow(PFN_PHYS(pgoff), req_len, &end)) return -EOVERFLOW; =20 /* - * Check that the mapping request does not go beyond available device - * memory size + * Check that the mapping request does not go beyond the exposed + * device memory size. */ if (end > memregion->memlength) return -EINVAL; =20 + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); + /* * The carved out region of the device memory needs the NORMAL_NC * property. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:41.2143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 218fa2c4-d5f6-464b-f9b9-08de2c485b4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6024 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Remove code duplication in vfio_pci_core_mmap by calling vfio_pci_core_setup_barmap to perform the bar mapping. cc: Donald Dutile Reviewed-by: Shameer Kolothum Suggested-by: Alex Williamson Signed-off-by: Ankit Agrawal Reviewed-by: Zhi Wang --- drivers/vfio/pci/vfio_pci_core.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_c= ore.c index c445a53ee12e..3cc799eb75ea 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1761,18 +1761,9 @@ int vfio_pci_core_mmap(struct vfio_device *core_vdev= , struct vm_area_struct *vma * Even though we don't make use of the barmap for the mmap, * we need to request the region and the barmap tracks that. */ - if (!vdev->barmap[index]) { - ret =3D pci_request_selected_regions(pdev, - 1 << index, "vfio-pci"); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:38.1198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b86e6a9-730c-4ae9-3378-08de2c485967 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9409 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Split the function that check for the GPU device being ready on the probe. Move the code to wait for the GPU to be ready through BAR0 register reads to a separate function. This would help reuse the code. Reviewed-by: Shameer Kolothum Signed-off-by: Ankit Agrawal Reviewed-by: Zhi Wang --- drivers/vfio/pci/nvgrace-gpu/main.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index 8a982310b188..2b736cb82f38 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -130,6 +130,20 @@ static void nvgrace_gpu_close_device(struct vfio_devic= e *core_vdev) vfio_pci_core_close_device(core_vdev); } =20 +static int nvgrace_gpu_wait_device_ready(void __iomem *io) +{ + unsigned long timeout =3D jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS); + + do { + if ((ioread32(io + C2C_LINK_BAR0_OFFSET) =3D=3D STATUS_READY) && + (ioread32(io + HBM_TRAINING_BAR0_OFFSET) =3D=3D STATUS_READY)) + return 0; + msleep(POLL_QUANTUM_MS); + } while (!time_after(jiffies, timeout)); + + return -ETIME; +} + static unsigned long addr_to_pgoff(struct vm_area_struct *vma, unsigned long addr) { @@ -933,9 +947,8 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct pci_dev *= pdev) * Ensure that the BAR0 region is enabled before accessing the * registers. */ -static int nvgrace_gpu_wait_device_ready(struct pci_dev *pdev) +static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev) { - unsigned long timeout =3D jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:43.2606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20a8da58-a0d4-481c-6078-08de2c485c77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6025 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Introduce a new flag reset_done to notify that the GPU has just been reset and the mapping to the GPU memory is zapped. Implement the reset_done handler to set this new variable. It will be used later in the patches to wait for the GPU memory to be ready before doing any mapping or access. cc: Jason Gunthorpe Suggested-by: Alex Williamson Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/nvgrace-gpu/main.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index 2b736cb82f38..7d5544280ed2 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -58,6 +58,8 @@ struct nvgrace_gpu_pci_core_device { /* Lock to control device memory kernel mapping */ struct mutex remap_lock; bool has_mig_hw_bug; + /* GPU has just been reset */ + bool reset_done; }; =20 static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vd= ev) @@ -1047,12 +1049,27 @@ static const struct pci_device_id nvgrace_gpu_vfio_= pci_table[] =3D { =20 MODULE_DEVICE_TABLE(pci, nvgrace_gpu_vfio_pci_table); =20 +static void nvgrace_gpu_vfio_pci_reset_done(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *core_device =3D dev_get_drvdata(&pdev->dev); + struct nvgrace_gpu_pci_core_device *nvdev =3D + container_of(core_device, struct nvgrace_gpu_pci_core_device, + core_device); + + nvdev->reset_done =3D true; +} + +static const struct pci_error_handlers nvgrace_gpu_vfio_pci_err_handlers = =3D { + .reset_done =3D nvgrace_gpu_vfio_pci_reset_done, + .error_detected =3D vfio_pci_core_aer_err_detected, +}; + static struct pci_driver nvgrace_gpu_vfio_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D nvgrace_gpu_vfio_pci_table, .probe =3D nvgrace_gpu_probe, .remove =3D nvgrace_gpu_remove, - .err_handler =3D &vfio_pci_core_err_handlers, + .err_handler =3D &nvgrace_gpu_vfio_pci_err_handlers, .driver_managed_dma =3D true, }; =20 --=20 2.34.1 From nobody Tue Dec 2 00:04:39 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010005.outbound.protection.outlook.com [52.101.56.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7DC432BF46; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 17:30:43.6043 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a72c2a4f-8920-4baf-4de5-08de2c485cab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7311 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Speculative prefetches from CPU to GPU memory until the GPU is ready after reset can cause harmless corrected RAS events to be logged on Grace systems. It is thus preferred that the mapping not be re-established until the GPU is ready post reset. The GPU readiness can be checked through BAR0 registers similar to the checking at the time of device probe. It can take several seconds for the GPU to be ready. So it is desirable that the time overlaps as much of the VM startup as possible to reduce impact on the VM bootup time. The GPU readiness state is thus checked on the first fault/huge_fault request or read/write access which amortizes the GPU readiness time. The first fault and read/write checks the GPU state when the reset_done flag - which denotes whether the GPU has just been reset. The memory_lock is taken across map/access to avoid races with GPU reset. cc: Shameer Kolothum cc: Alex Williamson cc: Jason Gunthorpe cc: Vikram Sethi Suggested-by: Alex Williamson Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/nvgrace-gpu/main.c | 66 ++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 7 deletions(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index 7d5544280ed2..f9cea19093fa 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -104,6 +104,17 @@ static int nvgrace_gpu_open_device(struct vfio_device = *core_vdev) mutex_init(&nvdev->remap_lock); } =20 + /* + * GPU readiness is checked by reading the BAR0 registers. + * + * ioremap BAR0 to ensure that the BAR0 mapping is present before + * register reads on first fault before establishing any GPU + * memory mapping. + */ + ret =3D vfio_pci_core_setup_barmap(vdev, 0); + if (ret) + return ret; + vfio_pci_core_finish_enable(vdev); =20 return 0; @@ -146,6 +157,31 @@ static int nvgrace_gpu_wait_device_ready(void __iomem = *io) return -ETIME; } =20 +/* + * If the GPU memory is accessed by the CPU while the GPU is not ready + * after reset, it can cause harmless corrected RAS events to be logged. + * Make sure the GPU is ready before establishing the mappings. + */ +static int +nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev) +{ + struct vfio_pci_core_device *vdev =3D &nvdev->core_device; + int ret; + + lockdep_assert_held_read(&vdev->memory_lock); + + if (!nvdev->reset_done) + return 0; + + ret =3D nvgrace_gpu_wait_device_ready(vdev->barmap[0]); + if (ret) + return ret; + + nvdev->reset_done =3D false; + + return 0; +} + static unsigned long addr_to_pgoff(struct vm_area_struct *vma, unsigned long addr) { @@ -179,8 +215,12 @@ static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(stru= ct vm_fault *vmf, pfn & ((1 << order) - 1))) return VM_FAULT_FALLBACK; =20 - scoped_guard(rwsem_read, &vdev->memory_lock) + scoped_guard(rwsem_read, &vdev->memory_lock) { + if (nvgrace_gpu_check_device_ready(nvdev)) + return ret; + ret =3D vfio_pci_vmf_insert_pfn(vdev, vmf, pfn, order); + } =20 dev_dbg_ratelimited(&vdev->pdev->dev, "%s order =3D %d pfn 0x%lx: 0x%x\n", @@ -592,9 +632,15 @@ nvgrace_gpu_read_mem(struct nvgrace_gpu_pci_core_devic= e *nvdev, else mem_count =3D min(count, memregion->memlength - (size_t)offset); =20 - ret =3D nvgrace_gpu_map_and_read(nvdev, buf, mem_count, ppos); - if (ret) - return ret; + scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) { + ret =3D nvgrace_gpu_check_device_ready(nvdev); + if (ret) + return ret; + + ret =3D nvgrace_gpu_map_and_read(nvdev, buf, mem_count, ppos); + if (ret) + return ret; + } =20 /* * Only the device memory present on the hardware is mapped, which may @@ -712,9 +758,15 @@ nvgrace_gpu_write_mem(struct nvgrace_gpu_pci_core_devi= ce *nvdev, */ mem_count =3D min(count, memregion->memlength - (size_t)offset); =20 - ret =3D nvgrace_gpu_map_and_write(nvdev, buf, mem_count, ppos); - if (ret) - return ret; + scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) { + ret =3D nvgrace_gpu_check_device_ready(nvdev); + if (ret) + return ret; + + ret =3D nvgrace_gpu_map_and_write(nvdev, buf, mem_count, ppos); + if (ret) + return ret; + } =20 exitfn: *ppos +=3D count; --=20 2.34.1