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charset="utf-8" Add support for clock provider. Acked-by: Conor Dooley Signed-off-by: Antoniu Miclaus --- changes in v3: - fix commit title - drop _clk suffix for clock names - drop additional example and update the existing one .../devicetree/bindings/iio/frequency/adi,adf4377.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.ya= ml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml index 5f950ee9aec7..be69b9c68e74 100644 --- a/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml @@ -40,6 +40,12 @@ properties: items: - const: ref_in =20 + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + chip-enable-gpios: description: GPIO that controls the Chip Enable Pin. @@ -97,6 +103,8 @@ examples: spi-max-frequency =3D <10000000>; clocks =3D <&adf4377_ref_in>; clock-names =3D "ref_in"; + #clock-cells =3D <0>; + clock-output-names =3D "adf4377"; }; }; ... --=20 2.43.0 From nobody Tue Dec 2 00:02:29 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DFFC1DF246; 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charset="utf-8" Add clk provider feature for the adf4377. Even though the driver was sent as an IIO driver in most cases the device is actually seen as a clock provider. This patch aims to cover actual usecases requested by users in order to completely control the output frequencies from userspace. Signed-off-by: Antoniu Miclaus --- Changes in v3: - Replace .is_enabled clock operation with .is_prepared - Use modern devm_clk_hw_register() instead of devm_clk_register() - Switch to clk_parent_data with fw_name instead of parent_names array - Use devm_of_clk_add_hw_provider() with of_clk_hw_simple_get for modern D= T integration - Fix indentation alignment in adf4377_clk_recalc_rate function parameter - Remove manual clock provider cleanup by using devm_* variants drivers/iio/frequency/adf4377.c | 119 +++++++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 2 deletions(-) diff --git a/drivers/iio/frequency/adf4377.c b/drivers/iio/frequency/adf437= 7.c index 08833b7035e4..045747351ed7 100644 --- a/drivers/iio/frequency/adf4377.c +++ b/drivers/iio/frequency/adf4377.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -435,9 +436,14 @@ struct adf4377_state { struct gpio_desc *gpio_ce; struct gpio_desc *gpio_enclk1; struct gpio_desc *gpio_enclk2; + struct clk *clk; + struct clk *clkout; + struct clk_hw hw; u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; =20 +#define to_adf4377_state(h) container_of(h, struct adf4377_state, hw) + static const char * const adf4377_muxout_modes[] =3D { [ADF4377_MUXOUT_HIGH_Z] =3D "high_z", [ADF4377_MUXOUT_LKDET] =3D "lock_detect", @@ -929,6 +935,108 @@ static int adf4377_freq_change(struct notifier_block = *nb, unsigned long action, return NOTIFY_OK; } =20 +static unsigned long adf4377_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + u64 freq; + int ret; + + ret =3D adf4377_get_freq(st, &freq); + if (ret) + return 0; + + return freq; +} + +static int adf4377_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + return adf4377_set_freq(st, rate); +} + +static int adf4377_clk_prepare(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + return regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | + ADF4377_001A_PD_CLKOUT2_MSK, + FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | + FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); +} + +static void adf4377_clk_unprepare(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | + ADF4377_001A_PD_CLKOUT2_MSK, + FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 1) | + FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 1)); +} + +static int adf4377_clk_is_prepared(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + unsigned int readval; + int ret; + + ret =3D regmap_read(st->regmap, 0x1a, &readval); + if (ret) + return ret; + + return !(readval & (ADF4377_001A_PD_CLKOUT1_MSK | ADF4377_001A_PD_CLKOUT2= _MSK)); +} + +static const struct clk_ops adf4377_clk_ops =3D { + .recalc_rate =3D adf4377_clk_recalc_rate, + .set_rate =3D adf4377_clk_set_rate, + .prepare =3D adf4377_clk_prepare, + .unprepare =3D adf4377_clk_unprepare, + .is_prepared =3D adf4377_clk_is_prepared, +}; + +static int adf4377_clk_register(struct adf4377_state *st) +{ + struct spi_device *spi =3D st->spi; + struct clk_init_data init; + struct clk_parent_data parent_data; + int ret; + + if (!device_property_present(&spi->dev, "#clock-cells")) + return 0; + + if (device_property_read_string(&spi->dev, "clock-output-names", &init.na= me)) { + init.name =3D devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk", + fwnode_get_name(dev_fwnode(&spi->dev))); + if (!init.name) + return -ENOMEM; + } + + parent_data.fw_name =3D "ref_in"; + + init.ops =3D &adf4377_clk_ops; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + init.flags =3D CLK_SET_RATE_PARENT; + + st->hw.init =3D &init; + ret =3D devm_clk_hw_register(&spi->dev, &st->hw); + if (ret) + return ret; + + ret =3D devm_of_clk_add_hw_provider(&spi->dev, of_clk_hw_simple_get, &st-= >hw); + if (ret) + return ret; + + st->clkout =3D st->hw.clk; + + return 0; +} + static const struct adf4377_chip_info adf4377_chip_info =3D { .name =3D "adf4377", .has_gpio_enclk2 =3D true, @@ -958,8 +1066,6 @@ static int adf4377_probe(struct spi_device *spi) =20 indio_dev->info =3D &adf4377_info; indio_dev->name =3D "adf4377"; - indio_dev->channels =3D adf4377_channels; - indio_dev->num_channels =3D ARRAY_SIZE(adf4377_channels); =20 st->regmap =3D regmap; st->spi =3D spi; @@ -979,6 +1085,15 @@ static int adf4377_probe(struct spi_device *spi) if (ret) return ret; =20 + ret =3D adf4377_clk_register(st); + if (ret) + return ret; + + if (!st->clkout) { + indio_dev->channels =3D adf4377_channels; + indio_dev->num_channels =3D ARRAY_SIZE(adf4377_channels); + } + return devm_iio_device_register(&spi->dev, indio_dev); } =20 --=20 2.43.0