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Tue, 25 Nov 2025 13:06:42 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id oMS1A+KpJWkDFAAAD6G6ig (envelope-from ); Tue, 25 Nov 2025 13:06:42 +0000 From: Thomas Zimmermann To: simona@ffwll.ch, airlied@gmail.com, alexander.deucher@amd.com, christian.koenig@amd.com, lyude@redhat.com, dakr@kernel.org, deller@gmx.de, mripard@kernel.org, maarten.lankhorst@linux.intel.com, jason.wessel@windriver.com, danielt@kernel.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-fbdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Zimmermann Subject: [PATCH 3/5] drm/radeon: Do not implement mode_set_base_atomic callback Date: Tue, 25 Nov 2025 13:52:15 +0100 Message-ID: <20251125130634.1080966-4-tzimmermann@suse.de> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251125130634.1080966-1-tzimmermann@suse.de> References: <20251125130634.1080966-1-tzimmermann@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[19]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FREEMAIL_TO(0.00)[ffwll.ch,gmail.com,amd.com,redhat.com,kernel.org,gmx.de,linux.intel.com,windriver.com,chromium.org]; RCVD_TLS_ALL(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLq3cifbxyhc6qbbynzfc6amns)]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FREEMAIL_ENVRCPT(0.00)[gmail.com,gmx.de] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Remove the implementation of the CRTC helper mode_set_base_atomic from radeon. It pretends to provide mode setting for kdb debugging, but has been broken for some time. Kdb output has been supported only for non-atomic mode setting since commit 9c79e0b1d096 ("drm/fb-helper: Give up on kgdb for atomic drivers") from 2017. While radeon provides non-atomic mode setting, kdb assumes that the GEM buffer object is at a fixed location in video memory. This assumption currently blocks radeon from converting to generic fbdev emulation. Fbdev-ttm helpers use a shadow buffer with a movable GEM buffer object. Triggering kdb does therefore not update the display. Another problem is that the current implementation does not handle USB keyboard input. Therefore a serial terminal is required. Then when continuing from the debugger, radeon fails with an error: [7]kdb> go [ 40.345523][ C7] BUG: scheduling while atomic: bash/1580/0x00110003 [...] [ 40.345613][ C7] schedule+0x27/0xd0 [ 40.345615][ C7] schedule_timeout+0x7b/0x100 [ 40.345617][ C7] ? __pfx_process_timeout+0x10/0x10 [ 40.345619][ C7] msleep+0x31/0x50 [ 40.345621][ C7] radeon_crtc_load_lut+0x2e4/0xcb0 [radeon 31c1ee785d= e120fcfd0babcc09babb3770252b4e] [ 40.345698][ C7] radeon_crtc_gamma_set+0xe/0x20 [radeon 31c1ee785de1= 20fcfd0babcc09babb3770252b4e] [ 40.345760][ C7] drm_fb_helper_debug_leave+0xd8/0x130 [ 40.345763][ C7] kgdboc_post_exp_handler+0x54/0x70 [...] and the system hangs. Support for kdb feels pretty much broken. Hence remove the whole kdb support from radeon. Signed-off-by: Thomas Zimmermann --- drivers/gpu/drm/radeon/atombios_crtc.c | 74 ++++++--------------- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 23 ++----- drivers/gpu/drm/radeon/radeon_mode.h | 10 +-- 3 files changed, 26 insertions(+), 81 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeo= n/atombios_crtc.c index 9b3a3a9d60e2..2fc0334e0d6c 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1133,7 +1133,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *cr= tc, struct drm_display_mode =20 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct radeon_crtc *radeon_crtc =3D to_radeon_crtc(crtc); struct drm_device *dev =3D crtc->dev; @@ -1150,33 +1150,23 @@ static int dce4_crtc_do_set_base(struct drm_crtc *c= rtc, bool bypass_lut =3D false; =20 /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 - /* If atomic, assume fb object is pinned & idle & fenced and - * just update base pointers - */ obj =3D target_fb->obj[0]; rbo =3D gem_to_radeon_bo(obj); r =3D radeon_bo_reserve(rbo, false); if (unlikely(r !=3D 0)) return r; =20 - if (atomic) - fb_location =3D radeon_bo_gpu_offset(rbo); - else { - r =3D radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); - if (unlikely(r !=3D 0)) { - radeon_bo_unreserve(rbo); - return -EINVAL; - } + r =3D radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r !=3D 0)) { + radeon_bo_unreserve(rbo); + return -EINVAL; } =20 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); @@ -1437,7 +1427,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crt= c, /* set pageflip to happen anywhere in vblank interval */ WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { rbo =3D gem_to_radeon_bo(fb->obj[0]); r =3D radeon_bo_reserve(rbo, false); if (unlikely(r !=3D 0)) @@ -1454,7 +1444,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crt= c, =20 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct radeon_crtc *radeon_crtc =3D to_radeon_crtc(crtc); struct drm_device *dev =3D crtc->dev; @@ -1470,15 +1460,12 @@ static int avivo_crtc_do_set_base(struct drm_crtc *= crtc, bool bypass_lut =3D false; =20 /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 obj =3D target_fb->obj[0]; rbo =3D gem_to_radeon_bo(obj); @@ -1486,17 +1473,10 @@ static int avivo_crtc_do_set_base(struct drm_crtc *= crtc, if (unlikely(r !=3D 0)) return r; =20 - /* If atomic, assume fb object is pinned & idle & fenced and - * just update base pointers - */ - if (atomic) - fb_location =3D radeon_bo_gpu_offset(rbo); - else { - r =3D radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); - if (unlikely(r !=3D 0)) { - radeon_bo_unreserve(rbo); - return -EINVAL; - } + r =3D radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r !=3D 0)) { + radeon_bo_unreserve(rbo); + return -EINVAL; } radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); radeon_bo_unreserve(rbo); @@ -1645,7 +1625,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *cr= tc, /* set pageflip to happen only at start of vblank interval (front porch) = */ WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { rbo =3D gem_to_radeon_bo(fb->obj[0]); r =3D radeon_bo_reserve(rbo, false); if (unlikely(r !=3D 0)) @@ -1667,26 +1647,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, i= nt x, int y, struct radeon_device *rdev =3D dev->dev_private; =20 if (ASIC_IS_DCE4(rdev)) - return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); - else if (ASIC_IS_AVIVO(rdev)) - return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); - else - return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - struct drm_device *dev =3D crtc->dev; - struct radeon_device *rdev =3D dev->dev_private; - - if (ASIC_IS_DCE4(rdev)) - return dce4_crtc_do_set_base(crtc, fb, x, y, 1); + return dce4_crtc_do_set_base(crtc, old_fb, x, y); else if (ASIC_IS_AVIVO(rdev)) - return avivo_crtc_do_set_base(crtc, fb, x, y, 1); + return avivo_crtc_do_set_base(crtc, old_fb, x, y); else - return radeon_crtc_do_set_base(crtc, fb, x, y, 1); + return radeon_crtc_do_set_base(crtc, old_fb, x, y); } =20 /* properly set additional regs when using atombios */ @@ -2215,7 +2180,6 @@ static const struct drm_crtc_helper_funcs atombios_he= lper_funcs =3D { .mode_fixup =3D atombios_crtc_mode_fixup, .mode_set =3D atombios_crtc_mode_set, .mode_set_base =3D atombios_crtc_set_base, - .mode_set_base_atomic =3D atombios_crtc_set_base_atomic, .prepare =3D atombios_crtc_prepare, .commit =3D atombios_crtc_commit, .disable =3D atombios_crtc_disable, diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/= radeon/radeon_legacy_crtc.c index 825b351ff53c..a1054c8094d4 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -360,19 +360,12 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, i= nt mode) int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return radeon_crtc_do_set_base(crtc, fb, x, y, 1); + return radeon_crtc_do_set_base(crtc, old_fb, x, y); } =20 int radeon_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct drm_device *dev =3D crtc->dev; struct radeon_device *rdev =3D dev->dev_private; @@ -390,15 +383,12 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, =20 DRM_DEBUG_KMS("\n"); /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 switch (target_fb->format->cpp[0] * 8) { case 8: @@ -445,7 +435,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, * We don't shutdown the display controller because new buffer * will end up in same spot. */ - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { struct radeon_bo *old_rbo; unsigned long nsize, osize; =20 @@ -555,7 +545,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { rbo =3D gem_to_radeon_bo(fb->obj[0]); r =3D radeon_bo_reserve(rbo, false); if (unlikely(r !=3D 0)) @@ -1108,7 +1098,6 @@ static const struct drm_crtc_helper_funcs legacy_help= er_funcs =3D { .mode_fixup =3D radeon_crtc_mode_fixup, .mode_set =3D radeon_crtc_mode_set, .mode_set_base =3D radeon_crtc_set_base, - .mode_set_base_atomic =3D radeon_crtc_set_base_atomic, .prepare =3D radeon_crtc_prepare, .commit =3D radeon_crtc_commit, .disable =3D radeon_crtc_disable, diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/= radeon_mode.h index 9e34da2cacef..088af85902f7 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -804,10 +804,6 @@ extern bool radeon_encoder_is_digital(struct drm_encod= er *encoder); extern void radeon_crtc_load_lut(struct drm_crtc *crtc); extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); -extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, - enum mode_set_atomic state); extern int atombios_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, @@ -817,13 +813,9 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, = int mode); =20 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); -extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, - enum mode_set_atomic state); extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic); + int x, int y); extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file_priv, uint32_t handle, --=20 2.51.1