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Tue, 25 Nov 2025 13:06:40 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id +GNcOOCpJWkDFAAAD6G6ig (envelope-from ); Tue, 25 Nov 2025 13:06:40 +0000 From: Thomas Zimmermann To: simona@ffwll.ch, airlied@gmail.com, alexander.deucher@amd.com, christian.koenig@amd.com, lyude@redhat.com, dakr@kernel.org, deller@gmx.de, mripard@kernel.org, maarten.lankhorst@linux.intel.com, jason.wessel@windriver.com, danielt@kernel.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-fbdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Zimmermann Subject: [PATCH 1/5] drm/amdgpu: Do not implement mode_set_base_atomic callback Date: Tue, 25 Nov 2025 13:52:13 +0100 Message-ID: <20251125130634.1080966-2-tzimmermann@suse.de> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251125130634.1080966-1-tzimmermann@suse.de> References: <20251125130634.1080966-1-tzimmermann@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: 7A27F5BD0D X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; 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R_RATELIMIT(0.00)[to_ip_from(RLgosu6qu4h11rje89ht7rjgg5)]; RCVD_VIA_SMTP_AUTH(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com,gmx.de] X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Remove all implementations of the CRTC helper mode_set_base_atomic from amdgpu. It pretends to provide mode setting for kdb debugging, but has been broken for some time. Kdb output has been supported only for non-atomic mode setting since commit 9c79e0b1d096 ("drm/fb-helper: Give up on kgdb for atomic drivers") from 2017. While amdgpu provides non-atomic mode setting for some devices, kdb assumes that the GEM buffer object is at a fixed location in video memory. This has not been the case since commit 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") from 2021. Fbdev-ttm helpers use a shadow buffer with a movable GEM buffer object. Triggering kdb does not update the display. Hence remove the whole kdb support from amdgpu. Signed-off-by: Thomas Zimmermann --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 35 ++++++++------------------ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 35 ++++++++------------------ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 35 ++++++++------------------ 3 files changed, 33 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/dce_v10_0.c index 72ca6538b2e4..61302204e9b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1838,7 +1838,7 @@ static void dce_v10_0_grph_enable(struct drm_crtc *cr= tc, bool enable) =20 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc =3D to_amdgpu_crtc(crtc); struct drm_device *dev =3D crtc->dev; @@ -1855,15 +1855,12 @@ static int dce_v10_0_crtc_do_set_base(struct drm_cr= tc *crtc, bool bypass_lut =3D false; =20 /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers @@ -1874,13 +1871,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_cr= tc *crtc, if (unlikely(r !=3D 0)) return r; =20 - if (!atomic) { - abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r !=3D 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r !=3D 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location =3D amdgpu_bo_gpu_offset(abo); =20 @@ -2068,7 +2063,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc= *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { abo =3D gem_to_amdgpu_bo(fb->obj[0]); r =3D amdgpu_bo_reserve(abo, true); if (unlikely(r !=3D 0)) @@ -2611,7 +2606,7 @@ static int dce_v10_0_crtc_mode_set(struct drm_crtc *c= rtc, =20 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v10_0_cursor_reset(crtc); @@ -2659,14 +2654,7 @@ static bool dce_v10_0_crtc_mode_fixup(struct drm_crt= c *crtc, static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); } =20 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs =3D { @@ -2674,7 +2662,6 @@ static const struct drm_crtc_helper_funcs dce_v10_0_c= rtc_helper_funcs =3D { .mode_fixup =3D dce_v10_0_crtc_mode_fixup, .mode_set =3D dce_v10_0_crtc_mode_set, .mode_set_base =3D dce_v10_0_crtc_set_base, - .mode_set_base_atomic =3D dce_v10_0_crtc_set_base_atomic, .prepare =3D dce_v10_0_crtc_prepare, .commit =3D dce_v10_0_crtc_commit, .disable =3D dce_v10_0_crtc_disable, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/am= dgpu/dce_v6_0.c index acc887a58518..8f4b4c2e36b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1876,7 +1876,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crt= c, bool enable) =20 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc =3D to_amdgpu_crtc(crtc); struct drm_device *dev =3D crtc->dev; @@ -1892,15 +1892,12 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crt= c *crtc, bool bypass_lut =3D false; =20 /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers @@ -1911,13 +1908,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crt= c *crtc, if (unlikely(r !=3D 0)) return r; =20 - if (!atomic) { - abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r !=3D 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r !=3D 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location =3D amdgpu_bo_gpu_offset(abo); =20 @@ -2083,7 +2078,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc = *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { abo =3D gem_to_amdgpu_bo(fb->obj[0]); r =3D amdgpu_bo_reserve(abo, true); if (unlikely(r !=3D 0)) @@ -2578,7 +2573,7 @@ static int dce_v6_0_crtc_mode_set(struct drm_crtc *cr= tc, =20 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v6_0_cursor_reset(crtc); @@ -2626,14 +2621,7 @@ static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc= *crtc, static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); } =20 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs =3D { @@ -2641,7 +2629,6 @@ static const struct drm_crtc_helper_funcs dce_v6_0_cr= tc_helper_funcs =3D { .mode_fixup =3D dce_v6_0_crtc_mode_fixup, .mode_set =3D dce_v6_0_crtc_mode_set, .mode_set_base =3D dce_v6_0_crtc_set_base, - .mode_set_base_atomic =3D dce_v6_0_crtc_set_base_atomic, .prepare =3D dce_v6_0_crtc_prepare, .commit =3D dce_v6_0_crtc_commit, .disable =3D dce_v6_0_crtc_disable, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/dce_v8_0.c index 2ccd6aad8dd6..9d1853c41fcd 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1785,7 +1785,7 @@ static void dce_v8_0_grph_enable(struct drm_crtc *crt= c, bool enable) =20 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc =3D to_amdgpu_crtc(crtc); struct drm_device *dev =3D crtc->dev; @@ -1802,15 +1802,12 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crt= c *crtc, bool bypass_lut =3D false; =20 /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } =20 - if (atomic) - target_fb =3D fb; - else - target_fb =3D crtc->primary->fb; + target_fb =3D crtc->primary->fb; =20 /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers @@ -1821,13 +1818,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crt= c *crtc, if (unlikely(r !=3D 0)) return r; =20 - if (!atomic) { - abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r !=3D 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |=3D AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r =3D amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r !=3D 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location =3D amdgpu_bo_gpu_offset(abo); =20 @@ -1995,7 +1990,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc = *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); =20 - if (!atomic && fb && fb !=3D crtc->primary->fb) { + if (fb && fb !=3D crtc->primary->fb) { abo =3D gem_to_amdgpu_bo(fb->obj[0]); r =3D amdgpu_bo_reserve(abo, true); if (unlikely(r !=3D 0)) @@ -2537,7 +2532,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *cr= tc, =20 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v8_0_cursor_reset(crtc); @@ -2585,14 +2580,7 @@ static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc= *crtc, static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y); } =20 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs =3D { @@ -2600,7 +2588,6 @@ static const struct drm_crtc_helper_funcs dce_v8_0_cr= tc_helper_funcs =3D { .mode_fixup =3D dce_v8_0_crtc_mode_fixup, .mode_set =3D dce_v8_0_crtc_mode_set, .mode_set_base =3D dce_v8_0_crtc_set_base, - .mode_set_base_atomic =3D dce_v8_0_crtc_set_base_atomic, .prepare =3D dce_v8_0_crtc_prepare, .commit =3D dce_v8_0_crtc_commit, .disable =3D dce_v8_0_crtc_disable, --=20 2.51.1