From nobody Tue Dec 2 00:26:28 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45AA731ED7D for ; Tue, 25 Nov 2025 12:06:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764072390; cv=none; b=j+7rEqeRfUb8cGS37WdLXjRAjJsgajyMG3IPiC1c/iraQrFqpNUP99grhvVmmhLA24Q6Xntxf0++/iOQfVg2LlwTfu/j6uMEB3ZeOHrk40t7/Kuw41pPAPWOZAqwbsvGKi+Ht7iZXsjZPxZbgUkq63BKdRuATpvfTaFO6e47TPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764072390; c=relaxed/simple; bh=xUFvUb8oKPEbKpAh29NhrNZ2bfXoPM/j19JqA5bbRxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pFKdxeyiDy8fVmja/PaqxYKnnXhBGTZ2PrX46PuedrA5F9KgYjMGVUi2MAAscr+2wB7eKNUq3LwRfwlFCcmAMBmjDGBUptWtcojpIjlmBPbiTjI9nSlsAfkm/dmV313vHEZK+PyYwXNX5x/Vbt8wiamWewm/EWCaow1YhPC/r0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GmGoHuOW; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GmGoHuOW" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-59578e38613so6264226e87.2 for ; Tue, 25 Nov 2025 04:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764072386; x=1764677186; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uN+F0Xnd3WljGjWpLVxmMpsaxzHe/mQ0Vkjj3hwJW+M=; b=GmGoHuOWaR995Lcc79GWMbCFK4Oss6BPSvGUKGkjTD/fy0s4ot8bE+Nlm7J/Yr5LF7 8F39Gcu6sECcvo64cJ8eaI5q06VXZ12D8uk6kRyRggF69MOM/jUQIVFAUffcE79K7h3j YJDbVtvlQ1JyXmfO3S0OxA3BvoOTKl0ZkCMOJ7c1KYOVB5iW42ckgzIUyVe5vJtVuOa9 Iu+TEwCepv3v5v8syqVEtfyNimIy6XEbFDV/e6aVKLCmHuCqyQ2j26951K4O6m7tho08 lL1Dwhgs1g0zA93IXwtba0Mrfc2iMxu1YrxeOfxiXNRbcyZjSKVLSi35jdPidD+IXl6i SVLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764072386; x=1764677186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=uN+F0Xnd3WljGjWpLVxmMpsaxzHe/mQ0Vkjj3hwJW+M=; b=puRrtRJg3kYQ3vWbWDp8lQVbb3QG/hob/eIyjLb1FWps4WMtQWNAOw6VZqJ5SjDSnM d8ztmI4ScBMbET+oRWYSA15A1yvs9kTVAQQvjG+Iiw8m4wW4p+PevUdZvVoIH9hHtZmS N46RdhuUnGhcmXa8urmzI/xc44Zt3Efi/FDFTy+61F92FJ2oI/r13Nt8g9RkjhE29i/e JIHP5stlA/XbFuYiQr4QhvHcMwb17hd6YEAjM6ijCYNnmeJLyCN5o0Un9Q5TCNBe3uf3 +NiISUYrL2W6h9wLiz+wKXvOMtp2VsPCAuWXuj2a4Lv6W0VSjUYEp8kSMeWve9Kh0pTj VBfA== X-Gm-Message-State: AOJu0Yz+3K4nLMK4HOkCdRjK3Bh7aGHCGayjcJvmt14RX1TCHiPUh2qR jHAqFJwsnF0SWWThMR8LGbsByFcOAm7NRXwiWJYL1Vl3Y5dFuAnGNtcjqGfZwQ== X-Gm-Gg: ASbGncvfB0Y9YM6OTCDRYG27JadeNXvHD1P3Hs46vreGGaQjJS/UW4vzO6tzwv+G8tS X67RvFuXGQ2CULFQXf5Z0UsK9xLwfWYCIWazILOvDf8T1Gk66Siq+zDYIoXUiJJmu+qAin87SDz CRvW8+rPRK0F5E7I34tU7/UtQci/9kGmsl6HfZQzr/8QQ2Kf19aJzO3x0osZJqYmQzskcgeaFmI KmPncNI3vqi/LlGgnq5OVYYwFl9PwRjLjxsriqlcf4TBDtSP2cyViCoYfy7qognxc6KbHjhHHGl TFxN7itF+EXYjVd09Zt8buOyTFgxIgs/12dcAUbD1cHkCUNlQ8GNb/lMMwlsQ5IiOzx5zkHUO+l 6GffMF5ciauEind2nladmNMD7pE9AT2bTJbArBJ+tXTArstF6kPkZ7Efd1ynvFpPnWFTJnJXQxJ o= X-Google-Smtp-Source: AGHT+IGkQddv0h4W/kIYw24XVr8lRF2/F0YngAnHGV9hmScDktzlX2Yt8Q6XtITCokbogoFFbpJn9Q== X-Received: by 2002:a05:6512:159c:b0:595:9152:b932 with SMTP id 2adb3069b0e04-596b526c87bmr786045e87.47.1764072385864; Tue, 25 Nov 2025 04:06:25 -0800 (PST) Received: from xeon ([188.163.112.74]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5969dbbecb9sm5150993e87.58.2025.11.25.04.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 04:06:25 -0800 (PST) From: Svyatoslav Ryhel To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Mikko Perttunen , Michael Turquette , Stephen Boyd , Dmitry Osipenko , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Svyatoslav Ryhel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 06/12] clk: tegra: set up proper EMC clock implementation for Tegra114 Date: Tue, 25 Nov 2025 14:05:53 +0200 Message-ID: <20251125120559.158860-7-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251125120559.158860-1-clamor95@gmail.com> References: <20251125120559.158860-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove current emc and emc_mux clocks and replace them with the proper EMC clock implementation for correct EMC driver support. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra114.c | 39 ++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index 8bde72aa5e68..853ef707654a 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] =3D { }; #define mux_plld_out0_plld2_out0_idx NULL =20 -static const char *mux_pllmcp_clkm[] =3D { - "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", -}; - static const struct clk_div_table pll_re_div_table[] =3D { { .val =3D 0, .div =3D 1 }, { .val =3D 1, .div =3D 2 }, @@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __= initdata =3D { [tegra_clk_csi] =3D { .dt_id =3D TEGRA114_CLK_CSI, .present =3D true }, [tegra_clk_i2c2] =3D { .dt_id =3D TEGRA114_CLK_I2C2, .present =3D true }, [tegra_clk_uartc] =3D { .dt_id =3D TEGRA114_CLK_UARTC, .present =3D true = }, - [tegra_clk_emc] =3D { .dt_id =3D TEGRA114_CLK_EMC, .present =3D true }, [tegra_clk_usb2] =3D { .dt_id =3D TEGRA114_CLK_USB2, .present =3D true }, [tegra_clk_usb3] =3D { .dt_id =3D TEGRA114_CLK_USB3, .present =3D true }, [tegra_clk_vde_8] =3D { .dt_id =3D TEGRA114_CLK_VDE, .present =3D true }, @@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __i= omem *clk_base, 0, 82, periph_clk_enb_refcnt); clks[TEGRA114_CLK_DSIB] =3D clk; =20 - /* emc mux */ - clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 29, 3, 0, &emc_lock); - - clk =3D tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + clk =3D tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, &emc_lock); clks[TEGRA114_CLK_MC] =3D clk; =20 @@ -1321,6 +1309,26 @@ static int tegra114_reset_deassert(unsigned long id) return 0; } =20 +static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *cl= kspec, + void *data) +{ + struct clk_hw *hw; + struct clk *clk; + + clk =3D of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + hw =3D __clk_get_hw(clk); + + if (clkspec->args[0] =3D=3D TEGRA114_CLK_EMC) { + if (!tegra124_clk_emc_driver_available(hw)) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + static void __init tegra114_clock_init(struct device_node *np) { struct device_node *node; @@ -1368,7 +1376,10 @@ static void __init tegra114_clock_init(struct device= _node *np) tegra_init_special_resets(1, tegra114_reset_assert, tegra114_reset_deassert); =20 - tegra_add_of_provider(np, of_clk_src_onecell_get); + tegra_add_of_provider(np, tegra114_clk_src_onecell_get); + clks[TEGRA114_CLK_EMC] =3D tegra124_clk_register_emc(clk_base, np, + &emc_lock); + tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); =20 tegra_clk_apply_init_table =3D tegra114_clock_apply_init_table; --=20 2.51.0