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Tue, 25 Nov 2025 04:06:21 -0800 (PST) Received: from xeon ([188.163.112.74]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5969dbbecb9sm5150993e87.58.2025.11.25.04.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 04:06:21 -0800 (PST) From: Svyatoslav Ryhel To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Mikko Perttunen , Michael Turquette , Stephen Boyd , Dmitry Osipenko , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Svyatoslav Ryhel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 03/12] dt-bindings: memory: Document Tegra114 Memory Controller Date: Tue, 25 Nov 2025 14:05:50 +0200 Message-ID: <20251125120559.158860-4-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251125120559.158860-1-clamor95@gmail.com> References: <20251125120559.158860-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Tegra114 support into existing Tegra124 MC schema with the most notable difference in the amount of EMEM timings. Signed-off-by: Svyatoslav Ryhel --- .../nvidia,tegra124-mc.yaml | 31 +++++-------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidi= a,tegra124-mc.yaml index 7b18b4d11e0a..f8747cebb680 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-= mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-= mc.yaml @@ -19,7 +19,9 @@ description: | =20 properties: compatible: - const: nvidia,tegra124-mc + enum: + - nvidia,tegra114-mc + - nvidia,tegra124-mc =20 reg: maxItems: 1 @@ -64,29 +66,12 @@ patternProperties: =20 nvidia,emem-configuration: $ref: /schemas/types.yaml#/definitions/uint32-array - description: | + description: Values to be written to the EMEM register block. See section - "15.6.1 MC Registers" in the TRM. - items: - - description: MC_EMEM_ARB_CFG - - description: MC_EMEM_ARB_OUTSTANDING_REQ - - description: MC_EMEM_ARB_TIMING_RCD - - description: MC_EMEM_ARB_TIMING_RP - - description: MC_EMEM_ARB_TIMING_RC - - description: MC_EMEM_ARB_TIMING_RAS - - description: MC_EMEM_ARB_TIMING_FAW - - description: MC_EMEM_ARB_TIMING_RRD - - description: MC_EMEM_ARB_TIMING_RAP2PRE - - description: MC_EMEM_ARB_TIMING_WAP2PRE - - description: MC_EMEM_ARB_TIMING_R2R - - description: MC_EMEM_ARB_TIMING_W2W - - description: MC_EMEM_ARB_TIMING_R2W - - description: MC_EMEM_ARB_TIMING_W2R - - description: MC_EMEM_ARB_DA_TURNS - - description: MC_EMEM_ARB_DA_COVERS - - description: MC_EMEM_ARB_MISC0 - - description: MC_EMEM_ARB_MISC1 - - description: MC_EMEM_ARB_RING1_THROTTLE + "20.11.1 MC Registers" in the Tegea114 TRM or + "15.6.1 MC Registers" in the Tegra124 TRM. + minItems: 18 + maxItems: 19 =20 required: - clock-frequency --=20 2.51.0