From nobody Tue Dec 2 00:25:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE96025A2DE for ; Tue, 25 Nov 2025 10:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764066029; cv=none; b=i4bSsJEp+LLrpDsVX/2LC+dwDxmX4ViaLxxrkJZpmgldg478ZaRv8eUQZaG7w2C2BlhJvxOFQ6L2uxRng4V6DzTp5lOaH0eB34gw76pNS7EsWuFXIdzDkj0VBPb8qvJFD3XKIAdj9s1Uh78Z9UjETXmjkBsyac8+L4JZiG40jCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764066029; c=relaxed/simple; bh=FX6vQCjspxWdfPC/pP/DPZ4hXHIGjzfMuhEKO1y22j8=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=rRdNSgGz/Jl4jJMuRvlDRGKsBau2mdMlB4f25JHtDtqcjvtcM+6yVqQ0dY0hJ9UG3TPYvlrm4aG2irVv7jhtY+YtHX/SW8vYHAKoROw5XXaCqhTYUgQPlLGYF2bwnazIuFcvptwL43VqBe7heLkMXDYiCJIO5fvOW5H1lPGkbN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=pFfvr8Qw; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nSZ006Vu; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="pFfvr8Qw"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nSZ006Vu" Message-ID: <20251125102000.763427030@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1764066026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CKOcxgwQC9pKv1DGXKe9DExfiqkuy6yibuRoUUEeNOQ=; b=pFfvr8QwCH6DX15Fk58bKeQ3FM6OVGnzio90AJ1j40CqtlQAsSorMGN0gduywYKrzhezC3 W10eQxf0L6h9lqb/6IOq1wwbKWzvQ3WQCtu7h1R16KVjObi9yktb8D/hiy9vHmN8KaWlQC uIv5srMJs5i1FQO29JrS8cXJRt4ZH53nsTqR/4Kl3amkCeZYXodyH0n4y/2akk7WdF2R4C eCFtVJnYYwGNPoRCKynWERRileok4ucZnBB5EEKpU1gj7vlRu5zXcG6TI9NQQqGVpVWBAL ey4o7aCV6tk4NzCS1CVDZyO6+b6J+vfvVx/+4dUzdpiS2hXAJg7Tpvzj5jnykw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1764066026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CKOcxgwQC9pKv1DGXKe9DExfiqkuy6yibuRoUUEeNOQ=; b=nSZ006Vu5NMbvPlJgPWvdTRN3FcLxreUVGbtPQuARRtKyTaSngkXqkSADrsggRhHfOkkRL KOMKxu00AGQukOBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Lu Baolu , Joerg Roedel , Luigi Rizzo Subject: [patch 3/3] x86/irq_remapping: Sanitize posted_msi_supported() References: <20251125101912.564125647@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 25 Nov 2025 11:20:25 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" posted_msi_supported() is a misnomer as it actually checks whether it is enabled or not. Aside of that this does not take CONFIG_X86_POSTED_MSI into account which is required to actually use it. Rename it to posted_msi_enabled() and make the return value depend on CONFIG_X86_POSTED_MSI, which allows the compiler to eliminate the related dead code and data if disabled: text data bss dec hex filename 10046 701 3296 14043 36db drivers/iommu/intel/irq_remapping.o 9904 413 3296 13613 352d drivers/iommu/intel/irq_remapping.o Signed-off-by: Thomas Gleixner Cc: Lu Baolu Cc: Joerg Roedel --- arch/x86/include/asm/irq_remapping.h | 5 +++-- drivers/iommu/intel/irq_remapping.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -67,9 +67,10 @@ static inline struct irq_domain *arch_ge =20 extern bool enable_posted_msi; =20 -static inline bool posted_msi_supported(void) +static inline bool posted_msi_enabled(void) { - return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); + return IS_ENABLED(CONFIG_X86_POSTED_MSI) && + enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); } =20 #else /* CONFIG_IRQ_REMAP */ --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1368,7 +1368,7 @@ static void intel_irq_remapping_prepare_ break; case X86_IRQ_ALLOC_TYPE_PCI_MSI: case X86_IRQ_ALLOC_TYPE_PCI_MSIX: - if (posted_msi_supported()) { + if (posted_msi_enabled()) { prepare_irte_posted(irte); data->irq_2_iommu.posted_msi =3D 1; } @@ -1460,7 +1460,7 @@ static int intel_irq_remapping_alloc(str =20 irq_data->hwirq =3D (index << 16) + i; irq_data->chip_data =3D ird; - if (posted_msi_supported() && + if (posted_msi_enabled() && ((info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSI) || (info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSIX))) irq_data->chip =3D &intel_ir_chip_post_msi;