From nobody Tue Dec 2 00:25:31 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 946BB2F12BD for ; Tue, 25 Nov 2025 10:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764066027; cv=none; b=qgfnBfuLwTW9zpoEis/PYK5qtnAsJHF+LZ6UqfuGk0UnZ4+sVIKGRri+eGDdEo0VaNcheFs91x1cy5qN3hteWpXOgG5xn4l51odv3BVDzWlwAlg7hEZQyTr7EMjqUWcgSGUe9/Vzi5mv9XyxSkWvD7EZD9BC9tljLQKZMuSY09o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764066027; c=relaxed/simple; bh=ThULgGE5HtqxkienEmg1LbApJ1gx0cXbI3YA4yF4y4k=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=Cm47/TtTF3+eCuVOzNdiM+kDsZqKvrP2lbStT/+cGPKeII925RSY7iC3Cae7dqSs09xss+PXmWlgwOZ02owv2m3EbfAErnY0vV8Y94ICsNheNI40XCJ1YCqGaavMGop66pas1Ir2If+fVkuPeWjynoIjZ0LmN3yNKI0lR5eJecc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0dCzXaow; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zMw7XbJH; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0dCzXaow"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zMw7XbJH" Message-ID: <20251125102000.699735132@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1764066023; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=czOKra+JElCo18rWCOg9NtKsN1jpBWlwRqImLdg5HVg=; b=0dCzXaowik80+pISltCCEztQGGlx6eYEuBPtzhSNkrbEGoAAffpje6DH6irDjwWM5jey14 YRIDH/TVRedlGhOF2L+tMrJzCY1wJNzRb5Hk+DYGnrA4we8W0/I9A5T5UFqEtA2qkhdfX7 pZ5bFW6RfNoAbUuD0132jPAu9qQ3A/ULQDawIlzUPyOQI4ml/42ImYBVszMUIFXZYGC7Di dCetLBYQ2LwXSVubKKldF62lDp00nEuw7LLisp7nU82TKLEijzkgGIEcve97ua+4okrAno ImdESYhHou96Y86DZuEoglD/DwHaH6sO5ISPYuTOFENIN1LG5n6/togZtDnf4Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1764066023; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=czOKra+JElCo18rWCOg9NtKsN1jpBWlwRqImLdg5HVg=; b=zMw7XbJHPhAgJCq8XpZyfaghwqdl3T3avx1nJ1Q8dtxGKpRbDu4o4/OuPHZO26ab1A2mWR LHnpQAxC4MxvVqCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Luigi Rizzo , Lu Baolu , Joerg Roedel Subject: [patch 2/3] x86/irq: Cleanup posted MSI code References: <20251125101912.564125647@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 25 Nov 2025 11:20:22 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make code and comments readable. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/irq.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -401,11 +401,9 @@ static DEFINE_PER_CPU_CACHE_HOT(bool, po =20 void intel_posted_msi_init(void) { - u32 destination; - u32 apic_id; + u32 destination, apic_id; =20 this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR); - /* * APIC destination ID is stored in bit 8:15 while in XAPIC mode. * VT-d spec. CH 9.11 @@ -449,8 +447,8 @@ static __always_inline bool handle_pendi } =20 /* - * Performance data shows that 3 is good enough to harvest 90+% of the ben= efit - * on high IRQ rate workload. + * Performance data shows that 3 is good enough to harvest 90+% of the + * benefit on high interrupt rate workloads. */ #define MAX_POSTED_MSI_COALESCING_LOOP 3 =20 @@ -460,11 +458,8 @@ static __always_inline bool handle_pendi */ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification) { + struct pi_desc *pid =3D this_cpu_ptr(&posted_msi_pi_desc); struct pt_regs *old_regs =3D set_irq_regs(regs); - struct pi_desc *pid; - int i =3D 0; - - pid =3D this_cpu_ptr(&posted_msi_pi_desc); =20 /* Mark the handler active for intel_ack_posted_msi_irq() */ this_cpu_write(posted_msi_handler_active, true); @@ -472,25 +467,25 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi irq_enter(); =20 /* - * Max coalescing count includes the extra round of handle_pending_pir - * after clearing the outstanding notification bit. Hence, at most - * MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here. + * Loop only MAX_POSTED_MSI_COALESCING_LOOP - 1 times here to take + * the final handle_pending_pir() invocation after clearing the + * outstanding notification bit into account. */ - while (++i < MAX_POSTED_MSI_COALESCING_LOOP) { + for (int i =3D 1; i < MAX_POSTED_MSI_COALESCING_LOOP; i++) { if (!handle_pending_pir(pid->pir, regs)) break; } =20 /* - * Clear outstanding notification bit to allow new IRQ notifications, - * do this last to maximize the window of interrupt coalescing. + * Clear the outstanding notification bit to rearm the notification + * mechanism. */ pi_clear_on(pid); =20 /* - * There could be a race of PI notification and the clearing of ON bit, - * process PIR bits one last time such that handling the new interrupts - * are not delayed until the next IRQ. + * Clearing the ON bit can race with a notification. Process the + * PIR bits one last time so that handling the new interrupts is + * not delayed until the next notification happens. */ handle_pending_pir(pid->pir, regs);