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Mon, 24 Nov 2025 22:49:10 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:2b48:6622:575f:f283]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7c3ed471022sm16853335b3a.21.2025.11.24.22.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:10 -0800 (PST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, chrome-platform@lists.linux.dev, Julius Werner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: firmware: coreboot: Convert to YAML Date: Tue, 25 Nov 2025 14:48:49 +0800 Message-ID: <20251125064851.3781993-1-wenst@chromium.org> X-Mailer: git-send-email 2.52.0.460.gd25c4c69ec-goog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the existing text binding to YAML. The description has been change to reflect the possibility of coreboot inserting the node itself. The example has been modified to compile and pass validation without any errors. A comment was added to note what the firmware actually emits. Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/firmware/coreboot.txt | 33 ---------- .../bindings/firmware/coreboot.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/firmware/coreboot.txt create mode 100644 Documentation/devicetree/bindings/firmware/coreboot.yaml diff --git a/Documentation/devicetree/bindings/firmware/coreboot.txt b/Docu= mentation/devicetree/bindings/firmware/coreboot.txt deleted file mode 100644 index 4c955703cea8..000000000000 --- a/Documentation/devicetree/bindings/firmware/coreboot.txt +++ /dev/null @@ -1,33 +0,0 @@ -COREBOOT firmware information - -The device tree node to communicate the location of coreboot's memory-resi= dent -bookkeeping structures to the kernel. Since coreboot itself cannot boot a -device-tree-based kernel (yet), this node needs to be inserted by a -second-stage bootloader (a coreboot "payload"). - -Required properties: - - compatible: Should be "coreboot" - - reg: Address and length of the following two memory regions, in order: - 1.) The coreboot table. This is a list of variable-sized descriptors - that contain various compile- and run-time generated firmware - parameters. It is identified by the magic string "LBIO" in its first - four bytes. - See coreboot's src/commonlib/include/commonlib/coreboot_tables.h for - details. - 2.) The CBMEM area. This is a downward-growing memory region used by - coreboot to dynamically allocate data structures that remain resident. - It may or may not include the coreboot table as one of its members. It - is identified by a root node descriptor with the magic number - 0xc0389481 that resides in the topmost 8 bytes of the area. - See coreboot's src/include/imd.h for details. - -Example: - firmware { - ranges; - - coreboot { - compatible =3D "coreboot"; - reg =3D <0xfdfea000 0x264>, - <0xfdfea000 0x16000>; - } - }; diff --git a/Documentation/devicetree/bindings/firmware/coreboot.yaml b/Doc= umentation/devicetree/bindings/firmware/coreboot.yaml new file mode 100644 index 000000000000..568afd1abb92 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/coreboot.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/coreboot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: COREBOOT firmware information + +maintainers: + - Julius Werner + +description: + The device tree node to communicate the location of coreboot's + memory-resident bookkeeping structures to the kernel. Coreboot's + FIT image payload can insert the node into the device tree. If a + second-stage bootloader (a coreboot "payload") is used, then it + is responsible for inserting the node. + +properties: + compatible: + const: coreboot + reg: + description: Address and length of the following two memory regions + items: + - description: + The coreboot table. This is a list of variable-sized descriptors + that contain various compile- and run-time generated firmware + parameters. It is identified by the magic string "LBIO" in its f= irst + four bytes. + + See coreboot's src/commonlib/include/commonlib/coreboot_tables.h= for + details. + - description: + The CBMEM area. This is a downward-growing memory region used by + coreboot to dynamically allocate data structures that remain res= ident. + It may or may not include the coreboot table as one of its membe= rs. It + is identified by a root node descriptor with the magic number + 0xc0389481 that resides in the topmost 8 bytes of the area. + + See coreboot's src/include/imd.h for details. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + firmware { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + /* Firmware actually emits "coreboot" node without unit name */ + coreboot@fdfea000 { + compatible =3D "coreboot"; + reg =3D <0xfdfea000 0x264>, <0xfdfea000 0x16000>; + }; + }; --=20 2.52.0.460.gd25c4c69ec-goog