From nobody Tue Dec 2 00:46:24 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 471B12C236B for ; Tue, 25 Nov 2025 06:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053347; cv=none; b=uGEAhxY3SBN9n1CRoLF9R1CIA3cMC6v72Gk1mewN9CVNfNZ0x93Yz83IB7SiKeoePsKJLBwunZoZqpa0tusEERe66XGJiqx7shHZ/7LFuiV0NnTlIZXvbKzrl/dzVkOQ9eSUQQIVEC0b7dtyM6Kf8SGnxi1v+JJ/IGlX7ghkgHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053347; c=relaxed/simple; bh=C/SRBt/7dSGnmJr1VczwjK56l7+Ma6+LmugqmP8ce6Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qTpkflTvXUX5fpWy6ACeepE+nsOtm3C25+KUl2vzWmAzA20henzeqILSs9Yya4KSyfhzb6fmntsLHPfBedSnuRqk6OWyvDIaDGf1vICi72EJhggH8Ldnsv92hUh1wwAq4TDywl+2Z8gFEQ5B5qb+gU52adjhB9YICe260biGa3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=DdcUgQCc; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Km7lpceK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="DdcUgQCc"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Km7lpceK" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gjmn2148813 for ; Tue, 25 Nov 2025 06:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ejOLCXs2H6V eH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=DdcUgQCcQkqhWxddtSUrQAFauQz HagkaneA6DB3ZSj/laGX2rbSj+i/XPn36v48RGK7hOZnEtqwNJpYd4s8fIpEhN+h G2358jOI5j/lxEGPiCA9PPp9Cj90YHwrNeOVL26oOEcMQbkrQqGctsblHthNw5x2 PH8jZoJVNiSkqzckDiQmpkEbZs/DQy4lZj1O0/w76IiXQ/Y1jMqaxM+bBCHZ17SD KONIi4wQYMNMI60P1ghH7hQVGL/nkq0QifxSCNbuoxO/XATLZfZGWW/PJmAg+BBv 6bxj1LKPLFpQJ6/OfxQ4wUKykVWi9qPhPACegszgblL5IpKKbHQEIKquMuQ== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amr8sanjh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:03 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8a1c15daa69so338872085a.1 for ; Mon, 24 Nov 2025 22:49:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053343; x=1764658143; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ejOLCXs2H6VeH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=Km7lpceKUfJiEsbP1G5Z9YWL/MWoWCyQr+2DFP++sY8N+o8ds/HTXPeooZJY0OsVIV 7GEusuzOrUAYFK9hD510YCLUEH+d6mF1IAXqQGVVjrOnpj1oZshM9Kc7FmQxxg7v7IVl YP53oL5KbGNZXBdF9k3Oi0GPYE7avMmUrOqiRmeO88Mn4DTw+16CJjnrrYuRtj71+2F0 QLAUsvP2m4Rjo6a9bwe5d9ieC9iftNN14csdYuvZZuxkYENfR+G+8w3J1Xibo/Rk+lZv lj+63Ri8Mqt6qcQI7Y5wZxj1pDEyuSOyqdrUSSpQgOFja139uy2Z8mR8BLeaQOJiFRVV 1IQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053343; x=1764658143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ejOLCXs2H6VeH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=hZ/Xts7bjx0WaLoEGWAQgnMd/rSfwiiICiU3Yw7xB276/SOvd5e+URSqgA5Y1Hykds INyHMunSqsblYrt2C81g23hsFeTShC0PqUFvhgtBv38yWQ5wTQgRRdoBWjumbmmkMqfi S6lKMVkO8Ce7FnFSJvjV7JskNiTW1QUDu+sDPamPFST52CRZFZDtFrgIaNlIF1V4S494 tUiMUIc5J0nhznrymPlDIB3lWUCEQMrTL2UifXx6JeiBSrDD6p6gjrtktjlpVf0Rh19x XhTErI6XEvVf2FlD+b9O9zNUdG5tXutiXrQWKg1uwvITacXNZGG3fUe37BZTEiiRj+zs sJKQ== X-Forwarded-Encrypted: i=1; AJvYcCVq2/qTOPDP7C7/3tnNzubfV9liEcrKW5SvT0F0xmXSPSFFadI5+kCA+wYxOSfQA5zh/v4tTUgHkkbWnJ8=@vger.kernel.org X-Gm-Message-State: AOJu0YyqHnkEMpUplFOIt73DF+Zp0Mm5F+XiCbzVx8PyexmJNsceXOUM pPgopmnED3gl5yutYIlZxx1rDttji3DwhTioUwve8SkRjGFhqZO3dMOOQVi/n4ZpDB8RgaXJ7gP ZjPcd1n26BoDfyU2wYbO/oJs4GnEPekSVsliyHUZBslX5PDcJTOIC+a104Avzc/K6bPI= X-Gm-Gg: ASbGncvhsVg+73BlRc+eMc6HXjyN1P6UNDI0s8/oMfKopoR53+CXXJ8WR6JCQWdIFVS KmBI8Uvh17UrAaqZawW8C9XOrrELatJ7ww74/YO9IgFmwD+ilm+VXs8aFzRD2Hotqhs//WmVBBB x8Z7f0aJrlYr+G5VlvdN+8J4ZzgLkNplRcl5IzyxBpfNLeYMb2ZVPBSfy8N+++8a6qiVuWyiDOA 3GG0UBsTPAbzu+ya/Im5sJbNuWTAWJRclkm1Pu4szIvfjP/DcJaa7PsAiE9tSwbp2lD6g40Mqy/ H1ZA84jGQB0SNMymjwPhTmdQTMqSPGb+7+nZGpkn2V59lG63cPik8WPtH3atex6wnDpP9AKQ96t xJecD9c6ze4WtLFD/oOhn+OE3QNhAhjhCmYSM7zpP/94Y4SoyPVT6ekbUG50cC66rBwGsHlM= X-Received: by 2002:a05:620a:1a05:b0:8b2:6ac7:aa61 with SMTP id af79cd13be357-8b4ebdbea66mr234711285a.73.1764053343262; Mon, 24 Nov 2025 22:49:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IHsdVVKLmwe2oMj05Y0aUe3dTPaFXm1YvlM5u/vQ9L9kjd09oWDF4kilPdJIBPHoiUnUPpmeg== X-Received: by 2002:a05:620a:1a05:b0:8b2:6ac7:aa61 with SMTP id af79cd13be357-8b4ebdbea66mr234708685a.73.1764053342797; Mon, 24 Nov 2025 22:49:02 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:02 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 04/10] dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali Date: Tue, 25 Nov 2025 14:47:52 +0800 Message-Id: <20251125064758.7207-5-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: jfucPMYA0zEpmvr-Yzk92vKSEP-WAdM- X-Authority-Analysis: v=2.4 cv=KP5XzVFo c=1 sm=1 tr=0 ts=6925515f cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=ttgK4pBlxCW4zpXUERAA:9 a=IoWCM6iH3mJn3m4BftBB:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfXz1JAHWCAOWyj 053F0gVINKsyU/CVE7xvoZi7/imxFQRYjXrsKPIH9kv1XBlnrvqLMjMd/emL1tVe4dF/SO6HNx8 xzWRpUPJPS5TnJ1EdVNEPr2qfLwXP6pkQi8eeblf0t8G+IGHGqANXBf1K/juxTYOQSWf6k2bHvk Ysd9rden4qEcX9M9RMjynKym3cd5q6MMKeMSe4muJ3xs0/GJ+vifdFxY4HuD+v3JkTJYB3QSpz9 7dYwDtm4+odoaCrh53yIOd7u9bhbrpBC0O5X8wOTFhDCzYPa4CVe6yt9FP/cZ339ndUxXRLkaU4 T1fCsucuZv3+DmWYp2Zq1o4/KKnQKon1xhRr9Id7f9fRoUACZJD91ATpQdFZ2XfAIuIjM4wk/Cg kNoFZ5AHizNwnZY1vtStkb7us+Ricg== X-Proofpoint-GUID: jfucPMYA0zEpmvr-Yzk92vKSEP-WAdM- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750, Kaanapali has significant register changes, making it incompatible with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../display/msm/qcom,kaanapali-mdss.yaml | 297 ++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaan= apali-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-m= dss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mds= s.yaml new file mode 100644 index 000000000000..92293e2b4d94 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Display MDSS + +maintainers: + - Yongxing Mou + - Yuanjie Yang + +description: + Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blo= cks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + - description: Display AHB SWI + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,kaanapali-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@9800000 { + compatible =3D "qcom,kaanapali-mdss"; + reg =3D <0x09800000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_ahb_swi_clk>; + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@9801000 { + compatible =3D "qcom,kaanapali-dpu"; + reg =3D <0x09801000 0x1c8000>, + <0x09b16000 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-156000000 { + opp-hz =3D /bits/ 64 <156000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@9ac0000 { + compatible =3D "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x09ac0000 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible =3D "qcom,kaanapali-dsi-phy-3nm"; + reg =3D <0x0 0x09ac1000 0x0 0x1cc>, + <0x0 0x09ac1200 0x0 0x80>, + <0x0 0x09ac1500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; --=20 2.34.1