From nobody Tue Dec 2 00:26:36 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E9A12C17A3 for ; Tue, 25 Nov 2025 06:48:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053319; cv=none; b=eOdPSNnQCkKKRTtNUpLzhr7ZLaMZoGbKumqIAAAylPrz9y69HLR1UpGC77C7x+IeXBHiXgkdDr7ncYosI4cSDczbPnyk3G1lS7oH62/0L3OESMv9lrnW1BA3baM8CHNfu8QM41EuTYlRGOYVaY9ywtTVKAvVCIjGTemcZD03g0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053319; c=relaxed/simple; bh=sJgfyWg3KIDNZCELmEUn2OxJam43v0UktDaButQbQgI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RsngYwaUBfK2IEfN2HjA2gPe/lFB67AdsbskswjBRG28tThMf6JuJaxv6SpurWoQhr1WB/DVI8WYmxBFh8GM+WXABOKmE/CTUo9B2G3x3YOj2S3i32ZQMb6x1Irx18CrSkLjv8LqUh1IAeQK/kS1T17lVAGfZMtm6ue0sVtKDqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ot6/TizF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=a3Ac/G9F; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ot6/TizF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="a3Ac/G9F" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gkeP2148816 for ; Tue, 25 Nov 2025 06:48:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=uka3uTpmYpZ zlyvT3E47XTXFzCZQzB9mn0T94QG8BGk=; b=ot6/TizFawuhqCorhRmo/gQyZj6 VFo7AI9lo/yMIhbdPyB/S+xbkrQrg1giT+G6mEEZCLmmjT4hgvpkoF+qyovlhFAa IH518rDNSYr41qi8eJpzaYz0JfCjQEsDO2RoYoKVR3NEvBk72OHMqsP5Wgk06ibr A7D91rDIGnLI30PSXji2rBcGo4eB5b5ql3NXiNd4TlWl9DkM24QrEG0HC9ldISAn NVEZvp6VZV+dVbZA8Yq3Mao26lE3miXPeNLg1ICjoamPGk2ArZwED65uAzKAk5Uu BDqwwbE9DV46QfECcH4pyzHquzUbnLlOg96Yj9i2gN1kLLqlL5G99/1TQ1w== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amr8sangr-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:48:36 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-4ed6ceab125so154632361cf.1 for ; Mon, 24 Nov 2025 22:48:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053316; x=1764658116; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uka3uTpmYpZzlyvT3E47XTXFzCZQzB9mn0T94QG8BGk=; b=a3Ac/G9Fd9W6nt6pYb1TJwCaXaBH4PQ47u6HZy0CvoYNFNEA1XN4GVLHpEcieH1xp0 zT0c4rmZYw/lq25YBXTzQHVTLmFuqmqbEF1pvOYsXiQdNjn1qxABVbc06+z0vsnx65cz pTDWiEFl9SMUfgYmBr0RSfjeK+f5rnSg8Rju86ZXuyDWDS+lLvMqNcVY0VqeNdYoSKaP C4Ukf6P+zc5i7jx63uX7bqFtLI+wD4MLHkWEbF+x8/LV+Pyfcg1G6lPmXrJQ20NQtw8U ZSwklACSL1U9Wcurt+2QLXHH7XfzuCWQrnj6Av3xWiX6v+/QvQIe/h26cqIXsih3EFkF b45Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053316; x=1764658116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=uka3uTpmYpZzlyvT3E47XTXFzCZQzB9mn0T94QG8BGk=; b=k2W22a+E3yuVZ85Ye7cYNh4BIaOuD8Ay1+PEwJdhFp+g44S9qKhuwsMqa6eDQ88/Un TQUzg5VRKtaCDbjweBXJ6YDfbb6/h3jY80olz19k3Ht3cchE9B8f46aRGG+Uy1AA4ReV M1KtZ12yIAKdt6+Quxfy16rWQNxq2WkBrrbf3c2/hZL2xj6phUmNC+bJDvgGBfxecESL 3ReBoX6IkgbpKGdVeEXYBL8sbXhm0buBP/fz+0Z5L3q8bgnoDHAE/LTQxR1GZOCr/niX SKBDqFsaMS+kLhHwtoJbXsD2rfreyi27nHNoOIXnCxen6XOmKQPlTvYVuQthtgFe1O4H 3sCg== X-Forwarded-Encrypted: i=1; AJvYcCW5vKfFSDYc600GIxg9YQQ8hMKphmQcRAWICe83m06Z6lGnzYUOoHDZaIiNIe72ZcIuZdgudijXVLS4umo=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4iTA+mjQ/Kn32cS0BoKqjhwXAHn/owJr125hN/aaKng9zxhdl b1xYhk3uDP+3Y1SZOj0s6omNzLj3Y/OlmP5Iqy2/9qJ8QdwUwEIkoUYb03kFInIIjwFLzyNjdZK TUc+Gdz2l/5k5syY+OrP1UffThzksCtOoeyUrIFz0Aobh1w58p5fmVu8lZiAoHfYj4p4= X-Gm-Gg: ASbGncvM91QiZuR9uWQ6JQSnIBEL7RRXvzG/rpQHL3+zDqY78kRLYvHvL1kzQMuK4Ne oUkiMiLLIPOTyb62L8oR6VA3nasWIgcVX61+y4jRgctBec31ctvN0jDAiE6DOuAOfbxGOYiYRz1 Nl2hTgtni7OlpK/q6B8E+RaEUxu2xGOOdDmf41+Jbfp1nHFEACuyE8HHgjZJmqkIeRa7rMGhKXX IOjfuMCvJ88h1DYUsTZ3WeVzpywZl3v2UNIUaC5dj10xp1svM3cbgv8nwt0RWXAmZfZGPc6tkLv U5zj0QPoY32629ws/0oVmfmhLHMtv7WL9UsDoRXoc65+7IvJhsHXs2f7xuND6kU12nHU2m60De/ B3pYtTL8uOeSRYwLw6O8pdxGNWKtxmzHlK1xb9F/uji6PQGlm3J/TaMfxq7q/u83W9pORqps= X-Received: by 2002:a05:622a:286:b0:4ed:62f2:8f03 with SMTP id d75a77b69052e-4ee5891e11amr213003831cf.81.1764053316371; Mon, 24 Nov 2025 22:48:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7Jw2MQLBvzFRC89v824DN/Tc0cUmEGvEmhJxMuJaT6Mxnhfg0N3B9zzancdtKnis4GzykTA== X-Received: by 2002:a05:622a:286:b0:4ed:62f2:8f03 with SMTP id d75a77b69052e-4ee5891e11amr213003551cf.81.1764053315898; Mon, 24 Nov 2025 22:48:35 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:48:35 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com Subject: [PATCH v2 01/10] dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali Date: Tue, 25 Nov 2025 14:47:49 +0800 Message-Id: <20251125064758.7207-2-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: k-9css1jfvhtsrkjzNC1UzKdOQy9yoQp X-Authority-Analysis: v=2.4 cv=KP5XzVFo c=1 sm=1 tr=0 ts=69255144 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=LEfPF28z9Y6gGZEU5FYA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX2tWqswuuukYB vCmKXXw3qQSSrUOk4R/+4FzrCaB0AIoLFiW5rFlaoMMLdDJDm/XkJ3EIYBPYzcPHh2janaHwMdx 0AIeBEePahmCnZ76yu5v6Yj1S20wfiopVNVPQ0ZCBOROlQrCsEEsUAJdXrz2o6xg4MBx7J1PVKz DYgq8baaOTjQZZLrvqHSiY/fG1iv/1dur9EbdTp1WoZPckbH+pVhrpmxPICss1ZmjfJK3kfS/jH Zogp7QcuSaB8spTcdXyaSC93g9i1tJCf8hxDvNkUNXorxpbnLvGOR7piCcpdMm/o4U4qDZ+BByD 9TYok/TeLqpEwcJqa0wDcLiv9BEV6adA7pIm6CoW/1r1h3LfazUMOkCsYwJxbBxD6uMZoUBZdin yD1RktxE8D+O0x5iHtpDXNVf+JFbrg== X-Proofpoint-GUID: k-9css1jfvhtsrkjzNC1UzKdOQy9yoQp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali DPU and SM8750 have significant differences, including additions and removals of registers, as well as changes in register addresses. Signed-off-by: Yuanjie Yang Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index fe296e3186d0..e29c4687c3a2 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: oneOf: - enum: - qcom,glymur-dpu + - qcom,kaanapali-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1591E2D2388 for ; Tue, 25 Nov 2025 06:48:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053329; cv=none; b=mO9LLK6NXKP5ZKVVHX7cp2jxpNFXw97OUTy3Nzp4ZGdJro8AsckrIMCtLrnZyrpt8Gs4N2RPEvzuy3lzgmNT8q0P/qDjTRDMbO07fakEFiC6BzP5jERx6uTiaSjvNIIDA7GMQLDKBB4EPYx1UZHDpeb9HloV+ZWIwTfd7WcZ7xQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053329; c=relaxed/simple; bh=vTeQ5AHKkwW/UkEd9H1rXrSNU2GbMHUYNZLpJPgp8X0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MPSeJINEI8xJ2+bY8yP36ZyqWWU16GElmKtuNVTvZT+Bk25pClxEWB0xB8FvNowwRNMurduvETjHyF1n2p1lXJ9XEloX8ei5RFGUgyTgqdBn1B1TF3ISx+mjy1X+Q47TI05y1YF0utK7G0b6bNi+d+Bb80TOOAGyW/JXGo6jgmw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=A1D1Gbnx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jN6DKewX; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="A1D1Gbnx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jN6DKewX" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gcHH1978793 for ; Tue, 25 Nov 2025 06:48:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=sav2JkTpiNB huDhe1bdSzqFnq6opp4D6AgKKwiZEkUs=; b=A1D1GbnxrdrPX9Y0bwmMKLo4dFs fFcNRG5yVSj3H47kfpiA86myucLWrR3KLKMz4tT+i21R+R3Z2NK+d/LgBTI30MIS VkE5tCBOxj50Vg2sbjAtmLWbFGCUbNff3EO4aN8xBgCh3Svq7vaGTB4R4AG/UTHk qIypC24v/Z9Fkgf0t5R4YL7feMMwv5YK9PDbMfHn2VIgxHzT8kXp9oEdAOWRqhMO fHVsz53H90rNSAxaee4HG0jhtwtH7DYSWEC1FZqQxbCLH2RQ08Y6jDH2oEpiC5pO fhqCZpLJm1dcxZeKUWrV3fo0Qv2HOZACnIwbqLLWJRsUmV/6GgknLvhUVZA== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amw9gsjfn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:48:46 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-8804b991a54so189321326d6.2 for ; Mon, 24 Nov 2025 22:48:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053326; x=1764658126; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sav2JkTpiNBhuDhe1bdSzqFnq6opp4D6AgKKwiZEkUs=; b=jN6DKewX/4CsJxlANzmF8EjebSWa+3eEyYQEJELzIvQODcUDfGKC3icscSKj1ru4uh 7R7x9Q1S4/6kUjPGTTITAaUWC39XXMOuFkXHChpnaOMFxVbE9wSAoBKyN8Ytcp1r0bV6 ije4D0CBqizS18NdKwaIu/V9WV3+tvEyiX/zdS7I+rMI5mkFA1cWNsGxnifu98A9Spae D2iF+8cGRdcidmTsC77c/09bTQdygeTwTd15GUcL1U8qFGd2Xoy/HJ4Xp/zFalgFfdg/ 3JAu/R+eJd2hMkFcuugUle3Lo5SHbKgDMGL9s8SEUXzGpVpCHJc9SoKcGTF9k7Mp1XTh LYkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053326; x=1764658126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sav2JkTpiNBhuDhe1bdSzqFnq6opp4D6AgKKwiZEkUs=; b=PrSwla0StiZjdpoqZ6tHZe/DXbbVJqaq6pXyCMSN1RNdY1FrOudUCDTLxDMASZfjjz XZHzQptN5p5z36Rnp1pU5xDLqJs2DVSMKkSflRnJGS0ya2u/PwP6t24HBgkWXmqhhWh6 rIOp9kBx2XFDj27//4Q/vdMFKhc38S/QmLEtLuJlQPvt4Q2mq5y1UH6HBxpmXvvmrw/T 0bAG6psiZFrlApx5qktpcAHdIEFRyL67kwqrUjyLwOqYD5hvHBV3imEJ9bu9fde1cOiz B+vciM0ZYymFxTyYMM/mG1+oI4mo4SSEP5myATSvlrTovFmlY8GhP1cseeAnEH6qXcB7 pMIg== X-Forwarded-Encrypted: i=1; AJvYcCUUhB/8vKXyoEBAakYWGeE93tU7Ei1o9ZViYQNVTdep/iI5O0xXCIqpUq1mqHl6zOmioRteYTroMMzkFqo=@vger.kernel.org X-Gm-Message-State: AOJu0YxDwaBzNaOGBG2s33ASeSbDq9V1UxBVRHlyKqTNs9H6HyBAd2S7 PQTfWQoDtkPyU/rjbybliGCyik3BjPR1oyxl7Ypr+ztU8ZGooevtCVBezz3Q+e7yjL1y2GZ6yCM MUgtpE0Lw5FY83jCWY3MSnSUifyYzDkV5i/LLmPPKTwi/W9+g8y588r28+jDKHuwBx2k= X-Gm-Gg: ASbGncsjtoyV/FAutOdirF47HzTkR02s94XHwd/24M2sRZsVuv6pKTn+rvBdcsfhrUK 5z8AaKSDX2ZubiC1dBZoBCtjcw51u9VVN1aB+UMHeYI0wlEkcTQONCMm3qW9Iugnfdo7GmhIpq2 aUkWOSROo5rb/qtPpmypyi73nlQ6lcG44NlBnvZlwcEx1q1cUDDyWtA7YBpjic1c9zzQ0ymS6i3 xF3NOnFaBurQMrkeW8HRF13or4tzhzLx4IB67p4pNqUOWvZU6RM64r0Ycjc3Bz0AOGCUqxqFJUW LfclBjuPX7YPK/CLsd2mn+nFuqRLK9++mk/eW73K/TqJK2TLV5yfRpdOs2gaurYjVqh8hSDiH18 Va5Qb7//4mCplCm7vjBT+nnIjL6dCNlAhkGlFYQnhElOnceKZanAUXduRC/yhik4/5rqTjao= X-Received: by 2002:a05:622a:303:b0:4ee:15af:b934 with SMTP id d75a77b69052e-4ee58b0644bmr207487121cf.79.1764053326273; Mon, 24 Nov 2025 22:48:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IH71783JNIvrMRVHdGNlmiZuEs7Iy0PRRr9PWxHrAh8mFu1oAwTLpeENpq76fFhnnNwxFIx6g== X-Received: by 2002:a05:622a:303:b0:4ee:15af:b934 with SMTP id d75a77b69052e-4ee58b0644bmr207486891cf.79.1764053325783; Mon, 24 Nov 2025 22:48:45 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:48:45 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com Subject: [PATCH v2 02/10] dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY Date: Tue, 25 Nov 2025 14:47:50 +0800 Message-Id: <20251125064758.7207-3-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfXzjQgoNF8fVbm bbeXM5m50pLaePtmAkRZLtNP6KST32qb281WfUVAtsyB1Hky8eDBf8qqS+wu7KpXhX/SqhYAlw3 u4LLcu31QApeGjpaAuEmh+Zgp9MPAEtwC3AB2nxxDEeJFqaxSuqR/p4LDw10UmMd8k6TDM/H7s5 Hn11DgzJrVhZe71FMHKGUpJvWvnzT32zwajT53l0Tg/bef8m6ynGjDIKs3nTGIvQUwQyDBvZFtx 4oLV51xqMF/bk9ODPhcb5jokAtVI/LkDE9rfKdDypWS3H8qw3JasylpZDx9obBDfLp9zJJM5DGY lffZMAIUMDgG3Qyu5y8gprMUkkaI12IOyH/NrGLJDgtkvjHx9mVmcXBJ2+cWiOUa1tAN33EBSpv 2BhCqJOHeDKWOvbBKdu/JMtgLoIOug== X-Authority-Analysis: v=2.4 cv=H53WAuYi c=1 sm=1 tr=0 ts=6925514e cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tNVMJPnUsVqa3Ada0T4A:9 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-ORIG-GUID: 0V830UGaGWSrsFYi9juuirC3JD7x4Rzh X-Proofpoint-GUID: 0V830UGaGWSrsFYi9juuirC3JD7x4Rzh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang The DSI PHY registers on the Kaanapali platform differ from those on SM8750. So add DSI PHY for Kaanapali to compatible these changes. Signed-off-by: Yuanjie Yang --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 1ca820a500b7..a6e044eed3df 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 + - qcom,kaanapali-dsi-phy-3nm - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DFCC2C21F5 for ; Tue, 25 Nov 2025 06:48:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053337; cv=none; b=lYZoeiKNolzVR+YSFjPmg+4o3VroQQZ1DGtL26YT2dvAI9BeOQypFdM9C46LihX6opGrasMHmldGqfUNocpNB3mAKlFw0i0qiZSaCOzv9OElc1Jv4l10mtAMS2EB793vmVeH4pZZXH9YBuD4cgZ4CzAuO7Sz0W8zqFSUSBnvyUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053337; c=relaxed/simple; bh=JaD7mb6XfRdztIfNyhkMYYOnCv9vI/fjXzhflA1DBYc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NW0nfA5cpeSXTkYtF6LcwHzJPi2d7WLFGnbn2Sot6o7vgkn5tZY0EjyqfD4/Ds3OqNOKF2cd4PfHRaljlyPwi9HOk11jmRvhIL4rI1Ai3Drp3mcQg5W0aBL3nPCF/LQ9LK/B45s9anGfs0/aBUdNDT0GkkW2D1MP+28Q5IKMtFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Cz5ijLBl; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=N/t8/y2v; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Cz5ijLBl"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="N/t8/y2v" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gfGJ1820689 for ; Tue, 25 Nov 2025 06:48:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=OqlJLDbVw4T n78JJhjxStsJzAZqGZdEBuegjg/h0GSI=; b=Cz5ijLBlzgvJwMtMyOD7NHXmfyX Hqgjs1vyo3visScVH+P7oI4AnXwJkUTFxeQqjhNSZA1tLLIF7fmQ7Hct0Iywdd3/ 7hUKvCmtiIX8IG2Heu7ltdBRubzoAkPvaZTrIIRGpnTm0kQWS4L3M7CzK0Jw13qA TZpyp4xNxAGS2K7iJ5xzKVr0xUObZ9HIQPoYzNMRgTa1J1ZuFq7nhQkbkUKb342r MzxfZMwhEgqC3YSKoxdpyRwm5X1CtiWLFeusJSBTVOWmvlSi8bR2p2JYZTG/LzG5 AvigkOvgUnYDIXvDvPz4SFhbP6WXFvYuQI8dIOGDrfXmDMnOd0SOfvnQwxQ== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amp6h32r1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:48:55 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-4ed79dd4a47so128709001cf.3 for ; Mon, 24 Nov 2025 22:48:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053334; x=1764658134; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OqlJLDbVw4Tn78JJhjxStsJzAZqGZdEBuegjg/h0GSI=; b=N/t8/y2vzAK+nDNrPw9md/aGzYUTymHCoE8RM6hFHR5lCfgQEE75DgAqVd66pLQ3eZ yzbi4ZYfk+HAM9Ne6M/fCPH5tLdNV5DzlueQpW8//OsTPgkOAPCIPEvooD1qZGRnSqv2 0AbmTcKGPRDrDhir880Lb7XqdnqQussS04Qn2nxX/QNo0XOOCtwPG/loewSwfMaWaeKZ xS5aPYkQGfUC6dcReQjcLwRcGaSXCCZTf1/U+eVr0RNLlOmIOxBX/0BhMLcsQcrVYLAa fJflTmcbozxe7a1MVPBfCgiLuxj2L1x6CFql3jtMHm73aLWaycYfZNUw/QtGuX3SVmIo EX7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053334; x=1764658134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OqlJLDbVw4Tn78JJhjxStsJzAZqGZdEBuegjg/h0GSI=; b=nFnU3mPifoUAQSy3Co+7AsUeYDIHU0Gb8g42Nk84ewmbFzHuZs9kaVPeIeq9czTPwN uIJl+aCG1K9D6bGjgP+buGAzbK9li+BPRfdlBkK5cPQeZ+wzg4q2+bWm5nFM1HgSeWsX NdcOjM/I9EbNnnmefwrD/hxip5JesDiTeIdEnhdzgEjYKvN4PZrzLyLShddRicivWxu4 asWARM37zibBLkCcA/SjHLdzg1EjXdsSaQZS+ItUnJQv0jgkYan/VoC10gHxy/eYN2+2 XdmLxiwqDJGwsk8VHworoJOandleOeumdM8/vGwdQuH/ijV7sRDPHfzyed188Axn70Qk sdfg== X-Forwarded-Encrypted: i=1; AJvYcCU18KFdHEiOUWPZRQ5hfu8KW7GLhHwuGNJG4/DPUbUiNrvclOSSjAy4XA5Pf+goY6Ajad+CLLYFhNJXIU8=@vger.kernel.org X-Gm-Message-State: AOJu0YyTy0DOxhPDxQ9ifDvu8q9Wz+pUgog11t98FeKaI3nJyRvmglXi plYs41d/xZ6Jsr2GjjbPHuluUUoJ8c/nqD70C80mM1PLVkxCjSU0stPckew8/6edfoBkkN5r9GR 0eQt2+NUxN2DJ1X2a+z0MYNG2q8ZHP3YPs6+3oX9ZV4q77Y/1Fp/29omRjTARK53pFYw= X-Gm-Gg: ASbGncsAaHyeDPxJUJ4fhOKxHYwL+1suGe6OvYijQ1sK4LKY/PvLv0kP06G6g5Iwb2x OV98mO/oh4rG7ZLIFIo+yOraqovvdNUhazAomrRpMOovZVI364wnT/9le7h7QOXmPrUq5ywJHp9 CWb6Ha+YugRFiC0lZ0g9ZP6ppJkysmX8Tx81l9LDd7PlAHBN3cEPQp3rSR9inuqQI7VBnNHuB78 ogn+l3KhX1wWMHUWbGZ6g9FGk/DeQb/dF2bdaF7D4T5S6jLn0ZYvSMLRCnHnxuhAwVfoFE/Qtuo OPZVvygk47QLOyVrx2SxWVN+sbpcyEUke3RlsfHPQ+i0EWrUeSDtNxf9/YGbf8qYc75RVw24ohD V6PGmg9jAXe2RWHO9XE2b8ivZ52l3u98Xra/UynbOykHlT5O8BnpFvOavQByd/TFBawEVFY0= X-Received: by 2002:a05:622a:1aa3:b0:4eb:a0aa:28e with SMTP id d75a77b69052e-4ee58936cb6mr191919561cf.64.1764053334590; Mon, 24 Nov 2025 22:48:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IFaU+K791QjFnobNp/KGKhqyUiww2Up4fYHtIc8c49z3Godcl3Fl5+c/+96X7shmR8C6UrmpA== X-Received: by 2002:a05:622a:1aa3:b0:4eb:a0aa:28e with SMTP id d75a77b69052e-4ee58936cb6mr191919251cf.64.1764053334173; Mon, 24 Nov 2025 22:48:54 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:48:53 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com Subject: [PATCH v2 03/10] dt-bindings: display/msm: dsi-controller-main: Add Kaanapali Date: Tue, 25 Nov 2025 14:47:51 +0800 Message-Id: <20251125064758.7207-4-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfXwDp41ASnzSmn 3SShWfLlo9HGwG3gI/Myo5iHpqhimorkBfBzTtUDacFrw5h0er12pey9TpwOx78BKzrRxjlYXSQ 1XfmyYSbmTry23c0N76LePMy89JVz7YbGeJ1MLZQrBLYDt67bFfSjxLeTd9vIaDklckCmBGTrx7 Y1JaoEtnIAMSFP6Bf4IpbT8OVdR2HkUUdkbaSh/+BKUAKBVZC/5FrOG5kIYT0N7Tl9Blt1Noo1D zuDZ4w6G122qHP3DI/FJpemZfHBawf/xFaP3KPrWdOcEExEFnZWskC2/osGaOQu51zNHKbZnzMZ JPmVQ5ezjs35ymAYJvCjcH3X4m6GcWobc/GDWp5lWdTiU48piZS09ip6Ta8DhqLzfLTyWRANwvY NQAaW0j8J7krPhryWyb50ptWqY1ymQ== X-Proofpoint-GUID: 6-npcvqiGeRji-itZ_qM8zS6XLN2DdcJ X-Proofpoint-ORIG-GUID: 6-npcvqiGeRji-itZ_qM8zS6XLN2DdcJ X-Authority-Analysis: v=2.4 cv=GoFPO01C c=1 sm=1 tr=0 ts=69255157 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=NRHHWUy0EX9jfUzwrTwA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang The DSI registers on the Kaanapali platform differ from those on SM8750. So add DSI for Kaanapali to compatible these changes. Signed-off-by: Yuanjie Yang --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 4400d4cce072..536ebf331828 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,apq8064-dsi-ctrl + - qcom,kaanapali-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -369,6 +370,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-dsi-ctrl - qcom,sm8750-dsi-ctrl then: properties: --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 471B12C236B for ; Tue, 25 Nov 2025 06:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053347; cv=none; b=uGEAhxY3SBN9n1CRoLF9R1CIA3cMC6v72Gk1mewN9CVNfNZ0x93Yz83IB7SiKeoePsKJLBwunZoZqpa0tusEERe66XGJiqx7shHZ/7LFuiV0NnTlIZXvbKzrl/dzVkOQ9eSUQQIVEC0b7dtyM6Kf8SGnxi1v+JJ/IGlX7ghkgHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053347; c=relaxed/simple; bh=C/SRBt/7dSGnmJr1VczwjK56l7+Ma6+LmugqmP8ce6Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qTpkflTvXUX5fpWy6ACeepE+nsOtm3C25+KUl2vzWmAzA20henzeqILSs9Yya4KSyfhzb6fmntsLHPfBedSnuRqk6OWyvDIaDGf1vICi72EJhggH8Ldnsv92hUh1wwAq4TDywl+2Z8gFEQ5B5qb+gU52adjhB9YICe260biGa3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=DdcUgQCc; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Km7lpceK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="DdcUgQCc"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Km7lpceK" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gjmn2148813 for ; Tue, 25 Nov 2025 06:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ejOLCXs2H6V eH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=DdcUgQCcQkqhWxddtSUrQAFauQz HagkaneA6DB3ZSj/laGX2rbSj+i/XPn36v48RGK7hOZnEtqwNJpYd4s8fIpEhN+h G2358jOI5j/lxEGPiCA9PPp9Cj90YHwrNeOVL26oOEcMQbkrQqGctsblHthNw5x2 PH8jZoJVNiSkqzckDiQmpkEbZs/DQy4lZj1O0/w76IiXQ/Y1jMqaxM+bBCHZ17SD KONIi4wQYMNMI60P1ghH7hQVGL/nkq0QifxSCNbuoxO/XATLZfZGWW/PJmAg+BBv 6bxj1LKPLFpQJ6/OfxQ4wUKykVWi9qPhPACegszgblL5IpKKbHQEIKquMuQ== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amr8sanjh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:03 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8a1c15daa69so338872085a.1 for ; Mon, 24 Nov 2025 22:49:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053343; x=1764658143; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ejOLCXs2H6VeH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=Km7lpceKUfJiEsbP1G5Z9YWL/MWoWCyQr+2DFP++sY8N+o8ds/HTXPeooZJY0OsVIV 7GEusuzOrUAYFK9hD510YCLUEH+d6mF1IAXqQGVVjrOnpj1oZshM9Kc7FmQxxg7v7IVl YP53oL5KbGNZXBdF9k3Oi0GPYE7avMmUrOqiRmeO88Mn4DTw+16CJjnrrYuRtj71+2F0 QLAUsvP2m4Rjo6a9bwe5d9ieC9iftNN14csdYuvZZuxkYENfR+G+8w3J1Xibo/Rk+lZv lj+63Ri8Mqt6qcQI7Y5wZxj1pDEyuSOyqdrUSSpQgOFja139uy2Z8mR8BLeaQOJiFRVV 1IQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053343; x=1764658143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ejOLCXs2H6VeH6zAgJDf6kqCLHfca0LQJWts7i4UWpM=; b=hZ/Xts7bjx0WaLoEGWAQgnMd/rSfwiiICiU3Yw7xB276/SOvd5e+URSqgA5Y1Hykds INyHMunSqsblYrt2C81g23hsFeTShC0PqUFvhgtBv38yWQ5wTQgRRdoBWjumbmmkMqfi S6lKMVkO8Ce7FnFSJvjV7JskNiTW1QUDu+sDPamPFST52CRZFZDtFrgIaNlIF1V4S494 tUiMUIc5J0nhznrymPlDIB3lWUCEQMrTL2UifXx6JeiBSrDD6p6gjrtktjlpVf0Rh19x XhTErI6XEvVf2FlD+b9O9zNUdG5tXutiXrQWKg1uwvITacXNZGG3fUe37BZTEiiRj+zs sJKQ== X-Forwarded-Encrypted: i=1; AJvYcCVq2/qTOPDP7C7/3tnNzubfV9liEcrKW5SvT0F0xmXSPSFFadI5+kCA+wYxOSfQA5zh/v4tTUgHkkbWnJ8=@vger.kernel.org X-Gm-Message-State: AOJu0YyqHnkEMpUplFOIt73DF+Zp0Mm5F+XiCbzVx8PyexmJNsceXOUM pPgopmnED3gl5yutYIlZxx1rDttji3DwhTioUwve8SkRjGFhqZO3dMOOQVi/n4ZpDB8RgaXJ7gP ZjPcd1n26BoDfyU2wYbO/oJs4GnEPekSVsliyHUZBslX5PDcJTOIC+a104Avzc/K6bPI= X-Gm-Gg: ASbGncvhsVg+73BlRc+eMc6HXjyN1P6UNDI0s8/oMfKopoR53+CXXJ8WR6JCQWdIFVS KmBI8Uvh17UrAaqZawW8C9XOrrELatJ7ww74/YO9IgFmwD+ilm+VXs8aFzRD2Hotqhs//WmVBBB x8Z7f0aJrlYr+G5VlvdN+8J4ZzgLkNplRcl5IzyxBpfNLeYMb2ZVPBSfy8N+++8a6qiVuWyiDOA 3GG0UBsTPAbzu+ya/Im5sJbNuWTAWJRclkm1Pu4szIvfjP/DcJaa7PsAiE9tSwbp2lD6g40Mqy/ H1ZA84jGQB0SNMymjwPhTmdQTMqSPGb+7+nZGpkn2V59lG63cPik8WPtH3atex6wnDpP9AKQ96t xJecD9c6ze4WtLFD/oOhn+OE3QNhAhjhCmYSM7zpP/94Y4SoyPVT6ekbUG50cC66rBwGsHlM= X-Received: by 2002:a05:620a:1a05:b0:8b2:6ac7:aa61 with SMTP id af79cd13be357-8b4ebdbea66mr234711285a.73.1764053343262; Mon, 24 Nov 2025 22:49:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IHsdVVKLmwe2oMj05Y0aUe3dTPaFXm1YvlM5u/vQ9L9kjd09oWDF4kilPdJIBPHoiUnUPpmeg== X-Received: by 2002:a05:620a:1a05:b0:8b2:6ac7:aa61 with SMTP id af79cd13be357-8b4ebdbea66mr234708685a.73.1764053342797; Mon, 24 Nov 2025 22:49:02 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:02 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 04/10] dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali Date: Tue, 25 Nov 2025 14:47:52 +0800 Message-Id: <20251125064758.7207-5-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: jfucPMYA0zEpmvr-Yzk92vKSEP-WAdM- X-Authority-Analysis: v=2.4 cv=KP5XzVFo c=1 sm=1 tr=0 ts=6925515f cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=ttgK4pBlxCW4zpXUERAA:9 a=IoWCM6iH3mJn3m4BftBB:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfXz1JAHWCAOWyj 053F0gVINKsyU/CVE7xvoZi7/imxFQRYjXrsKPIH9kv1XBlnrvqLMjMd/emL1tVe4dF/SO6HNx8 xzWRpUPJPS5TnJ1EdVNEPr2qfLwXP6pkQi8eeblf0t8G+IGHGqANXBf1K/juxTYOQSWf6k2bHvk Ysd9rden4qEcX9M9RMjynKym3cd5q6MMKeMSe4muJ3xs0/GJ+vifdFxY4HuD+v3JkTJYB3QSpz9 7dYwDtm4+odoaCrh53yIOd7u9bhbrpBC0O5X8wOTFhDCzYPa4CVe6yt9FP/cZ339ndUxXRLkaU4 T1fCsucuZv3+DmWYp2Zq1o4/KKnQKon1xhRr9Id7f9fRoUACZJD91ATpQdFZ2XfAIuIjM4wk/Cg kNoFZ5AHizNwnZY1vtStkb7us+Ricg== X-Proofpoint-GUID: jfucPMYA0zEpmvr-Yzk92vKSEP-WAdM- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750, Kaanapali has significant register changes, making it incompatible with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../display/msm/qcom,kaanapali-mdss.yaml | 297 ++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaan= apali-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-m= dss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mds= s.yaml new file mode 100644 index 000000000000..92293e2b4d94 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Display MDSS + +maintainers: + - Yongxing Mou + - Yuanjie Yang + +description: + Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blo= cks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + - description: Display AHB SWI + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,kaanapali-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@9800000 { + compatible =3D "qcom,kaanapali-mdss"; + reg =3D <0x09800000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_ahb_swi_clk>; + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@9801000 { + compatible =3D "qcom,kaanapali-dpu"; + reg =3D <0x09801000 0x1c8000>, + <0x09b16000 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-156000000 { + opp-hz =3D /bits/ 64 <156000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@9ac0000 { + compatible =3D "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x09ac0000 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible =3D "qcom,kaanapali-dsi-phy-3nm"; + reg =3D <0x0 0x09ac1000 0x0 0x1cc>, + <0x0 0x09ac1200 0x0 0x80>, + <0x0 0x09ac1500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 738262D7812 for ; Tue, 25 Nov 2025 06:49:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053355; cv=none; b=B0N1jlLulIQCNGg1sAa6U90y8NW4nh7fTXkSXPi4ez8Tgk7hej4zoJGfpe2ZNOF4zG2AH8ecKAmnbrwT4DIoXBm+2p6ibsc6fzQn8XzPGy9Dzh4gGSQwbSOyKOTHTZEyNW6ugf2bHS5H8jI+lRHpn0I8EFQ9pcGvC8OjZSu/TLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053355; c=relaxed/simple; bh=Lkr9nURjaF/4X10BCp6AkVEKptwiYyv1SOrxAC89O/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+34RpGy+uJnvVJ+k118e0XVDKSxvVfMNu9BP0n+gtAPaEYlsl9IaQ724iqn+SqIpU8oqqCZovm0nC/chdWAZunr/FHesw1ZFYyQNcheTSurKGtsi6/+G3DMD4X+7eewStnAFeUoqMutqU0GbwZLeq8Kq3pnemCrK0MYbtm5aWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=F+kxnB4B; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Agx0y4+Z; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="F+kxnB4B"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Agx0y4+Z" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2giXo1741142 for ; Tue, 25 Nov 2025 06:49:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=sl70Xakrk/Q WuTVO9HzpUuERYvoGu0ruQzvOAyWXJVA=; b=F+kxnB4BHt1771E/s27KGl4vZuO ji8uIBVxgAtc5jlyJX+jZc33agIimP1nJw3p9GmWMjweTmrdjTerZkWj9GMCaBjE /kBZptiUZC7pVh3IMBfbzsAFANG6SrX9lbxdutCuPsqzCbYj6TOjSmcpgFJF0bVm QZDfisUxkFu1VEoPx5tULR93GhSCqeNCU6bj59YkdOeX8KdBGOBpwatP/TZJK2ac 9177VB3b8TygmF9bi1UimgwhtEKdcWTBtRKJRz12VlRJSpL1YHK/pQmef86RcWtc 38tUF3X7YNflRC3lgBkfu40F1SJyFCeiw/SCXnX3hmBf9CxptNApl0AAezQ== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amteba844-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:12 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-4ed69f9ce96so208392091cf.3 for ; Mon, 24 Nov 2025 22:49:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053351; x=1764658151; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sl70Xakrk/QWuTVO9HzpUuERYvoGu0ruQzvOAyWXJVA=; b=Agx0y4+Z6ezwTSohYMnM1Vv8P0ojXc2pl0yqKil6NKMY2b6CIOlLZ+80JU1fdcdbkZ Y8Fbx5X1+7xZfDpqkuQs28Y/ZuknHVnL7DM62P7EOYBlgqdsEsvbUjNX2NFWqZwDh7ET ThaZrghTxyh/DQgHLhWADaFs4jUl877Khc5IsPmZWV+SHDU+In9TQz1I9b4PyHXaL5qy 9LkMWUe2EyHRG/10g80BEna7dyGQ6rqXY4sHzHm5cZuQSHQ2194vOdS9856Rkpj6OGQf g0P6o90x4tCFcdSYhLCDC58UretjtUkJhEeCecxHa6+jkeJffUVXp/wxuZRuBeUg717a Wohg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053351; x=1764658151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sl70Xakrk/QWuTVO9HzpUuERYvoGu0ruQzvOAyWXJVA=; b=OS1fiAoMbux3yazIeyet186q4fJalDMD2kqShJzTbnE493BNlg0kCe6ku/C7Nq3+vA unqsFkTnJbylPtGZSbwAp83loJ9ZCC+XYrZAuJX4rF8latVCzPAVNTgpV6GAruOHpIAv pRbCB06XXshodxQMK0Ey/4e/eRvCGtpRD+PO1+UVzl4uUPLYAh2kKDTOX8KTtV439J+R uPNHnT0B2ll3uNfkCdTCuW524XoyF82vOJcXOBVw66IHtWtnCgxFHhqJBxRIrnPCfq2R HGbgwO8OCaAtF444OCI56SrYm6P8YRJ+aFOxPsL8bnDf9Hg32o3sVLg8mSqTnzIwTQ8M pJSA== X-Forwarded-Encrypted: i=1; AJvYcCUl563s81fiyygfRVCJHCYN2kLMKL2jDABflZ5+8AlfuIudEfrnfxjeBj+cyGH8mN1JY3sXiqFOrYs+ETY=@vger.kernel.org X-Gm-Message-State: AOJu0YzSt+t28UrQxRIM4Gx0e34uRn7g1Q9KNW6AnTYAYPupJ4d2SVzR RLFGqfzJVubKEia2+wjx7zOQfX6fo5VkBs7D/8gAVCVta+3vWPkTZ6FYUqsWgSCZ/f/aUim7+Su cyU1gJiGNMHolV/k96o8v8lSh2wwLuhKm3c9DL7ax0/duPSgjUqDKbPnFUqf+RTp2OhY= X-Gm-Gg: ASbGncuea1FMG/Mdjab0WsM/fGXzm2+rVsuWFcFswdVUOAMzr5+gzQfnu3H3s5WU8dO UzxWiAinWeKCpKiCUiHpGwu2DjrgaRLkNg2R+QIW0VHZ7kID99B13Pxiz49bTzCc7z5yhuCxZau YBTqOrDbvNw5fuybsAsc9Y82CFwbPxvySa5QuHPQfzqAbJ17P76iWnKw8lcWtMY8dMfecf7gsg0 s+tOQHsVsBp92N8WrfeGfQ9BwoSF+2VzyfV8mr3ZDKO1fb+sGh5FslZOK1oM32PfHJjcoUXU60b wJFdqwGls2j6JbjVNlr8arjSeLW+fxPz0jW5bi2QqKkUcxFbbYBIE/+vAXgXDX/j2cJ6T/6GSa4 JzPPrSUhU7iAeNrD+lMwcKgPLD+ocRXzDU4GUq4RvTfmUK/LTxpwPnptQnewhLD/gx7H021w= X-Received: by 2002:a05:622a:98d:b0:4ed:bad6:9fac with SMTP id d75a77b69052e-4ee58a446e5mr170268761cf.1.1764053351621; Mon, 24 Nov 2025 22:49:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFiZgA3RMR7QzcGUxzPh5hdymLOsFNIYBB5TZ/d/l1DFbwPQDvEADrbvlT5d/ZAyusRDJhjzg== X-Received: by 2002:a05:622a:98d:b0:4ed:bad6:9fac with SMTP id d75a77b69052e-4ee58a446e5mr170268461cf.1.1764053351283; Mon, 24 Nov 2025 22:49:11 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:10 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 05/10] drm/msm/mdss: Add support for Kaanapali Date: Tue, 25 Nov 2025 14:47:53 +0800 Message-Id: <20251125064758.7207-6-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: cMwSUpWh1GYzecOOWFr9k_y1Ng-5lt4C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX9JBv1Bg2zAFf I2GB//+jTZdbUncduC/SVndEtN5TRKwLKxRCpZgPd+xD+8+DKEkaMJsI2RaVXtZZUemCqvUm5R1 6MdWqK0AJT5AoCpRcEzzcHEo1QwFcdNSZABMvfS2Vz/q9+i19YZvCONoufrk/KsgYhHRCPOvVvt 12OtFfbSqa6H3lU0ASZaZ9VJP5zRr/VNZt4y7PTG0zAoDTAk/SsTngtTJRfwWr5OyQ6Sz6+3jFn HkXNCeQ5Ji5oRGb3df5MZqlniAAvZyMJ9y28GzhpzGgExJNl1N3Cf63JZuEt0k3bXrGXaLyRjsK 7ZjtewV9xH5YHL4hgTbUDt6eomANSwMPmhGUK899f50KXxU8T5lS1gh2HpoZnlIrmaqiF0Qmbq/ VDia2yQyUfPoO+ZcYs2JXRN9LXuLmw== X-Proofpoint-ORIG-GUID: cMwSUpWh1GYzecOOWFr9k_y1Ng-5lt4C X-Authority-Analysis: v=2.4 cv=d7f4CBjE c=1 sm=1 tr=0 ts=69255168 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=74ENWJKDy3Vb_L2bHi4A:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add mdss support for the Qualcomm Kaanapali platform. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/msm_mdss.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index bf9a33e925ac..797ef134e081 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -243,6 +243,24 @@ static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss= *msm_mdss) writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } =20 +static void msm_mdss_setup_ubwc_dec_60(struct msm_mdss *msm_mdss) +{ + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret, i; @@ -296,6 +314,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case UBWC_5_0: msm_mdss_setup_ubwc_dec_50(msm_mdss); break; + case UBWC_6_0: + msm_mdss_setup_ubwc_dec_60(msm_mdss); + break; default: dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", msm_mdss->mdss_data->ubwc_dec_version); @@ -552,6 +573,7 @@ static const struct msm_mdss_data data_153k6 =3D { }; =20 static const struct of_device_id mdss_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-mdss", .data =3D &data_57k }, { .compatible =3D "qcom,mdss", .data =3D &data_153k6 }, { .compatible =3D "qcom,glymur-mdss", .data =3D &data_57k }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1EBF2F7AB4 for ; Tue, 25 Nov 2025 06:49:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053364; cv=none; b=D7ns5eRalHyvYfN4M0tDRE8Fta6VsThE0pKFbrmCRzt0FFLhyHFQxZCun6MAby1ih8Sco5Bm/sZGb0co1vtYNdtlv7eERefhwhaPXpZwq5kr4Weob/ehVv2Zc6oo8bLWUxNNkQ9kdqMRsQvlE1vrlTcmKHJPVDZrxd0AFNUF6Oc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053364; c=relaxed/simple; bh=vuUrrskU23wX33PjpqTBcL/IP1cl943DrlpkwCNd+WE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JU/6lM8WGe4GQ6sGzz1uKvN5AnB8D6+KYmJd2DKRKZXE235L/8w++StFEaNnUco61qCK81iZzihQBARO3/9f4CDTVAv2BLqbYHakRTkLQdnGywaQQw4dtARGkmMOMbtoZTHN+XhB7xkvGvxCq499KcbSEimWnG970KQ+Vy6ATGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nGru6I3e; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gVCeGBty; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nGru6I3e"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gVCeGBty" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2ggM11741105 for ; Tue, 25 Nov 2025 06:49:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=mTEpnqQDbzn otcGF0MdKYZhvxCR/jGVEFQI5zYSrPmA=; b=nGru6I3eZC4Kcyl6h6QAt5wjHNE p54D/D6y+YCW+milCaEbwqgSkbm5emB1ToEVha66h0J3d5C47xMcRadiuKI5aq7F 17g5V3LcFsMGQVphlPRLd1KJ6FdRIwUtbfMa2wbOPM3e3nD8EBd21tCR/exefokk KD5s4ZZ4qfHXSqkpaaZyWQVYvbvg22xxzRuEsq/1mSzQtW7q2DJ2oUCrSDNA5rA3 VZNAAsfRP84O7IepjIGTxO6PfG/WCBPcnJkvJAjtsPcHjAWE/rjXnso7KJdxy3Zs 331vKNQ4Yr6svyaXhvmEtuZGXCTep3Us0zNCIb8Y+GrRqUPCTyaSZW7JPVA== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amteba84x-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:21 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-4ee09693109so110912651cf.3 for ; Mon, 24 Nov 2025 22:49:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053361; x=1764658161; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mTEpnqQDbznotcGF0MdKYZhvxCR/jGVEFQI5zYSrPmA=; b=gVCeGBtyAoiGlmhu/lJ/McuKX4nhfAQdeWdUwbsuSZj5RzhlZpGsvFspz8pEe84y+f EAIsywJKcFNM9mXlpcREEBq9FXywhedvSoWHXvcLxgTq7dHd9lo/Lii68xQY4YkAvk06 1tEz3vm/KOPvK2/ci/Pe4sPhEGs8BlQKdVlHsyky0ILZvv+NuURhKw4qoqISsOw3kdTU 50Ui96OpInFHrLE6kYmz8zX8r9aHBEmuhKSPas5FFvhmBeHU4b/rA8h5RIZ2vARloZLS EnavcdR6Y5uigf1H3SRu0g3Isl2uZsQlU1ucgLUgSCqVYLnRp5BdNFiCVScOuozztjIV OePQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053361; x=1764658161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mTEpnqQDbznotcGF0MdKYZhvxCR/jGVEFQI5zYSrPmA=; b=w6WNWO/eYnFNDrVTzQf7IMbcTvgj7yHRkYJgNgBtzdwHnrVJta/Z47gcKu988fv08T j7hwDS5lQZOOiFO+hXelD8ckiMyHcUirNIKBEBYfg6pXZ5IavUrCejCbsfKZ2929V/n9 q6/XUpONgdOpHXpE5W6omN7De9AMuGURmnrA8sIpOHcjT6af3i5LLezSmOZ1qOZJ3NWX hP5+Ni+fCbqLFedMHO/d2rHHAPqyTFvAe4qs1G4mQcgK7cYLRMA7ruuHIRhBuboEQnj7 ka6wu1WNdVSLQuRuu8prLhVloq2bJ0Qc0ZquvfQ7gr2+kgaldXzLFblHYVspZa3sWLIG vCjA== X-Forwarded-Encrypted: i=1; AJvYcCUf7Du/3Zcu7ZTC9YJdG8drPBiwc7/Yx0i33QkTwHMlQ3/H7ATTqboBfukENLfmd90QAIqH7MCuSUKEDSg=@vger.kernel.org X-Gm-Message-State: AOJu0Yy1mKJtN0hag0iDNwurNxQtV6dosLDKsT7q6+fHVg7TGrimVO3b wqEnTnpN23RwaAKnVqdPEgyzqNSwtVfk/CJPAwlAmwYTsZTblOmsoUni8i57Cd4W2tiuc3+AUuO pMurgR7WLJ+4n/pBPyNlpNXz1OVXDNoSLPQdyMQUnvDRgBC6+wKi99pIco1zeOYoB7IM= X-Gm-Gg: ASbGncvc1w+YRbFJ6la6k4Q/XcKjRkDHWIgurszIiUsB/hn6D8e5lLR8kHJKcnxxc09 zwD3e2jG1IHOgHT6+Vn2YJe1VN15VfqMYD+cD3YLZesNxM7kUxCZ8QfS4L0/pWZgQshV4StY3B5 ubuEj9W71h0iN0xSiAbeK6caMHdG0r7wCIpP2AQopgwvT1FB7l6PnR7SH+z1aK07oKxoxiw82aI MC+pEAPz4Adf/Bib7RRfz0JqD6j5JHx4kpXNE2RMNY+RJuR0EmNg85T/uCHwMrFgbznMKixsCdi 2MIZZn9C6Wc06KRD8NrpWT8/PPh7Jm679NvhflcM3vGurgvxzOq0sQzkOQU5z0XKDlNW2cC0Aot HfCiYOWHqF2I7qsTupWI9A7AT7lGXEpGpLR4PnrysGfa0w/Beowk+6xZrwEfAP8Zb1G49GNI= X-Received: by 2002:a05:622a:118b:b0:4ee:9b1:e32 with SMTP id d75a77b69052e-4efbd90ca3cmr25012851cf.12.1764053360735; Mon, 24 Nov 2025 22:49:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IGplJtM6PIhFpmRcTZ2wr4latOAgppymuITWXHdQsTlNhCo4gWclBzktAKtg0xrwFlPEesmIg== X-Received: by 2002:a05:622a:118b:b0:4ee:9b1:e32 with SMTP id d75a77b69052e-4efbd90ca3cmr25012451cf.12.1764053359837; Mon, 24 Nov 2025 22:49:19 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:19 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 06/10] drm/msm/dsi/phy: Add support for Kaanapali Date: Tue, 25 Nov 2025 14:47:54 +0800 Message-Id: <20251125064758.7207-7-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 1yeKomKVwdg53PvM_isAl-TL_s18-DDW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfXyTbwekSHYVap rqKtbf7vNw1FxE6hriLCXNpKXatTDDrr847pJDwS6m2vzAaxgGLhHx4JtKct2aDmzMMQCloTngG 7BBNLnq2Kc/YMCmp9DJaCb024G+SZcDOPqPpvbTMItrOl9O4qqXfAOajeTxikD9bN93o+tfGLnb Son786Hp1OWzY2sAuKeExgpIL3FGQO9nbQDsqSSowFJSfACCsNRF6IiTdSr6M+nLaAjbwqrXKMR GNhfnpvWlXjvCQPL7Yn49+LCgVMbTD/L4FHxNEMOTtpmW/aiDNJbHvQ/iFY9QhyF7Q/0q3KEzyN gsUotnZpthKO7KCHS7/7Mu1ei4bwyBsmlba7xsq8T/2v6ugQBlhbkZWsp0rYGkvf4H9pks4IFoU HH4v68w6boCgjfR0ZsdMVvTNVTkUNA== X-Proofpoint-ORIG-GUID: 1yeKomKVwdg53PvM_isAl-TL_s18-DDW X-Authority-Analysis: v=2.4 cv=d7f4CBjE c=1 sm=1 tr=0 ts=69255171 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ab5uJhi7KCXt4xzmVoQA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DSI PHY support for the Kaanapali platform, kaanapali introduce addition of DSI2/DSI2_phy compared to SM8650, However, based on the HPG diagram, only DSI0_phy and DSI1_phy works. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..7937266de1d2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8650_cfgs }, { .compatible =3D "qcom,sm8750-dsi-phy-3nm", .data =3D &dsi_phy_3nm_8750_cfgs }, + { .compatible =3D "qcom,kaanapali-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_kaanapali_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 3cbf08231492..c01784ca38ed 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_= cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c5e1d2016bcc..8cb0db3a9880 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1504,3 +1504,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0x9ac1000, 0x9ac4000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F6602FBE03 for ; Tue, 25 Nov 2025 06:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053372; cv=none; b=mNXykXkxglTPwmhMBrGXq7Bd3ZlTomqh0KE7l993ZsOLwV4HMRfmPxQ+ajDNjIvqNoMZ55j/T5ZaGHxswiuVo4X/p8i6vFYku25Rji4oYosRf1EjSjwGJU0+rvP+qivXrxQs9wLloWiErIUjEVIc9G5uXbbim8R5RbEtd+FQHuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053372; c=relaxed/simple; bh=pryC3efeva7N8Mb8bqhAcLUUN+nF1bsHQT4thpYUZ4U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OAGpvGg6dJXI96FgMJW8BsA+YmKkk+MH+BO2MyzuoamazAhy/jUwL2dy8pP3Q3tFB3omDxa7TMi9GHYGaWZ3gJCbRuJjhpEIycBggp5N6MLaNaYrLpFRHhna1HF7AO6sVwvRkhsuPyxrdof8vwKzfJuNoilgVG1X19AEgVIAjPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FzGbr7hU; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=idZS4EBC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FzGbr7hU"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="idZS4EBC" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2hL0J1233477 for ; Tue, 25 Nov 2025 06:49:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=OMLdFutodWp WHUQwzTx9cYTOE2PbYgwc5aWDG8hPTMs=; b=FzGbr7hUJh58BwhxTL7jr4/MvVM d1v9HaelRvizsBBOD6RCFrBjvkKiB8WonI0EVHh6WemqUaUV0yAorgKbP4SW+AKT GWsefpJiht89SYwlRQpefVTZdvHhqaI2e/0zVHVjH9sD1ybMOu1i3mUtn42Kjmpb 0bwIuU0dm6sFWeNNEranwkPh4OpBYLiAes3QyDRaSpoAkXCc+mDutU+62l+Dn8kW Sv0Z2Ov17Bb49afLEwXfbuFqb4lFz96KkryiZRMTp7KHyhQqihIwG5s7wsSC7nti hkDpGxOlPhXXX0paxMbchyys735MatGGbMcdWGLjU7PgTCXIUI3wmA8ILbQ== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4an0xyh34x-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:30 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8b225760181so565884585a.2 for ; Mon, 24 Nov 2025 22:49:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053369; x=1764658169; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OMLdFutodWpWHUQwzTx9cYTOE2PbYgwc5aWDG8hPTMs=; b=idZS4EBCjzLhXcTbiC4z9XHqysXyhkjwVSmiETXM37EiCt6dH/UuZsZuSTzKjkuj7S nnDrJsJm+pv744LiEafdT4TzXdNL5ks7aBurc624pUyIUxS8ryFVK5trKCMS7TEyvzxu SFZMSX6rLQqqam55zU9bluuD+FFLN27dTf3GphiO7GQn8jroHcNzA621B64oRMqP3OQx 2nTvAjjZ+LNNwW4ltQRcoqDfEp+/PAmUR4+h0BBAh9HaEaUCf3aNkpzAfhfbHR3UE3Ki 0d4izMxlO3tLFE6joG7KmLDxF2Tq/6Wg25isKsi6lGqA+thbQ2VHcc0UN60jIl2y+JiP c6/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053370; x=1764658170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OMLdFutodWpWHUQwzTx9cYTOE2PbYgwc5aWDG8hPTMs=; b=UAb5QrurpewweHRZR3ZgBTIvLtgyXWHJw+GcPquqNwyZZWOIipkF7J3Sz0Vhj5iEg9 ZhQL/gMw+sO3dM2cclBCARtgUZhap9ea3jLbvorQqAsZYpg+kNxAYJxHoyo6k9qXYhxB f4YIh2E49lOBJbdisvNMEAJeeZ8YfBWdIF1S406g2keWI6K7aKhgzFkHHiSy34rwZrwx 01CWaZN5GjEDldfq7m/6NUHj7V9llwfGfaRIj+7YfitBd5PgD7tfbF/5rPYN1S7hLuL9 GrNqEe5UZ/DJukMLsrDOGSmx40v0cUgItOAkPNDVkQKGJ78kRkMgcDVDWJZaV28gbfs/ wRTw== X-Forwarded-Encrypted: i=1; AJvYcCXIh+VtaNVXHmsHOOkbt3xQ+h9F8liE3pOvnimtREgBHxLkjWn8yFK9lsLHGP2TSVCQE0SqJbpyJzp6W84=@vger.kernel.org X-Gm-Message-State: AOJu0Ywe0MXD/N385tTwZu/JT1Tajx4T9CLnyIS0FJi72t0vchlZXwkt v7lSdbBGANt/T2ArY9GHq6IEch+oHQbbWk8z0AYF7fiCyxSkWNZYA8IzystA905MWlZbMP8kUqo oP45DoHSkZ8bSJO7wWL6RgEoxYCQrcpXxkTSrSJIHSNMVLKouFwigD3c1/HrnRI/DVdU= X-Gm-Gg: ASbGnctDAgyael61gDteNkI3tIS9OMaemt1VHjaM+A3gGGgrO9rWkwV7sd43a8q4zLS Ounj2CzKqa/582TNr0CtxvbzPEyan/LsWWDgEZOV2jNovW+RV4XBPyIIlBRDeWMNeHawSdFG4gp cdtD29vl+sFV4Xevm7cC8Q8+4xFBqspaauLto0vMVboKJ3s13rQdIxmF7fI4U0YvpuAbm2RzN1c 6s+WrX4zCoBVrfZK7q0v6O2F9BX5vqM3FJ5T7qBdxNIqwaAlMY+l092PbZqazAuD+DQBHRJ7vTd ybYqym4nzVWq6bO5m2+cRgTk7qCH1feoReC96bhJ6lCUj0p0FrT45VB2Pncu67n6ypH33Xf93b3 6jfXpYcPFP9+5+ZsHZlyid9MZzVhpui7FxEwIxKitdLojLtP0QmGTww9jLRj6NqJMWP2az4Y= X-Received: by 2002:a05:622a:1b8e:b0:4e8:83b8:9e7f with SMTP id d75a77b69052e-4efbd8ca5d9mr22384131cf.14.1764053369632; Mon, 24 Nov 2025 22:49:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiWneXixXB3xjrJUwkHgPebGASZPAo0VwGDiJADDtvYnesA26C81fRxH8HLYpaCJG40TQhxg== X-Received: by 2002:a05:622a:1b8e:b0:4e8:83b8:9e7f with SMTP id d75a77b69052e-4efbd8ca5d9mr22383761cf.14.1764053369213; Mon, 24 Nov 2025 22:49:29 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:28 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou , Dmitry Baryshkov Subject: [PATCH v2 07/10] drm/msm/dsi: Add support for Kaanapali Date: Tue, 25 Nov 2025 14:47:55 +0800 Message-Id: <20251125064758.7207-8-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=S+bUAYsP c=1 sm=1 tr=0 ts=6925517a cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=EGddA7oXPexY6v9tJfMA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX3I7qLprM2X21 q+zxyokMfkDj9D1lhKorf3hLw8cc5JJKw+RcmPfxF7bHDvRlEpALwN/JAc0O9ALiWnu2YPjEoLn QnCMGtv09G1Klt5IjzIJENWnH6hKfRIqNwqeW6Q6ZLxjYPMgZzjdjcERdv65hQRpWzp4eAOipN/ vc9CBTyrtj2LYt4jXjk2GKC9klqL8HLtk6LiZgFpJ07tdegmwZaWubzrAoCFSMjHv1U0v6lYhn7 wl6dzcwkIcHZr+diqxbPrtngDDeJL+IHjKrYfDp39BWJ/HRxuMEWCts1FO0c7dW4JIMJh4dFmLj HBLPdDJIKBlXOaSvTLp7n/twSHvFNi4r1j05yRgY/zlljtyYNeFNbDp+Vf6eTg42nVEs8Uo6nSu uqsOhI1Hz4OeCMGbkNTS7xprJMMQkQ== X-Proofpoint-ORIG-GUID: Xk20dB92o-KCYkeRmQrHm428tRxeTvPo X-Proofpoint-GUID: Xk20dB92o-KCYkeRmQrHm428tRxeTvPo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DSI Controller version 2.10.0 support for DSI on Qualcomm Kaanapali SoC. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 13 +++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index fed8e9b67011..bd3c51c350e7 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg =3D { }, }; =20 +static const struct msm_dsi_config kaanapali_dsi_cfg =3D { + .io_offset =3D DSI_6G_REG_SHIFT, + .regulator_data =3D sm8650_dsi_regulators, + .num_regulators =3D ARRAY_SIZE(sm8650_dsi_regulators), + .bus_clk_names =3D dsi_v2_4_clk_names, + .num_bus_clks =3D ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start =3D { + { 0x9ac0000, 0x9ac3000 }, + }, +}; + static const struct regulator_bulk_data sc7280_dsi_regulators[] =3D { { .supply =3D "vdda", .init_load_uA =3D 8350 }, /* 1.2 V */ { .supply =3D "refgen" }, @@ -332,6 +343,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_10_0, + &kaanapali_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; =20 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 38f303f2ed04..5dc812028bd5 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -32,6 +32,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 #define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000 #define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000 +#define MSM_DSI_6G_VER_MINOR_V2_10_0 0x200a0000 =20 #define MSM_DSI_V2_VER_MINOR_8064 0x0 =20 --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E6132D97B4 for ; Tue, 25 Nov 2025 06:49:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053381; cv=none; b=jc0aaxb3mEv06NaihU+YpbIZSXfTzF5UT+EAuFAMggAlJNMBzwWJ/z6UCh6wcwaFpdoxXB4sZRuq5z8/DPjU5ZVnjHVuOBnWnlkQnPU2+H5UeM3N7pKC5PLDRzmkBYFlCcKF1kxR2uIzKSIl7dwbyyBiYQe9b3mNPYZxSlGOuaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053381; c=relaxed/simple; bh=CWfkoJLjgIy2gUgRXCOUxurYebB6LVsEC7XgknJptQU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jWjpzBtINRh41piilVhPV1Ixg0SbFMnSqiQQ7vxTWDAeGJ0NWgmXPmcM/ZwOtbpz1QoidgIIQEauN3TwAUHxYw8eJ16bxbUTvj0hCiiVwN9ZE9wdRugcZtkK6oN1Z97GhVb8kTFE181fYJ/gfooQWTbrzMfUTdSlzXhHF/YdC9s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=BaDg3Zts; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bfNzaHHE; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="BaDg3Zts"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bfNzaHHE" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2giLL1820780 for ; Tue, 25 Nov 2025 06:49:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ZtV4X5cR6Ur U16OtyrxKymwqQ6A4WNFYALAmfpTs2C4=; b=BaDg3ZtschB6e07Sx+8ui2qu92j 9TRotQC8bRrFgSaxJRMlwBy06ZFM0ODpA4mzF+3/aBRFjLiwjkxbY/01l+IJDdR3 ex/vOTHgvLXqVGqY1HafwDgswbSXZ1XeMku35Cf07u0lUuBExXjEzEvlNWEmwHfc wuhCACETM+G6TedGUtjyo4JrAQFf+mHP+02PKbap/iGELYorDD0jPxchBKMx2MQI Vt0M3wS9o1l3gKYIQ/9R4jjlCldWfDadUQ2F+dFnpaFjHzqxLeZxIiG01cKR/zTa SQoSh5VBddicuvxyaU0K3wtXlXAayE7sjWrQ+DqdcIgJyj62sIhHaPk0dtA== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amp6h32tb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:39 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-4ed79dd4a47so128719901cf.3 for ; Mon, 24 Nov 2025 22:49:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053378; x=1764658178; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZtV4X5cR6UrU16OtyrxKymwqQ6A4WNFYALAmfpTs2C4=; b=bfNzaHHEJ076A4ayFXqsP/D20/Rz3wgoXgvHBlrTeVQ0wx1Hx3EXp8AaWeA0GAW6Z4 SXPQzw5zyV8JutlAS8RXA+IwoPC+iR9A3eBTbIta9Xi+hLRuYJaXN4GKeJSvqctBTkmm iIEO5TRc0eHIkmHnSNgWNbN2sUhOG8gJpmHalYqKgoXXDsvVXqB94AbXTxGDDv+Wy20E YfMg86ATFx/Iog1RiOMK5kg8P6Dbxinxb23INhvl4d+XZ012mWR2myeQetep3C2jN1K0 rbUJWCoR6NkatyMzh5G6TSy+OeVdgwULgYfMDkDjxP3RRaRCQBwZPiIHTpBvwcY/qNvN W0MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053378; x=1764658178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZtV4X5cR6UrU16OtyrxKymwqQ6A4WNFYALAmfpTs2C4=; b=NtbOs0QU3APKzsz9z/i9MEeJiXsMx2JFX58FW+0HjTjjvW9pcMvME0aDf7MfHbTuhP YxwBablic8pD7ZYTEZ9rx774J6GHp0+u5Q4TsPXF/MPajvt0DCrtn5ZYJcNURtq0h+XM c/1ZdUv73hasgonPSiwfHkMypvyjOJzpV5Y3l9MrqE3KSqp0SVn25S0lBEfdMNEY5wcM luKOmeYNS3r6SGs1RJxtDX9373gIaEwycSqG3RmzaxYSMQI2mNJF1u7VD2HCZ2NS4vtT xzOk+/mxe3qxKG5dn+meAY0qIgLruhJ7kVcATGkOyQySzCjbscej3bd6ePhKMlBdSHtM 1AKA== X-Forwarded-Encrypted: i=1; AJvYcCWzbaKPqWohdpIkUV7NCCX2XqE0RwvXjc2J3G/C0rSs48ST+RkzJ+n+LHfjD1qYD/pBEuYXSS5L7k6uR9g=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0Bn+W29TkqMHaBP7j59vIvQkW1FswOzZLXaTrkRhab1jGL2Lc y2yo5n82uavfjbfoXRFqtj6g9PRg02AX34SrcrXj+ZdegO4FbxO4hkxORgrK+62vavVwyqHkuos soANU/DRUgNLbyvMD9eKlfrfxT+73971CAf5IZLiLSGy2VSS0pgAN9Ak8Zhk9mrc+4/0= X-Gm-Gg: ASbGncvk5K+Q9px3bfgxxaKR9UFMbdaoyhimRkoX3AgFuPzlpiABT6Syr3ogjnusPSx Dye0hjLu8mdC3gc81hfw7bntEHjAmVndXg+gCjkbYS7Ww/T6TjeQ914e5K7azUXQsve232JV4UI d3VDn0yNINcqVUCcVZ+6hbNBmUrFcys+18mOrpqbn8Ot3zFMcUdYByZzE9q/gXs8UazwOk1umht xClrkWNBLUO6/t8eoHmDa1z3lWSSgTkDyQ/fnQnn68K/RQXdyWK1rJ3GV/Z53edHfpS83cyep8Q jlmAOCnYv+VUlZgF/oluR5IDqK3cMw2nYG4JXJFHTgwAkhgbBxZcCWbkX4kZG+SZ1AgDUVyANvJ LXOmSND5/8sg4t71brnLOQoZ1NnPr+PG3LMhc1s87i+lKPwVeLPwsQzEio0nGZgetyQLpKos= X-Received: by 2002:a05:622a:282:b0:4b6:299d:dfe4 with SMTP id d75a77b69052e-4ee588643b0mr179856141cf.32.1764053378327; Mon, 24 Nov 2025 22:49:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IHm/Df/TMVkbw0+C52gzCmwzm6S2/Yi7LKlRQTQ1LKoSX7qQJ5OsrNdtob4J3N0FtyBo01Ycg== X-Received: by 2002:a05:622a:282:b0:4b6:299d:dfe4 with SMTP id d75a77b69052e-4ee588643b0mr179855831cf.32.1764053377853; Mon, 24 Nov 2025 22:49:37 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:37 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 08/10] Add interrupt registers for DPU 13.0.0 Date: Tue, 25 Nov 2025 14:47:56 +0800 Message-Id: <20251125064758.7207-9-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX8JFQLDZmbgwk lQKf7N5vlsvqGn35nrGmA4yK+6r6uSBPjgOdGlrgAEWxuBW0EmsagyT3fx2uJPUfTKUDuYppOxw S4/7+b1YjbH8RKrtKDwoheRevnlz0LOcmN+RdulWlRfgGix8Qxur34unnQ9Ca2ok58KPxVqsgjx WTrR0moPbnYwDUWwjM82MLcCVTD8HhMkzrrt2wBLmC1xMl0ZSdhh/Pn0u3GeC6J9c78H8+PDaXW MxO6DCc4Nn0MrmVWcRWo7iANkGLKj9wiGQkAYRgYuDj5OQ+ZY0o+9TZdv3dO8fUh0a4iX/GZe3T P0miEWi9nMR2oADPlDNMNk8Q1hT3cUKL9NzBvIH4XJpMDi1nbSyQUOXcKYqAhDi87uZDl4e6Zwe 55CbGnahDI3f24RpUb8Gaq179QQ+Vg== X-Proofpoint-GUID: _os3HBO7IG_lsHueYZfw0KH2wIm6SXfp X-Proofpoint-ORIG-GUID: _os3HBO7IG_lsHueYZfw0KH2wIm6SXfp X-Authority-Analysis: v=2.4 cv=GoFPO01C c=1 sm=1 tr=0 ts=69255183 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RfJNy9JZAWTFlj1jTG0A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces changes to the interrupt register layout. Update the driver to support these modifications for proper interrupt handling. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 49bd77a755aa..5b7cd5241f45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -40,6 +40,15 @@ #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x004) #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x008) =20 +#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0= x1c0) +#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) = + 0x1c4) +#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) += 0x1c8) +#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(= intf) + 0x000) +#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x004) +#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x008) + /** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg @@ -199,6 +208,82 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = =3D { }, }; =20 +/* + * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >=3D 13.0 + */ +static const struct dpu_intr_reg dpu_intr_set_13xx[] =3D { + [MDP_SSPP_TOP0_INTR] =3D { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] =3D { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] =3D { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(0), + MDP_INTF_REV_13xx_INTR_EN(0), + MDP_INTF_REV_13xx_INTR_STATUS(0) + }, + [MDP_INTF1_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_EN(1), + MDP_INTF_REV_13xx_INTR_STATUS(1) + }, + [MDP_INTF1_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_TEAR_EN(1), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1) + }, + [MDP_INTF2_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_EN(2), + MDP_INTF_REV_13xx_INTR_STATUS(2) + }, + [MDP_INTF2_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_TEAR_EN(2), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2) + }, + [MDP_INTF3_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(3), + MDP_INTF_REV_13xx_INTR_EN(3), + MDP_INTF_REV_13xx_INTR_STATUS(3) + }, + [MDP_INTF4_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(4), + MDP_INTF_REV_13xx_INTR_EN(4), + MDP_INTF_REV_13xx_INTR_STATUS(4) + }, + [MDP_INTF5_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(5), + MDP_INTF_REV_13xx_INTR_EN(5), + MDP_INTF_REV_13xx_INTR_STATUS(5) + }, + [MDP_INTF6_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(6), + MDP_INTF_REV_13xx_INTR_EN(6), + MDP_INTF_REV_13xx_INTR_STATUS(6) + }, + [MDP_INTF7_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(7), + MDP_INTF_REV_13xx_INTR_EN(7), + MDP_INTF_REV_13xx_INTR_STATUS(7) + }, + [MDP_INTF8_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(8), + MDP_INTF_REV_13xx_INTR_EN(8), + MDP_INTF_REV_13xx_INTR_STATUS(8) + }, +}; + #define DPU_IRQ_MASK(irq_idx) (BIT(DPU_IRQ_BIT(irq_idx))) =20 static inline bool dpu_core_irq_is_valid(unsigned int irq_idx) @@ -507,7 +592,9 @@ struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device = *dev, if (!intr) return ERR_PTR(-ENOMEM); =20 - if (m->mdss_ver->core_major_ver >=3D 7) + if (m->mdss_ver->core_major_ver >=3D 13) + intr->intr_set =3D dpu_intr_set_13xx; + else if (m->mdss_ver->core_major_ver >=3D 7) intr->intr_set =3D dpu_intr_set_7xxx; else intr->intr_set =3D dpu_intr_set_legacy; --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34D12D7D42 for ; Tue, 25 Nov 2025 06:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053392; cv=none; b=HDsaM7N2npUG4DBqtEHGsUDThxjZY/a9v8jiMuz+9Ptx9+wuP1Q+11UkcSDwHwlegZcLDVjx+xRFhD86tOS4Kc3hf8BLxaHw+dOrhD0j2vQSPoJN7Kn/n8AesnQFar5zMUFSSD67kA9sKHEIuOmgapd6/XtcbSmLkw8/8eIuS20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053392; c=relaxed/simple; bh=SxXrCI8iozRb9p/ESSDGcsMW4ysG4FwGNXhKBXRjUxA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iMlsocLHEhaqOLzAJmSlMCpldf42WypejkoTU8ysZps5DvNPCRm1zPGbhmf5yZgVv4OMD4cjUMb1EAOJaQRJliCzmbxqG13mERDZD/B1OJIywG+GPJUsH9VsQFEzgcRBWIoBGns6hLoiIKsrljIZ0319xekraT4O9iIAQi9oGZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LoXXuFnv; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Sk1jUCa5; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LoXXuFnv"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Sk1jUCa5" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gfGW1820689 for ; Tue, 25 Nov 2025 06:49:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=Yj/9brCSBAS IZxCqS1ZYhyDBxQSW7D8ZzqqzmpVofLg=; b=LoXXuFnv9/uzZ4PdYmPmyjROvxg FGbl88HY5wUbuY4x4L+v+qZYnrJIXuxhxpej70fNKsEc8TnR1OY9Zv8wDrTGw4Rl LKn6SWk/u4cI1TlToS0Bal78HctCKwAKhcwBRxCX+FLNCloUiyoT3RYbpcrNhysw DmKChCtiX+d5vTCnG6AYVEMBahElgOeOGdCg0w+fUBNo8BENm1jthpe20VcOq5eM 4C9EBZa5lSIzsguf5ymVGEGfSGA9cQbQ1UZpR8fnVGh2FK+4PUeDspt2r5Rmm2RJ HbgtlU1EosAqZRZr0bC6gaR8MVHKpJ5GEVj/Okf08IdywvlxkrfG+tS+8tg== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amp6h32u1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:49 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-4ed7591799eso127817571cf.0 for ; Mon, 24 Nov 2025 22:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053388; x=1764658188; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yj/9brCSBASIZxCqS1ZYhyDBxQSW7D8ZzqqzmpVofLg=; b=Sk1jUCa5CbNnWLpYPQieNj5qSHVm/n/0KLHIj9nR4X/byhMMM0IfqZGM6JAdjsRzQv 3tY3nGeYnq80kaacLI242FAL+QImwQKmQPFhOBmLVe//LOfBM3kz83k3m0fMZAv0J1sO NEzFSQsY47srrH4tpd2Sq1Cp6lr/KMkQ5IgjhoCu2SWP+T9B+2aIsJQi1GLe2wnCCkQU crooJdwyCufqVM+e8HU+4LkaFRIUGKg8ri99tsrCYLLF5ecTTTvL70o3Mem3U4CH61xA 9MDrzIoudAxn4ddA4Snt0tg6zxWdJ/olnL7RfKJhCqRIQmsijAEQ0d7YyZbvYPyxi3/u bWqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053388; x=1764658188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Yj/9brCSBASIZxCqS1ZYhyDBxQSW7D8ZzqqzmpVofLg=; b=E+1CH5dUSa8mStaPdma3o/v5bX6lfNxo5tH0JtldRqqcdNTvjLlYN+4wKCwPThBUqU OedBstd+ZkK40Q6E4k6iYWWVoBeKgwzqbskJDTF5a5neRDZtMPtA9kvbmGazNoyNAEFA T+gbqSpxHrxwX2bQkOwWj2ZCg5r/JoS5xW6AaQ3NWTDwb4sMh2HXREvqEHp/j8PhxKrU UznlA94SlcEK4llY597pTh+s15PXUcEpMgqPkl8YLYAOFczt5kCCK+VTr1nkSaaGm3bd nrWVABWM75zEmIAifMuaAGp+UjwG+jDNMTOKkO2QuqBWn9L0CyreQHLYlVnUw/Srp1qj zQlQ== X-Forwarded-Encrypted: i=1; AJvYcCWz7ENTfNo8h/k2MLiJaLEClO1p8iLP0YHjbmRPVb44Cr01HhDgRAaHok2SxXK8YiHu5mqHcUYy0chghKU=@vger.kernel.org X-Gm-Message-State: AOJu0YwwMZxi3GroG+ep+IdDRZpzb1w//dZHgrw29lQMlty1Cdks4C8p UGy6KNr75zqgEK+FJDYShgdx2wHo/3wkbW13Icgh8cCO5fpNIEaRcHDXEMK0DDJGoJQ9qIxw8DV XxVB5Mg7So9SNmfw34wpmvKEPQCoVh9X0JVTMVNI7ZFLOlVb68C+DYOeyQ5K2cP6ZLVc= X-Gm-Gg: ASbGncuRE5udJF5nd6B8rtwMT5rlYT9FTUmp4GWJ+g9rPHcU8dvRZrVsfCD6/nHCl1E AA6mUhxs6OxyJtmwBh1ogKVlkXRRjOlZG/18qcjSxc/hnkPD/DoEzdto+rReTWJ1ajzEU++l2ge C4qR3oW3O0qkYgx/gyCG8PjlW0RbgKoEgNFpsvAH2Doie1qEEDwMa9zjPYu5ZssJhofQBfPRyXw b42o97gMI2+lBPrBkZrSPtJC4dV5GdiHxKPnPvUWLyo60hTHhb42DkY3JhqsUKtJ/IRlrmyKEzD 5YzvMsP6YV6OMa9OlYeI2TuEWxh6QUXXhIp3K8PStdToa1ZQhSWYxj2UG5Kauo/5X17WwPC2inj +hx/lzrvHxMsJFwWNcZ+VhtFULqQexj2wrSzdRhKp3keTp0B50hsIwuF0mVGG5i8xPy+BZMk= X-Received: by 2002:ac8:5705:0:b0:4ed:a8f8:305e with SMTP id d75a77b69052e-4ee588601dcmr207935581cf.34.1764053387757; Mon, 24 Nov 2025 22:49:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkZ2BnIQfcxeVMaqU1P9PZbdy/RFja9oHg0qAN80DOdku8dEP9ZhVVMGp5H6qBzPixL2iTaQ== X-Received: by 2002:ac8:5705:0:b0:4ed:a8f8:305e with SMTP id d75a77b69052e-4ee588601dcmr207935211cf.34.1764053387181; Mon, 24 Nov 2025 22:49:47 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:46 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 09/10] drm/msm/dpu: Add Kaanapali SSPP sub-block support Date: Tue, 25 Nov 2025 14:47:57 +0800 Message-Id: <20251125064758.7207-10-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX3Ky75/s6rDsH 75LnFFavEbFlmocQrwMaVckkhG4AoNKwLy9MhfuHG3yJ/z3ddGD9nuj7FWMBGMagWxInpIJNTRO ps8cSeMWv70RkD0Amr/R6aXg+6r9UwmkQ+zRfd18cbkbOsI632sEzZpqFax1KSw4gBLn1jjOkzM +vegSSEd4ko4suv7k9f+2zjUrhVUVPLLY2QGxRLEXcgn5l91RHH3/ZYZn3e7MxUlzklN87Uj5r6 hOR6+y33l1DZ7gg4cbZO9PIQkEVQC4l+sNidXgc6/Yuny2Q5PYtJvJ+rbVdwlWxDXOVMZOJCfzo ybwRCmT7O+JA5rnVdbpfOCvP9mueMYTPab+YUHAzZKGhhzexAE3yXFvj9RGJgELSx/qmSGIFkXG rKz+ZBh5rdk27qjE3OW4gN95IjoQpw== X-Proofpoint-GUID: iIjQd1gUaAkiBqAw5QqkEuShiheXPYjP X-Proofpoint-ORIG-GUID: iIjQd1gUaAkiBqAw5QqkEuShiheXPYjP X-Authority-Analysis: v=2.4 cv=GoFPO01C c=1 sm=1 tr=0 ts=6925518d cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=CSmiJbPyAX6pfzxNJIkA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Kaanapali platform SSPP sub-blocks, which introduce structural changes including register additions, removals, and relocations. Add the new common and rectangle blocks, and update register definitions and handling to ensure compatibility with DPU v13.0. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/Makefile | 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 27 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 276 +++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 264 +++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_ssppv13.c | 224 ++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 23 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 + 7 files changed, 645 insertions(+), 174 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ssppv13.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 8aa7d07303fb..664e71dfa880 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -86,6 +86,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ disp/dpu1/dpu_hw_lm.o \ disp/dpu1/dpu_hw_pingpong.o \ disp/dpu1/dpu_hw_sspp.o \ + disp/dpu1/dpu_hw_ssppv13.o \ disp/dpu1/dpu_hw_dspp.o \ disp/dpu1/dpu_hw_merge3d.o \ disp/dpu1/dpu_hw_top.o \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 336757103b5a..c996b08076a9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -208,6 +208,30 @@ struct dpu_dsc_blk { u32 len; }; =20 +/** + * struct dpu_sspp_rec_blk - SSPP REC sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_rec_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + +/** + * struct dpu_sspp_cmn_blk - SSPP common sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_cmn_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + /** * enum dpu_qos_lut_usage - define QoS LUT use cases */ @@ -294,7 +318,8 @@ struct dpu_sspp_sub_blks { u32 qseed_ver; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; - + struct dpu_sspp_rec_blk sspp_rec0_blk; + struct dpu_sspp_rec_blk sspp_rec1_blk; const u32 *format_list; u32 num_formats; const struct dpu_rotation_cfg *rotation_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 6f1fc790ad6d..a2c5d1433f13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -15,141 +15,24 @@ =20 #include =20 -#define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 - -/* SSPP registers */ -#define SSPP_SRC_SIZE 0x00 -#define SSPP_SRC_XY 0x08 -#define SSPP_OUT_SIZE 0x0c -#define SSPP_OUT_XY 0x10 -#define SSPP_SRC0_ADDR 0x14 -#define SSPP_SRC1_ADDR 0x18 -#define SSPP_SRC2_ADDR 0x1C -#define SSPP_SRC3_ADDR 0x20 -#define SSPP_SRC_YSTRIDE0 0x24 -#define SSPP_SRC_YSTRIDE1 0x28 -#define SSPP_SRC_FORMAT 0x30 -#define SSPP_SRC_UNPACK_PATTERN 0x34 -#define SSPP_SRC_OP_MODE 0x38 -#define SSPP_SRC_CONSTANT_COLOR 0x3c -#define SSPP_EXCL_REC_CTL 0x40 -#define SSPP_UBWC_STATIC_CTRL 0x44 -#define SSPP_FETCH_CONFIG 0x48 -#define SSPP_DANGER_LUT 0x60 -#define SSPP_SAFE_LUT 0x64 -#define SSPP_CREQ_LUT 0x68 -#define SSPP_QOS_CTRL 0x6C -#define SSPP_SRC_ADDR_SW_STATUS 0x70 -#define SSPP_CREQ_LUT_0 0x74 -#define SSPP_CREQ_LUT_1 0x78 -#define SSPP_DECIMATION_CONFIG 0xB4 -#define SSPP_SW_PIX_EXT_C0_LR 0x100 -#define SSPP_SW_PIX_EXT_C0_TB 0x104 -#define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 -#define SSPP_SW_PIX_EXT_C1C2_LR 0x110 -#define SSPP_SW_PIX_EXT_C1C2_TB 0x114 -#define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 -#define SSPP_SW_PIX_EXT_C3_LR 0x120 -#define SSPP_SW_PIX_EXT_C3_TB 0x124 -#define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 -#define SSPP_TRAFFIC_SHAPER 0x130 -#define SSPP_CDP_CNTL 0x134 -#define SSPP_UBWC_ERROR_STATUS 0x138 -#define SSPP_CDP_CNTL_REC1 0x13c -#define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 -#define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 -#define SSPP_TRAFFIC_SHAPER_REC1 0x158 -#define SSPP_OUT_SIZE_REC1 0x160 -#define SSPP_OUT_XY_REC1 0x164 -#define SSPP_SRC_XY_REC1 0x168 -#define SSPP_SRC_SIZE_REC1 0x16C -#define SSPP_MULTIRECT_OPMODE 0x170 -#define SSPP_SRC_FORMAT_REC1 0x174 -#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 -#define SSPP_SRC_OP_MODE_REC1 0x17C -#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 -#define SSPP_EXCL_REC_SIZE_REC1 0x184 -#define SSPP_EXCL_REC_XY_REC1 0x188 -#define SSPP_EXCL_REC_SIZE 0x1B4 -#define SSPP_EXCL_REC_XY 0x1B8 -#define SSPP_CLK_CTRL 0x330 - -/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ -#define MDSS_MDP_OP_DEINTERLACE BIT(22) -#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) -#define MDSS_MDP_OP_IGC_ROM_1 BIT(18) -#define MDSS_MDP_OP_IGC_ROM_0 BIT(17) -#define MDSS_MDP_OP_IGC_EN BIT(16) -#define MDSS_MDP_OP_FLIP_UD BIT(14) -#define MDSS_MDP_OP_FLIP_LR BIT(13) -#define MDSS_MDP_OP_BWC_EN BIT(0) -#define MDSS_MDP_OP_PE_OVERRIDE BIT(31) -#define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) -#define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) -#define MDSS_MDP_OP_BWC_Q_MED (2 << 1) - -/* SSPP_QOS_CTRL */ -#define SSPP_QOS_CTRL_VBLANK_EN BIT(16) -#define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) -#define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 -#define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 -#define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 -#define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 - -/* DPU_SSPP_SCALER_QSEED2 */ -#define SSPP_VIG_OP_MODE 0x0 -#define SCALE_CONFIG 0x04 -#define COMP0_3_PHASE_STEP_X 0x10 -#define COMP0_3_PHASE_STEP_Y 0x14 -#define COMP1_2_PHASE_STEP_X 0x18 -#define COMP1_2_PHASE_STEP_Y 0x1c -#define COMP0_3_INIT_PHASE_X 0x20 -#define COMP0_3_INIT_PHASE_Y 0x24 -#define COMP1_2_INIT_PHASE_X 0x28 -#define COMP1_2_INIT_PHASE_Y 0x2C -#define VIG_0_QSEED2_SHARP 0x30 - -/* SSPP_TRAFFIC_SHAPER and _REC1 */ -#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF - -/* - * Definitions for ViG op modes - */ -#define VIG_OP_CSC_DST_DATAFMT BIT(19) -#define VIG_OP_CSC_SRC_DATAFMT BIT(18) -#define VIG_OP_CSC_EN BIT(17) -#define VIG_OP_MEM_PROT_CONT BIT(15) -#define VIG_OP_MEM_PROT_VAL BIT(14) -#define VIG_OP_MEM_PROT_SAT BIT(13) -#define VIG_OP_MEM_PROT_HUE BIT(12) -#define VIG_OP_HIST BIT(8) -#define VIG_OP_SKY_COL BIT(7) -#define VIG_OP_FOIL BIT(6) -#define VIG_OP_SKIN_COL BIT(5) -#define VIG_OP_PA_EN BIT(4) -#define VIG_OP_PA_SAT_ZERO_EXP BIT(2) -#define VIG_OP_MEM_PROT_BLEND BIT(1) - -/* - * Definitions for CSC 10 op modes - */ -#define SSPP_VIG_CSC_10_OP_MODE 0x0 -#define VIG_CSC_10_SRC_DATAFMT BIT(1) -#define VIG_CSC_10_EN BIT(0) -#define CSC_10BIT_OFFSET 4 - -/* traffic shaper clock in Hz */ -#define TS_CLK 19200000 - - static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - u32 mode_mask; + u32 op_mode_off; =20 if (!ctx) return; =20 + op_mode_off =3D SSPP_MULTIRECT_OPMODE; + + _dpu_hw_setup_multirect(pipe, ctx, op_mode_off); +} + +void _dpu_hw_setup_multirect(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, u32 op_mode_off) +{ + u32 mode_mask; + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a @@ -158,7 +41,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pi= pe *pipe) */ mode_mask =3D 0; } else { - mode_mask =3D DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); + mode_mask =3D DPU_REG_READ(&ctx->hw, op_mode_off); mode_mask |=3D pipe->multirect_index; if (pipe->multirect_mode =3D=3D DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |=3D BIT(2); @@ -166,11 +49,11 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_= pipe *pipe) mode_mask &=3D ~BIT(2); } =20 - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); + DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask); } =20 -static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, - u32 mask, u8 en) +void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; u32 opmode; @@ -189,8 +72,8 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } =20 -static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, - u32 mask, u8 en) +void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; u32 opmode; @@ -211,11 +94,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, const struct msm_format *fmt, u32 flags) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 chroma_samp, unpack, src_format; - u32 opmode =3D 0; - u32 fast_clear =3D 0; u32 op_mode_off, unpack_pat_off, format_off; + u32 ubwc_ctrl_off, ubwc_err_off; =20 if (!ctx || !fmt) return; @@ -230,16 +110,42 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, unpack_pat_off =3D SSPP_SRC_UNPACK_PATTERN_REC1; format_off =3D SSPP_SRC_FORMAT_REC1; } + ubwc_ctrl_off =3D SSPP_UBWC_STATIC_CTRL; + ubwc_err_off =3D SSPP_UBWC_ERROR_STATUS; + + _dpu_hw_setup_format(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off); +} + +void _dpu_hw_setup_format(struct dpu_sw_pipe *pipe, const struct msm_forma= t *fmt, + u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, + u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off, u32 ubwc_err_o= ff) +{ + struct dpu_hw_blk_reg_map *c; + u32 chroma_samp, unpack, src_format; + u32 opmode; + u32 fast_clear; + u8 core_major_ver; =20 c =3D &ctx->hw; + core_major_ver =3D ctx->mdss_ver->core_major_ver; + opmode =3D DPU_REG_READ(c, op_mode_off); - opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | + if (core_major_ver >=3D 13) + opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | + MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE + | MDSS_MDP_OP_ROT_90); + else + opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); =20 if (flags & DPU_SSPP_FLIP_LR) opmode |=3D MDSS_MDP_OP_FLIP_LR; if (flags & DPU_SSPP_FLIP_UD) opmode |=3D MDSS_MDP_OP_FLIP_UD; + if (core_major_ver >=3D 13) + if (flags & DPU_SSPP_ROT_90) + opmode |=3D MDSS_MDP_OP_ROT_90; =20 chroma_samp =3D fmt->chroma_sample; if (flags & DPU_SSPP_SOURCE_ROTATED_90) { @@ -273,31 +179,34 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, if (MSM_FORMAT_IS_UBWC(fmt)) opmode |=3D MDSS_MDP_OP_BWC_EN; src_format |=3D (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, - DPU_FETCH_CONFIG_RESET_VALUE | - ctx->ubwc->highest_bank_bit << 18); + + if (core_major_ver < 13) + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, + DPU_FETCH_CONFIG_RESET_VALUE | + ctx->ubwc->highest_bank_bit << 18); + switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | - BIT(8) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | + BIT(8) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_2_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->ubwc->ubwc_swizzle) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + fast_clear | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_3_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - BIT(30) | (ctx->ubwc->ubwc_swizzle) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + BIT(30) | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_4_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } } @@ -323,9 +232,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, DPU_REG_WRITE(c, format_off, src_format); DPU_REG_WRITE(c, unpack_pat_off, unpack); DPU_REG_WRITE(c, op_mode_off, opmode); - /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); + DPU_REG_WRITE(c, ubwc_err_off, BIT(31)); } =20 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, @@ -385,9 +293,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_s= spp *ctx, tot_req_pixels[3]); } =20 -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, - struct dpu_hw_scaler3_cfg *scaler3_cfg, - const struct msm_format *format) +void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format) { if (!ctx || !scaler3_cfg) return; @@ -405,15 +313,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pip= e *pipe, struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; =20 if (!ctx || !cfg) return; =20 - c =3D &ctx->hw; - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) { src_size_off =3D SSPP_SRC_SIZE; @@ -427,6 +331,19 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe= *pipe, out_xy_off =3D SSPP_OUT_XY_REC1; } =20 + _dpu_hw_setup_rects(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); +} + +void _dpu_hw_setup_rects(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg, struct dpu_hw_sspp *ctx, + u32 src_size_off, u32 src_xy_off, + u32 out_size_off, u32 out_xy_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 src_size, src_xy, dst_size, dst_xy; + + c =3D &ctx->hw; =20 /* src and dest rect programming */ src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; @@ -497,8 +414,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_= sw_pipe *pipe, DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); } =20 -static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, - const struct dpu_csc_cfg *data) +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data) { u32 offset; bool csc10 =3D false; @@ -519,21 +436,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp = *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 colo= r) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_fmt_layout cfg; + u32 const_clr_off; =20 if (!ctx) return; =20 + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || + pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR; + else + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR_REC1; + + _dpu_hw_setup_solidfill(pipe, color, ctx, const_clr_off); +} + +void _dpu_hw_setup_solidfill(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, + u32 const_clr_off) +{ + struct dpu_hw_fmt_layout cfg; + /* cleanup source addresses */ memset(&cfg, 0, sizeof(cfg)); ctx->ops.setup_sourceaddress(pipe, &cfg); =20 - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || - pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); - else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, - color); + DPU_REG_WRITE(&ctx->hw, const_clr_off, color); } =20 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, @@ -706,7 +633,10 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, =20 hw_pipe->mdss_ver =3D mdss_rev; =20 - _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); + if (mdss_rev->core_major_ver >=3D 13) + _setup_layer_ops_v13(hw_pipe, hw_pipe->cap->features, mdss_rev); + else + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); =20 return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index bdac5c04bf79..8ae4091e6e63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -14,6 +14,167 @@ struct dpu_hw_sspp; =20 #define DPU_SSPP_MAX_PITCH_SIZE 0xffff =20 +/* <=3D v12 DPU */ +/* SSPP registers */ +#define SSPP_SRC_SIZE 0x00 +#define SSPP_SRC_XY 0x08 +#define SSPP_OUT_SIZE 0x0c +#define SSPP_OUT_XY 0x10 +#define SSPP_SRC0_ADDR 0x14 +#define SSPP_SRC1_ADDR 0x18 +#define SSPP_SRC2_ADDR 0x1C +#define SSPP_SRC3_ADDR 0x20 +#define SSPP_SRC_YSTRIDE0 0x24 +#define SSPP_SRC_YSTRIDE1 0x28 +#define SSPP_SRC_FORMAT 0x30 +#define SSPP_SRC_UNPACK_PATTERN 0x34 +#define SSPP_SRC_OP_MODE 0x38 +#define SSPP_SRC_CONSTANT_COLOR 0x3c +#define SSPP_EXCL_REC_CTL 0x40 +#define SSPP_UBWC_STATIC_CTRL 0x44 +#define SSPP_FETCH_CONFIG 0x48 +#define SSPP_DANGER_LUT 0x60 +#define SSPP_SAFE_LUT 0x64 +#define SSPP_CREQ_LUT 0x68 +#define SSPP_QOS_CTRL 0x6C +#define SSPP_SRC_ADDR_SW_STATUS 0x70 +#define SSPP_CREQ_LUT_0 0x74 +#define SSPP_CREQ_LUT_1 0x78 +#define SSPP_DECIMATION_CONFIG 0xB4 +#define SSPP_SW_PIX_EXT_C0_LR 0x100 +#define SSPP_SW_PIX_EXT_C0_TB 0x104 +#define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 +#define SSPP_SW_PIX_EXT_C1C2_LR 0x110 +#define SSPP_SW_PIX_EXT_C1C2_TB 0x114 +#define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 +#define SSPP_SW_PIX_EXT_C3_LR 0x120 +#define SSPP_SW_PIX_EXT_C3_TB 0x124 +#define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 +#define SSPP_TRAFFIC_SHAPER 0x130 +#define SSPP_CDP_CNTL 0x134 +#define SSPP_UBWC_ERROR_STATUS 0x138 +#define SSPP_CDP_CNTL_REC1 0x13c +#define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 +#define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 +#define SSPP_TRAFFIC_SHAPER_REC1 0x158 +#define SSPP_OUT_SIZE_REC1 0x160 +#define SSPP_OUT_XY_REC1 0x164 +#define SSPP_SRC_XY_REC1 0x168 +#define SSPP_SRC_SIZE_REC1 0x16C +#define SSPP_MULTIRECT_OPMODE 0x170 +#define SSPP_SRC_FORMAT_REC1 0x174 +#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 +#define SSPP_SRC_OP_MODE_REC1 0x17C +#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 +#define SSPP_EXCL_REC_SIZE_REC1 0x184 +#define SSPP_EXCL_REC_XY_REC1 0x188 +#define SSPP_EXCL_REC_SIZE 0x1B4 +#define SSPP_EXCL_REC_XY 0x1B8 +#define SSPP_CLK_CTRL 0x330 + +/* >=3D v13 DPU */ +/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */ +/* Name Offset */ +#define SSPP_CMN_CLK_CTRL 0x0 +#define SSPP_CMN_CLK_STATUS 0x4 +#define SSPP_CMN_MULTI_REC_OP_MODE 0x10 +#define SSPP_CMN_ADDR_CONFIG 0x14 +#define SSPP_CMN_CAC_CTRL 0x20 +#define SSPP_CMN_SYS_CACHE_MODE 0x24 +#define SSPP_CMN_QOS_CTRL 0x28 +#define SSPP_CMN_DANGER_LUT 0x2c +#define SSPP_CMN_SAFE_LUT 0x30 + +#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c +#define SSPP_CMN_FILL_LEVELS 0x40 +#define SSPP_CMN_STATUS 0x44 +#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48 +#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c +#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50 +#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c +#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60 +#define SSPP_CMN_UNPACK_LINE_COUNT 0x64 +#define SSPP_CMN_TPG_CONTROL 0x68 +#define SSPP_CMN_TPG_CONFIG 0x6c +#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70 +#define SSPP_CMN_TPG_RECTANGLE 0x74 +#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78 +#define SSPP_CMN_TPG_RGB_MAPPING 0x7c +#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80 + +/*RECRegisterset*/ +/*Name Offset*/ +#define SSPP_REC_SRC_FORMAT 0x0 +#define SSPP_REC_SRC_UNPACK_PATTERN 0x4 +#define SSPP_REC_SRC_OP_MODE 0x8 +#define SSPP_REC_SRC_CONSTANT_COLOR 0xc +#define SSPP_REC_SRC_IMG_SIZE 0x10 +#define SSPP_REC_SRC_SIZE 0x14 +#define SSPP_REC_SRC_XY 0x18 +#define SSPP_REC_OUT_SIZE 0x1c +#define SSPP_REC_OUT_XY 0x20 +#define SSPP_REC_SW_PIX_EXT_LR 0x24 +#define SSPP_REC_SW_PIX_EXT_TB 0x28 +#define SSPP_REC_SRC_SIZE_ODX 0x30 +#define SSPP_REC_SRC_XY_ODX 0x34 +#define SSPP_REC_OUT_SIZE_ODX 0x38 +#define SSPP_REC_OUT_XY_ODX 0x3c +#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40 +#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44 +#define SSPP_REC_PRE_DOWN_SCALE 0x48 +#define SSPP_REC_SRC0_ADDR 0x4c +#define SSPP_REC_SRC1_ADDR 0x50 +#define SSPP_REC_SRC2_ADDR 0x54 +#define SSPP_REC_SRC3_ADDR 0x58 +#define SSPP_REC_SRC_YSTRIDE0 0x5c +#define SSPP_REC_SRC_YSTRIDE1 0x60 +#define SSPP_REC_CURRENT_SRC0_ADDR 0x64 +#define SSPP_REC_CURRENT_SRC1_ADDR 0x68 +#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c +#define SSPP_REC_CURRENT_SRC3_ADDR 0x70 +#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74 +#define SSPP_REC_CDP_CNTL 0x78 +#define SSPP_REC_TRAFFIC_SHAPER 0x7c +#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80 +#define SSPP_REC_PD_MEM_ALLOC 0x84 +#define SSPP_REC_QOS_CLAMP 0x88 +#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c +#define SSPP_REC_UBWC_STATIC_CTRL 0x90 +#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94 +#define SSPP_REC_UBWC_STATS_ROI 0x98 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4 +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0 +#define SSPP_REC_EXCL_REC_CTRL 0xb4 +#define SSPP_REC_EXCL_REC_SIZE 0xb8 +#define SSPP_REC_EXCL_REC_XY 0xbc +#define SSPP_REC_LINE_INSERTION_CTRL 0xc0 +#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4 +#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8 +#define SSPP_REC_META_ERROR_STATUS 0xcc +#define SSPP_REC_UBWC_ERROR_STATUS 0xd0 +#define SSPP_REC_FLUSH_CTRL 0xd4 +#define SSPP_REC_INTR_EN 0xd8 +#define SSPP_REC_INTR_STATUS 0xdc +#define SSPP_REC_INTR_CLEAR 0xe0 +#define SSPP_REC_HSYNC_STATUS 0xe4 +#define SSPP_REC_FP16_CONFIG 0x150 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c +#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174 +#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178 + /** * Flags */ @@ -23,6 +184,76 @@ struct dpu_hw_sspp; #define DPU_SSPP_ROT_90 BIT(3) #define DPU_SSPP_SOLID_FILL BIT(4) =20 +/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ +#define MDSS_MDP_OP_DEINTERLACE BIT(22) +#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) +#define MDSS_MDP_OP_IGC_ROM_1 BIT(18) +#define MDSS_MDP_OP_IGC_ROM_0 BIT(17) +#define MDSS_MDP_OP_IGC_EN BIT(16) +#define MDSS_MDP_OP_ROT_90 BIT(15) +#define MDSS_MDP_OP_FLIP_UD BIT(14) +#define MDSS_MDP_OP_FLIP_LR BIT(13) +#define MDSS_MDP_OP_BWC_EN BIT(0) +#define MDSS_MDP_OP_PE_OVERRIDE BIT(31) +#define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) +#define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) +#define MDSS_MDP_OP_BWC_Q_MED (2 << 1) + +/* + * Definitions for ViG op modes + */ +#define VIG_OP_CSC_DST_DATAFMT BIT(19) +#define VIG_OP_CSC_SRC_DATAFMT BIT(18) +#define VIG_OP_CSC_EN BIT(17) +#define VIG_OP_MEM_PROT_CONT BIT(15) +#define VIG_OP_MEM_PROT_VAL BIT(14) +#define VIG_OP_MEM_PROT_SAT BIT(13) +#define VIG_OP_MEM_PROT_HUE BIT(12) +#define VIG_OP_HIST BIT(8) +#define VIG_OP_SKY_COL BIT(7) +#define VIG_OP_FOIL BIT(6) +#define VIG_OP_SKIN_COL BIT(5) +#define VIG_OP_PA_EN BIT(4) +#define VIG_OP_PA_SAT_ZERO_EXP BIT(2) +#define VIG_OP_MEM_PROT_BLEND BIT(1) + +/* + * Definitions for CSC 10 op modes + */ +#define SSPP_VIG_CSC_10_OP_MODE 0x0 +#define VIG_CSC_10_SRC_DATAFMT BIT(1) +#define VIG_CSC_10_EN BIT(0) +#define CSC_10BIT_OFFSET 4 + +/* SSPP_QOS_CTRL */ +#define SSPP_QOS_CTRL_VBLANK_EN BIT(16) +#define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) +#define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 +#define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 +#define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 +#define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 + +#define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 + +/* DPU_SSPP_SCALER_QSEED2 */ +#define SSPP_VIG_OP_MODE 0x0 +#define SCALE_CONFIG 0x04 +#define COMP0_3_PHASE_STEP_X 0x10 +#define COMP0_3_PHASE_STEP_Y 0x14 +#define COMP1_2_PHASE_STEP_X 0x18 +#define COMP1_2_PHASE_STEP_Y 0x1c +#define COMP0_3_INIT_PHASE_X 0x20 +#define COMP0_3_INIT_PHASE_Y 0x24 +#define COMP1_2_INIT_PHASE_X 0x28 +#define COMP1_2_INIT_PHASE_Y 0x2C +#define VIG_0_QSEED2_SHARP 0x30 + +/* SSPP_TRAFFIC_SHAPER and _REC1 */ +#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF + +/* traffic shaper clock in Hz */ +#define TS_CLK 19200000 + /** * Component indices */ @@ -331,5 +562,38 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, struct dentry *entry); =20 +void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format); + +void _setup_layer_ops_v13(struct dpu_hw_sspp *c, + unsigned long features, + const struct dpu_mdss_version *mdss_rev); + +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data); + +void _dpu_hw_setup_multirect(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, + u32 op_mode_off); + +void _dpu_hw_setup_format(struct dpu_sw_pipe *pipe, const struct msm_forma= t *fmt, + u32 flags, struct dpu_hw_sspp *ctx, + u32 op_mode_off, u32 unpack_pat_off, u32 format_off, + u32 ubwc_ctrl_off, u32 ubwc_err_off); + +void _dpu_hw_setup_rects(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg = *cfg, + struct dpu_hw_sspp *ctx, u32 src_size_off, u32 src_xy_off, + u32 out_size_off, u32 out_xy_off); + +void _dpu_hw_setup_solidfill(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off); + #endif /*_DPU_HW_SSPP_H */ =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ssppv13.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_ssppv13.c new file mode 100644 index 000000000000..ba2d70182d58 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ssppv13.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "dpu_hw_sspp.h" + +static inline u32 _sspp_calculate_rect_off(enum dpu_sspp_multirect_index r= ect_index, + struct dpu_hw_sspp *ctx) +{ + return (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSP= P_RECT_0) ? + ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base; +} + +static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 op_mode_off; + + if (!ctx) + return; + + op_mode_off =3D SSPP_CMN_MULTI_REC_OP_MODE; + + _dpu_hw_setup_multirect(pipe, ctx, op_mode_off); +} + +static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, u32 flags) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 op_mode_off, unpack_pat_off, format_off; + u32 ubwc_ctrl_off, ubwc_err_off; + u32 offset; + + if (!ctx || !fmt) + return; + + offset =3D _sspp_calculate_rect_off(pipe->multirect_index, ctx); + + op_mode_off =3D offset + SSPP_REC_SRC_OP_MODE; + unpack_pat_off =3D offset + SSPP_REC_SRC_UNPACK_PATTERN; + format_off =3D offset + SSPP_REC_SRC_FORMAT; + ubwc_ctrl_off =3D offset + SSPP_REC_UBWC_STATIC_CTRL; + ubwc_err_off =3D offset + SSPP_REC_UBWC_ERROR_STATUS; + + _dpu_hw_setup_format(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off); +} + +static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_pixel_ext *pe_ext) +{ + struct dpu_hw_blk_reg_map *c; + u8 color; + u32 lr_pe[4], tb_pe[4]; + const u32 bytemask =3D 0xff; + u32 offset =3D ctx->cap->sblk->sspp_rec0_blk.base; + + if (!ctx || !pe_ext) + return; + + c =3D &ctx->hw; + /* program SW pixel extension override for all pipes*/ + for (color =3D 0; color < DPU_MAX_PLANES; color++) { + /* color 2 has the same set of registers as color 1 */ + if (color =3D=3D 2) + continue; + + lr_pe[color] =3D ((pe_ext->right_ftch[color] & bytemask) << 24) | + ((pe_ext->right_rpt[color] & bytemask) << 16) | + ((pe_ext->left_ftch[color] & bytemask) << 8) | + (pe_ext->left_rpt[color] & bytemask); + + tb_pe[color] =3D ((pe_ext->btm_ftch[color] & bytemask) << 24) | + ((pe_ext->btm_rpt[color] & bytemask) << 16) | + ((pe_ext->top_ftch[color] & bytemask) << 8) | + (pe_ext->top_rpt[color] & bytemask); + } + + /* color 0 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]); + + /* color 1 and color 2 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]); +} + +static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 src_size_off, src_xy_off, out_size_off, out_xy_off; + u32 offset; + + if (!ctx || !cfg) + return; + + offset =3D _sspp_calculate_rect_off(pipe->multirect_index, ctx); + + src_size_off =3D offset + SSPP_REC_SRC_SIZE; + src_xy_off =3D offset + SSPP_REC_SRC_XY; + out_size_off =3D offset + SSPP_REC_OUT_SIZE; + out_xy_off =3D offset + SSPP_REC_OUT_XY; + + _dpu_hw_setup_rects(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); +} + +static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe, + struct dpu_hw_fmt_layout *layout) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + int i; + u32 offset, ystride0, ystride1; + + if (!ctx) + return; + + offset =3D _sspp_calculate_rect_off(pipe->multirect_index, ctx); + + for (i =3D 0; i < ARRAY_SIZE(layout->plane_addr); i++) + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4, + layout->plane_addr[i]); + + ystride0 =3D (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16); + ystride1 =3D (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16); + + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0); + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1); +} + +static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 = color) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 const_clr_off; + u32 offset; + + if (!ctx) + return; + + offset =3D _sspp_calculate_rect_off(pipe->multirect_index, ctx); + const_clr_off =3D offset + SSPP_REC_SRC_CONSTANT_COLOR; + + _dpu_hw_setup_solidfill(pipe, color, ctx, const_clr_off); +} + +static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_qos_cfg *cfg) +{ + if (!ctx || !cfg) + return; + + _dpu_hw_setup_qos_lut_v13(&ctx->hw, 0, 1, cfg); +} + +static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx, + bool danger_safe_en) +{ + if (!ctx) + return; + + DPU_REG_WRITE(&ctx->hw, SSPP_CMN_QOS_CTRL, + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); +} + +static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, + bool enable) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 offset =3D 0; + + if (!ctx) + return; + + offset =3D _sspp_calculate_rect_off(pipe->multirect_index, ctx); + dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable); +} + +static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, = bool enable) +{ + static const struct dpu_clk_ctrl_reg sspp_clk_ctrl =3D { + .reg_off =3D SSPP_CMN_CLK_CTRL, + .bit_off =3D 0 + }; + + return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable); +} + +void _setup_layer_ops_v13(struct dpu_hw_sspp *c, + unsigned long features, const struct dpu_mdss_version *mdss_rev) +{ + c->ops.setup_format =3D dpu_hw_sspp_setup_format_v13; + c->ops.setup_rects =3D dpu_hw_sspp_setup_rects_v13; + c->ops.setup_sourceaddress =3D dpu_hw_sspp_setup_sourceaddress_v13; + c->ops.setup_solidfill =3D dpu_hw_sspp_setup_solidfill_v13; + c->ops.setup_pe =3D dpu_hw_sspp_setup_pe_config_v13; + + if (test_bit(DPU_SSPP_QOS, &features)) { + c->ops.setup_qos_lut =3D dpu_hw_sspp_setup_qos_lut_v13; + c->ops.setup_qos_ctrl =3D dpu_hw_sspp_setup_qos_ctrl_v13; + } + + if (test_bit(DPU_SSPP_CSC, &features) || + test_bit(DPU_SSPP_CSC_10BIT, &features)) + c->ops.setup_csc =3D dpu_hw_sspp_setup_csc; + + if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect_v13; + + if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) + c->ops.setup_scaler =3D _dpu_hw_sspp_setup_scaler3; + + if (test_bit(DPU_SSPP_CDP, &features)) + c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp_v13; + + c->ops.setup_clk_force_ctrl =3D dpu_hw_sspp_setup_clk_force_ctrl_v13; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.c index 486be346d40d..968020967bc5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask =3D DPU_DBG_MASK_NONE; #define QOS_CREQ_LUT_0 0x14 #define QOS_CREQ_LUT_1 0x18 =20 +/* CMN_QOS_LUT */ +#define SSPP_CMN_DANGER_LUT 0x2C +#define SSPP_CMN_SAFE_LUT 0x30 +#define SSPP_CMN_CREQ_LUT_0 0x34 +#define SSPP_CMN_CREQ_LUT_1 0x38 +#define SSPP_CMN_QOS_CTRL 0x28 + /* QOS_QOS_CTRL */ #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0) #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4) @@ -475,6 +482,22 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *= c, u32 offset, cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); } =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, u32 offset, + bool qos_8lvl, + const struct dpu_hw_qos_cfg *cfg) +{ + DPU_REG_WRITE(c, offset + SSPP_CMN_DANGER_LUT, cfg->danger_lut); + DPU_REG_WRITE(c, offset + SSPP_CMN_SAFE_LUT, cfg->safe_lut); + + if (qos_8lvl) { + DPU_REG_WRITE(c, offset + SSPP_CMN_CREQ_LUT_0, cfg->creq_lut); + DPU_REG_WRITE(c, offset + SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32); + } + + DPU_REG_WRITE(c, offset + SSPP_CMN_QOS_CTRL, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); +} + /* * note: Aside from encoders, input_sel should be set to 0x0 by default */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 67b08e99335d..9d442d6fc11c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -360,6 +360,10 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *= c, u32 offset, bool qos_8lvl, const struct dpu_hw_qos_cfg *cfg); =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, u32 offset, + bool qos_8lvl, + const struct dpu_hw_qos_cfg *cfg); + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u8 input_sel); =20 --=20 2.34.1 From nobody Tue Dec 2 00:26:36 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1F6C2E8E12 for ; Tue, 25 Nov 2025 06:49:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053401; cv=none; b=I75c6TPHQAOTJHo23tN3ccbqWTnj3QuwRgenhdU4M1HuYDx/OFiG1R7T7qRh2fumU+PhwuPctsBmmUdif5v3QzwlZwxvaQOCvufUvDuN7ijqaH2GQf/y+U8IBRlfnJEvla+Rz8avkv4ULcaQN0ZxqnZwfMbeaASKlPkJQexGHSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764053401; c=relaxed/simple; bh=TNDq8mkLMSVU3Da1mrHQxKNiCXtWYOQqjgOYB21tllM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oCpBiNocTYNscbkBB+W1aNv87HJqnuUBWdlwH54nxiQyabGLRE2Buv4z+2fsEPPcTJLBTUIVYeAituuk32S+x72Zl7Is2eykQP85V1DBpkOBJFoL0o1s7o6IEU/nsRipdmqd79nyMkpVRNX9n0Z7cs+8+sDQCldCc0z3gR0Z2ZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=etfBD5+5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jVdGDhi5; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="etfBD5+5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jVdGDhi5" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2gkj51688365 for ; Tue, 25 Nov 2025 06:49:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=XxK3gfAsvNp 9xX3RxeJTwwOUyerwBQHdHbIQLFQrL8Q=; b=etfBD5+5HCI9U7Be72roBIf1P4y SZfKmbtYXWEFUmvkxIaQ/a5ydYgsTD7fbBmjqBaNXL2pSLa3jJCMnJMDlcHFat7e 970EDE4kmi7dW/eLFbZ6ezaA3BNo9GfsXggeaZ6CGj1ycLplcrZ1ccfC1IzYL5Fu TrGhoG0N6y7ZvnP8ry+HIPcFzTXAnHokED9sIGgiNM6zKY5Wn/Gx4e2hagRcpGeE TJKL/G9n8XL0ziEKJqlTgF5dZfv3JTWdmPWedhu3JC6dufsySRCggQI+gWYJnjnI 5N5VJ7mV0gLDab3VAYY12XbTUDYZvdn2BzY+o6LDxPGN/BNzxtH3o4ONY+g== Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amrv6aj6k-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 06:49:58 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-8823f71756dso59853786d6.3 for ; Mon, 24 Nov 2025 22:49:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764053397; x=1764658197; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XxK3gfAsvNp9xX3RxeJTwwOUyerwBQHdHbIQLFQrL8Q=; b=jVdGDhi5rmSlplYJ/viS7/BgMdAx4o0pU72Wz6inYxw2pIIyV3H9DxbFO4j8pKLs6p Ju56B5jR8/FLnRxT8pFxBtgAMa5/KqPl6U61B8/LxQbJQhU9AASdooVKPPfFE26pTjHo LTcNbIxiUFdzDEuIGkqz4nh7FhK2l/PdReHYVheBmFUUoJ8+mHU6+NoYbOwhDKuSI0Wp dkckqTMxWELnz5r560kv5pyOelcp54DhnXnImuSSAA2ipw0H1o5Kjt1XIoQdULjPFJxu SaP0pXuMAt7Wb/s4QEKsccEBdak4AUgsrzJrCcB9sAMTxDxzhFLyjUKtyo6B/5uuhtGI jGiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764053397; x=1764658197; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XxK3gfAsvNp9xX3RxeJTwwOUyerwBQHdHbIQLFQrL8Q=; b=L5v9G7guycNGB7wCq0CFT7HqowU/lYKecZEsOHY2ZLu+fRPw07xZe5Cqz7C35QWuDg IR3htnIGI3081ZS0i0i/CjgsGQw2icjbwRk4KDhGtRiNpxwa2WkUKTaJRX1kpaPC2HC1 Fv86oy762tTN2WjoaxEy9pdXR1Cr/1nfeVcxKwaj6G9P+/lV1M9SuD9MoYl5Lwt5kUlW ESLYHTsBjtoN4C0tyL74IEXLAm6aG0UULsKku5y+RREu5rBw7Pl11mmZrkq4LsUdVZc3 cM471c/YpFLT9NQWCpMnm+NhgS46DLNETtu22DPj92X5TavnolP2sxfV8IvLilJcOc1V q4iw== X-Forwarded-Encrypted: i=1; AJvYcCWdHhxRVkGN4XtGwXGwzYky+oyiwkOR/m3Y8Y65HxE5xtxNmpsOk4+vBf5kVeoZC1TbO1dXXvGrHULyBqY=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4Px+94ylf5J6Z6w+Z7ER6tBkIt6JtyV0aBYW7aST+6IF4owXS rQk388T858NlaBVtjfRCBDqX92hQSe6rlA9hBC5OHGJH9WoVl76CR6YWbzVM5Z/oMHUGqkvuGbH cRXPluL0Ws/ecq5fkkl/9urkF/nDXhM8+f+6pC28bgqRvhl9JGuOPRiRUDA6gQpLYwuE= X-Gm-Gg: ASbGnctQwyMR3lRJzpdWXWetAohIctd6ZKzhzz0R3FSEIT8z/LglIfAuZGcnuuPTnGE yIqjzIZ1hZwcQ46I3qr0HIwh+oJoJ/ghuFnVEAZ4ZIPdRzn9kbCKr0P1s/gOLjPuOVKkUF6VsLZ 6xTdUbqSf2q73AB4Y6JxGofZLgqXcspH0ua8ULU201UxYutPNFqZC9hBRWHgLxqZnPCCAh+MQOA X195JREeKO6IbXYSa76LrFk6ftih1bGbQFMP6Rrn/kIoo+iPsONo6OFPUVtn5yNMqj1HZO+3JlU Q9cLz2/54kke7i+IRb7JFhagGPRldZO5WO+ceQaiceivRD0CeB9080MZJH+p5JxhkgxMc3+9cUm plkhN3OTZ29S9/tlMTeEIWZ2+D4c8g4BtWEt6tpoyiU1DsZp/iwJt5odmMjAXrGdLSjtIHIU= X-Received: by 2002:a05:622a:19a4:b0:4ed:e064:1638 with SMTP id d75a77b69052e-4efbda9015fmr21240741cf.40.1764053396891; Mon, 24 Nov 2025 22:49:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IGGX45VGw51UkNg2dhBcwFHvisr394hJNXjtMaVqPVKQtS9cNj7et3kANkvVHWgmGE8kyjz1g== X-Received: by 2002:a05:622a:19a4:b0:4ed:e064:1638 with SMTP id d75a77b69052e-4efbda9015fmr21240561cf.40.1764053396355; Mon, 24 Nov 2025 22:49:56 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48e3edb9sm100645971cf.22.2025.11.24.22.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 22:49:55 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org, yuanjie.yang@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Yongxing Mou Subject: [PATCH v2 10/10] drm/msm/dpu: Add support for Kaanapali DPU Date: Tue, 25 Nov 2025 14:47:58 +0800 Message-Id: <20251125064758.7207-11-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> References: <20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA1NCBTYWx0ZWRfX7rr/BeaMy16b 4ohO2CwdeamPIojD+44ynEVztJg8lugbEdUpwjvs/UNR2w6awi8A0xbu9kdqfyVMKhYAXBcn6dW KATuS/1L6dopx5/VeRO5gxsYYQwmVDvDTaJpkwuqd5LwJcyD6hESs3Y42AsWb53XcLPrHE4yyfw CRtN4x3+nOPMEcHLMJoGctca5CZiiHHsT4sWK5L/yD9j2F/VIGD1kxcfqWLzXKEcgVrN+BG4Y5Z 9cceWx1Bhohem7dZir5NQx7v01wRn/tHivNSkXtLyi3ffsgLpV9couiKmcC3wVcdwJrj3PLq4o6 X/FY64Y19dOISJXYlDIkicH/kswdSjbAlc91A6NVMq1lrr1GEDUMvNt2Fl4B4UYKbZQw79QQF6C mOBQFXDb4+9fFw7uBj7KFl5EzzLeXg== X-Proofpoint-GUID: nhWqJ1bOdH0JlCViS8KZ3E29EdhJMja- X-Authority-Analysis: v=2.4 cv=f7BFxeyM c=1 sm=1 tr=0 ts=69255196 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=iVC9QAuiRl3Xz_40r_EA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: nhWqJ1bOdH0JlCViS8KZ3E29EdhJMja- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_01,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250054 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Display Processing Unit (DPU) version 13.0 on the Kaanapali platform. This version introduces changes to the SSPP sub-block structure. Add common block and rectangle blocks to accommodate these structural modifications for compatibility. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov --- .../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 535 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapal= i.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/d= rivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h new file mode 100644 index 000000000000..0b20401b04cf --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -0,0 +1,492 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DPU_13_0_KAANAPALI_H +#define _DPU_13_0_KAANAPALI_H + +static const struct dpu_caps kaanapali_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg kaanapali_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg kaanapali_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1f000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x20000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x21000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x22000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x23000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x24000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg kaanapali_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x2b000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x34000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x3d000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0x46000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x97000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0xa0000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0xa9000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0xb2000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0xbb000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0xc4000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg kaanapali_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x103000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x10b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x113000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x11b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x123000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x12b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x133000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x13b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg kaanapali_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x105000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x10d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x115000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x11d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg kaanapali_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x108000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x110000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x118000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x120000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x128000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x130000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x138000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x140000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x169000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x169400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x16a000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x16a400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x163000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x164000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x165000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x166000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x169700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x16a700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg kaanapali_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg kaanapali_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x16e000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg kaanapali_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x169200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x169600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x16a200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x16a600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg kaanapali_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x18d000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x18e000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x18f000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x190000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg kaanapali_perf_data =3D { + .max_bw_low =3D 21400000, + .max_bw_high =3D 30200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x0ffff, 0x0ffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(kaanapali_qos_linear), + .entries =3D kaanapali_qos_linear + }, + {.nentry =3D ARRAY_SIZE(kaanapali_qos_macrotile), + .entries =3D kaanapali_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version kaanapali_mdss_ver =3D { + .core_major_ver =3D 13, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_kaanapali_cfg =3D { + .mdss_ver =3D &kaanapali_mdss_ver, + .caps =3D &kaanapali_dpu_caps, + .mdp =3D &kaanapali_mdp, + .cdm =3D &dpu_cdm_13_x, + .ctl_count =3D ARRAY_SIZE(kaanapali_ctl), + .ctl =3D kaanapali_ctl, + .sspp_count =3D ARRAY_SIZE(kaanapali_sspp), + .sspp =3D kaanapali_sspp, + .mixer_count =3D ARRAY_SIZE(kaanapali_lm), + .mixer =3D kaanapali_lm, + .dspp_count =3D ARRAY_SIZE(kaanapali_dspp), + .dspp =3D kaanapali_dspp, + .pingpong_count =3D ARRAY_SIZE(kaanapali_pp), + .pingpong =3D kaanapali_pp, + .dsc_count =3D ARRAY_SIZE(kaanapali_dsc), + .dsc =3D kaanapali_dsc, + .merge_3d_count =3D ARRAY_SIZE(kaanapali_merge_3d), + .merge_3d =3D kaanapali_merge_3d, + .wb_count =3D ARRAY_SIZE(kaanapali_wb), + .wb =3D kaanapali_wb, + .cwb_count =3D ARRAY_SIZE(kaanapali_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(kaanapali_intf), + .intf =3D kaanapali_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &kaanapali_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 23bb39b471b7..be3492df8bde 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -241,6 +241,23 @@ static const u32 wb2_formats_rgb_yuv[] =3D { .rotation_cfg =3D NULL, \ } =20 +/* kaanapali SSPP common configuration */ +#define _VIG_SBLK_REC0_REC1(scaler_ver) \ + { \ + .sspp_rec0_blk =3D {.name =3D "sspp_rec0", \ + .base =3D 0x1000, .len =3D 0x180,}, \ + .csc_blk =3D {.name =3D "csc", \ + .base =3D 0x1800, .len =3D 0x100,}, \ + .scaler_blk =3D {.name =3D "scaler", \ + .version =3D scaler_ver, \ + .base =3D 0x2000, .len =3D 0xec,}, \ + .sspp_rec1_blk =3D {.name =3D "sspp_rec1", \ + .base =3D 0x3000, .len =3D 0x180,}, \ + .format_list =3D plane_formats_yuv, \ + .num_formats =3D ARRAY_SIZE(plane_formats_yuv), \ + .rotation_cfg =3D NULL, \ + } + #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ { \ .scaler_blk =3D {.name =3D "scaler", \ @@ -329,6 +346,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_3 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 4)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =3D + _VIG_SBLK_REC0_REC1(SSPP_SCALER_VER(3, 5)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -412,6 +432,11 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sb= lk =3D { .len =3D 0x20, .version =3D 0x20000}, }; =20 +static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk =3D { + .dither =3D {.name =3D "dither", .base =3D 0xc0, + .len =3D 0x40, .version =3D 0x30000}, +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -452,6 +477,13 @@ static const struct dpu_cdm_cfg dpu_cdm_5_x =3D { .base =3D 0x79200, }; =20 +static const struct dpu_cdm_cfg dpu_cdm_13_x =3D { + .name =3D "cdm_0", + .id =3D CDM_0, + .len =3D 0x240, + .base =3D 0x19e000, +}; + /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -639,6 +671,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_linear[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { {.fl =3D 0, .lut =3D 0x0011223445566777 }, }; @@ -668,6 +704,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macro= tile[] =3D { {.fl =3D 0, .lut =3D 0x0011223344556677}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] =3D { {.fl =3D 10, .lut =3D 0x0000000344556677}, }; @@ -727,3 +767,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_10_0_sm8650.h" #include "catalog/dpu_12_0_sm8750.h" #include "catalog/dpu_12_2_glymur.h" +#include "catalog/dpu_13_0_kaanapali.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index c996b08076a9..7c53490c6c83 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -775,6 +775,7 @@ struct dpu_mdss_cfg { }; =20 extern const struct dpu_mdss_cfg dpu_glymur_cfg; +extern const struct dpu_mdss_cfg dpu_kaanapali_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index f4c9767c418d..0623f1dbed97 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1506,6 +1506,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { =20 static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,glymur-dpu", .data =3D &dpu_glymur_cfg, }, + { .compatible =3D "qcom,kaanapali-dpu", .data =3D &dpu_kaanapali_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.34.1