From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EDCC33C52D; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764102580; cv=none; b=luBhFRdRs04XmK+YUGEPKe1gk2IkPqEpem4O+88KSgCwRN75YmsDGY/NDxHX8yRyVZMyR62ljwoVnLEJQrUY2VHd5JbzUkPh7moxzsLWeAPHfE6Kq8QdGV+bEMS7vFC23B21gCoBGVXGBALrY7X8vi/DE1Y7BmQx26vQmItk8lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764102580; c=relaxed/simple; bh=HjJDMUd9VNGNyS2sUGn4tel1CQSAz6Tp6zX5Z6lzkq8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pOsHACiBG8gxQQ0iLrfSF92G7w6QsJq2rzDGchg3Wka2F63cY/7ik4L7c4BUJjHV0YEnmMbXtuIlnoJ1BU8JqMtCL4MD51I2Uh4CyIZb6CkU1rxYDnHl/jkGXu5bKZzviSmPGEZnXVxVGn1E+W8M7lkej5/CAu4QO6skJbgBujc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DJt3K7vt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DJt3K7vt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2B3E7C116D0; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764102580; bh=HjJDMUd9VNGNyS2sUGn4tel1CQSAz6Tp6zX5Z6lzkq8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DJt3K7vtRHVni0LTuwpZoShwfF/dltrBf7bdA+Xlb7FLN5gWAemYKXFVFteQn753m hNEpp/gebDqu3DD3Kk4dkK4/86fH7uIutJEEPR2IOa/DJlvRcNdoTe7HwWcvH4XE8v 0DYvcGhuRwW9HXZl+yppO/WL5ltzJbLFXQ2BYOjj3fxl6durUaYk2Rb/8S0ShpHt1a Myja75zUH2JYdTi3j/0w147MVRgh+IOrEiacYTOKUMFIIHZ4rDFfVPbdUEo+6peSI9 rJW8ehh02oi1IRvwRi0Rt1h8PFdZwBcW/R0Q/rIeh0/1O7fdj6nFzNapYSKFUvX5Dt ZEgFWw77MFgRA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B203D0EE1C; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 25 Nov 2025 21:29:36 +0100 Subject: [PATCH v4 1/8] dt-bindings: arm: qcom: Add Pixel 3 and 3 XL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-1-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=765; i=david@ixit.cz; h=from:subject:message-id; bh=Vnt/xXHh7c01EXNWnpunAXvFyH2vLjx4UfYXxFc1+5w=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpJhGxIifGirp9T6Vi0DAyXs9lMbhdTd35xqlUn 8qk+HAK3iuJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaSYRsQAKCRBgAj/E00kg cmSAD/42LNDykpTI8CUnBYJaoFIPJ7gr61SFUWX/wcGFaT6C2JmQl0ufk9mk4SJQf2+9+kQxajf zK6BKujBbQA5EB7w8XgHhtEcnptt28L68Lf+yhrVEroUc64+/QWg7xuOZ14uZLVZNkKt44xQSSY 6Y8X5CmuyZdwIrIfPVAdRGxkdiVPqaR/Ezgu5m6997GfQfCXPQgRlOLGi8wbqIJlAsigon+1KZ3 1rIhiZxBlPFllYSco5fi40JVVze0WjDgVTEghHS8cmOE75rMtwPGT9pnbGZJJBBLoZfBCkIBY96 XJhHwb9pmqhVPW1a1i85npc9JOUtwLxf9vps0VZEdaJnMbiyZBYC0jj2FJJT/TApY0zYthispwp 9cppO17ulPjPja9axlm7LuZrG3AXCzTlfQcvGO+iDWcSMs+y3pAjrfa0rOB8ZxBZmwt+6F1uuwd CvP9Rx16JKJbes/F1ICQCvV/CUo2+qqK+GRGHonjgHuOP5Gv13Wn2hu4KxubFARWqG2IcSaR4yt 8WChH/9IlvmT2A7jQJGjAbYW9TiNd9qMD1kmlYVkx5nD5wIgmbb7BNt8Fr+hcT70TorQpeidVF1 e0U9kwoVWhVOTGzLqZVb1PNyCYWaFGwBQlaQ2eeeFDvqyrgLtvZu1QN/C4skK/8hvYi6vNn+pxL ZgWZGycOSfdsf0Q== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Document the bindings for the Pixel 3 and 3 XL. Acked-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca2010..760b6633b7a55 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -900,6 +900,8 @@ properties: =20 - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln --=20 2.51.0 From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AADDF33CE91; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-2-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1875; i=david@ixit.cz; h=from:subject:message-id; bh=NUtDhdxgm27JmLpy0LMIV+8SFYDHd5eqrKtd8gdhaI0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpJhGxa2kozTUZUMHAbh33k98FWegntz/YxT2q8 RDgtZMm88WJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaSYRsQAKCRBgAj/E00kg cql0EACzbJ7MRU5M/6U505fHRfvpRGxyfS9ImojQvXzjptKh6eHWy8N6ojZ50qxeoUMEE+XK6TE FEQYLma4Rj0pmaIJmwuI/J9+LuJ+wROdCMyG4f1GK2PZJwivSO5n+YdJX0XEbh9pm/NrAQ4xtIt YZNW5SIOGwG3jsw8Wo6jMPdHzmDv0qqtuku91wtwPAPSRtBgZK6tANumSRPKsVG7BJ8IMyYPP62 m+Lc2DskktcooHk6y8gTAJs00BLLziJWCSw+RnLx2dj892Nor1S4I9+qoUKV5iKl4YCVMTLwqry awR9Ch1fIIZo54cIq2PhsDIYsY6cUzpVocf6rA/RZ4LYRuyAVJncxE0BEP9xW6mMqVk3V9UArfx 8qZBgQwKRNLOzOMEtHE3n0X0eWuKEkSVXdG0PaC8fBa3mDLc0umYtIlLxcKktVp0kCiHofBX6hl F/9J+POci51fxUaSCtmVroAIITkzzuFBDMY+2mpavahYndEoIQPe13/uj/SJoHM//M8b52X6RJE +wRmELkKGZrHujsaBJxe32+ado4rW8qA7tOwtjIek+pm6ib5sTnlcRZAp7cDyHREUnx2Bi49VkI LQRG/cIetrMjrSXVRURsISnMTnL0LauA8GWAJorF4saXLUFEumaOJDKK7yfDYHJPZAqc0yYAYYd 41r+0fSUKOs+x0w== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Add compatible for used LG panel. SW43408 is not panel, but DDIC. The panel itself is the LG LH546WF1-ED01, so introduce combined compatible for it. Signed-off-by: David Heidelberg --- .../devicetree/bindings/display/panel/lg,sw43408.yaml | 13 +++++++++= ---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yam= l b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 2219d3d4ac43b..f641efaeb8b36 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LG SW43408 1080x2160 DSI panel +title: LG SW43408 AMOLED DDIC =20 maintainers: - Casey Connolly =20 description: - This panel is used on the Pixel 3, it is a 60hz OLED panel which - required DSC (Display Stream Compression) and has rounded corners. + The SW43408 is display driver IC with connected panel. + + LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel + which required DSC (Display Stream Compression) and has rounded corners. =20 allOf: - $ref: panel-common.yaml# @@ -19,6 +21,9 @@ allOf: properties: compatible: items: + - enum: + # LG 5.46 inch, 1080x2160 pixels, 18:9 ratio + - lg,sw43408-lh546wf1-ed01 - const: lg,sw43408 =20 reg: @@ -46,7 +51,7 @@ examples: #size-cells =3D <0>; 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Tue, 25 Nov 2025 20:29:40 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 25 Nov 2025 21:29:38 +0100 Subject: [PATCH v4 3/8] drm/panel: sw43408: Introduce LH546WF1-ED01 panel compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-3-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The supported panel is LH546WF1-ED01, add compatible and adjust the struct name to reflect that. The standalone compatible lg,sw43408 will continue to work, even thou there are no users yet. Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 46a56ea92ad9f..dcca7873acf8e 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -149,7 +149,7 @@ static int sw43408_prepare(struct drm_panel *panel) return ret; } =20 -static const struct drm_display_mode sw43408_mode =3D { +static const struct drm_display_mode lh546wf1_ed01_mode =3D { .clock =3D (1080 + 20 + 32 + 20) * (2160 + 20 + 4 + 20) * 60 / 1000, =20 .hdisplay =3D 1080, @@ -171,7 +171,7 @@ static const struct drm_display_mode sw43408_mode =3D { static int sw43408_get_modes(struct drm_panel *panel, struct drm_connector *connector) { - return drm_connector_helper_get_modes_fixed(connector, &sw43408_mode); + return drm_connector_helper_get_modes_fixed(connector, &lh546wf1_ed01_mod= e); } =20 static int sw43408_backlight_update_status(struct backlight_device *bl) @@ -214,7 +214,8 @@ static const struct drm_panel_funcs sw43408_funcs =3D { }; =20 static const struct of_device_id sw43408_of_match[] =3D { - { .compatible =3D "lg,sw43408", }, + { .compatible =3D "lg,sw43408", }, /* legacy */ + { .compatible =3D "lg,sw43408-lh546wf1-ed01", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sw43408_of_match); --=20 2.51.0 From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAE5833CE92; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764102580; cv=none; b=OzvkrVmpEDuyS3uuFiRP9PIUcPK2ZR7+1udJyMcwHkSrxCPD8BGmuEEmEZ9D79CKEFfBfMBSX3n9nbsftEocRbDny9r56+JgnphuxTg9Xk5wmuwO41pGPisDiFecGsCYrbphq7njpoPSCuE2C3pTGsfJ/9/kUMkwu35I0DlGiJY= ARC-Message-Signature: i=1; a=rsa-sha256; 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b=c05brCQyAXaYoDVve5H2cyU5lOZQuOW1VoD4yEgASgBIT/Qjgf1GwoG1Nd1/+90IL jjm/RyMUPqCu16BmISX3EhjgjenycjGW/GDYHcT5QgZNp1NsM9EdrgXr0g/A83GYfU RRiw/Zd9pcMFUHzqw1FANB40mwwx1Idy0z3nj92yOwLuk00Z7LVWbOhwsNThxIWcC/ nBhjOIMuzDcyrWLoR9kpBxEYPQ/SxQ/UF90lW2bDwyo7X3DIIK8mAa322J8yG0jeOi u5XSwDc8xTGX4+0Uog4gh6nUT0JQtXAJmQKqtCXGjNWzGCfZqfE+8X5fNfsdXbxKRl qRlnNuyOL/Ywg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52021D0EE1C; Tue, 25 Nov 2025 20:29:40 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 25 Nov 2025 21:29:39 +0100 Subject: [PATCH v4 4/8] drm/panel: sw43408: Add enable/disable and reset functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-4-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4880; i=david@ixit.cz; h=from:subject:message-id; bh=YlQ6X/JDXJqBsYiKSkEnQvOJfhJFKMivKfC8vTnULQ4=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpJhGy7DpqdrMysErdAcvvgd0lkis1gq+UapPrI BaqwQAfYAGJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaSYRsgAKCRBgAj/E00kg ctBbD/9yRQdZ8Nz7y3zldNwFNDBW7OC7sNFuYXYFHHOxT5XquF865DZ/8PDYBKwypgmTew8rAA3 ZPjHLPQ6TDkyqhFBnAJQ1EJzoDQbdtRJSkAdWNHOJ9uudICo1KNxIx/zyuseAZ5xQz4p9Hm8Z5R 4Qrx63j/MBaWcxQpyTrVtOZLzPbRc+2uN+Wmxzw5YgZxCLMXrP72amq0oVx31sEjnkfqnc/juZD HAMLT1Lnn22euetdFoRmDKBKcPjNyAgxqX7UDWFRbsSK7+m5Qgr07RtPmvku8De0hAEZeqib7wr xNonwZt1lhkR7Ma3tiwt/pa4ymedcT/DqJEtn0yJ0aTMM9+Vvczwinnwle5oeEyxyJfUf9R6uBX yRhGCOibyeNFo2C1x9ZSWULy9yE+sNZ+Axep68GfJS5J+sG1jn/5yVNoNTidVJ6NJsyYsdzOwsH pvkrNtowrELO8DO6a28+JXlyk0JWy7Swu+j6yHH1S3JR+8SUxxPinZxUR5A1DAEFVZbJ+qle8Wr S10lSRQ2811t2kpitYLhkIJN2m0QGlYDabgTHXsm9weENFLzJCfFSBdouZDrbgKiwTamL3UymFW JZLC5C0kts+aT7paA3YFm8zUL7tUkdv2qdY0la109s6wyEwOUfVaMliuT6l3MZSDmTw8B+OQU1U irvUVE0qKjARYbg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Introduce enable(), disable() and reset() functions. The enable() and disable() callbacks keep the symmetry in the commands sent to the panel and also make a clearer distinction between panel initialization and configuration. Splitting reset() from prepare() follows clean coding practices and lets us potentially make reset optional in the future for flicker-less takeover from a bootloader or framebuffer driver where the panel is already configured. Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 83 ++++++++++++++++++++--------= ---- 1 file changed, 53 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index dcca7873acf8e..20217877e107f 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -38,11 +38,10 @@ static inline struct sw43408_panel *to_panel_info(struc= t drm_panel *panel) return container_of(panel, struct sw43408_panel, base); } =20 -static int sw43408_unprepare(struct drm_panel *panel) +static int sw43408_disable(struct drm_panel *panel) { struct sw43408_panel *sw43408 =3D to_panel_info(panel); struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; - int ret; =20 mipi_dsi_dcs_set_display_off_multi(&ctx); =20 @@ -50,19 +49,55 @@ static int sw43408_unprepare(struct drm_panel *panel) =20 mipi_dsi_msleep(&ctx, 100); =20 + return ctx.accum_err; +} + +static int sw43408_unprepare(struct drm_panel *panel) +{ + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + int ret; + gpiod_set_value(sw43408->reset_gpio, 1); =20 ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->su= pplies); =20 - return ret ? : ctx.accum_err; + return ret; } =20 -static int sw43408_program(struct drm_panel *panel) +static int sw43408_enable(struct drm_panel *panel) { struct sw43408_panel *sw43408 =3D to_panel_info(panel); struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; struct drm_dsc_picture_parameter_set pps; =20 + mipi_dsi_dcs_set_display_on_multi(&ctx); + + mipi_dsi_msleep(&ctx, 50); + + sw43408->link->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + + drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); + + mipi_dsi_picture_parameter_set_multi(&ctx, &pps); + + sw43408->link->mode_flags |=3D MIPI_DSI_MODE_LPM; + + /* + * This panel uses PPS selectors with offset: + * PPS 1 if pps_identifier is 0 + * PPS 2 if pps_identifier is 1 + */ + mipi_dsi_compression_mode_ext_multi(&ctx, true, + MIPI_DSI_COMPRESSION_DSC, 1); + + return ctx.accum_err; +} + +static int sw43408_program(struct drm_panel *panel) +{ + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; + mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x02); =20 mipi_dsi_dcs_set_tear_on_multi(&ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); @@ -97,26 +132,19 @@ static int sw43408_program(struct drm_panel *panel) mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0x= db); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xca); =20 - mipi_dsi_dcs_set_display_on_multi(&ctx); - - mipi_dsi_msleep(&ctx, 50); - - sw43408->link->mode_flags &=3D ~MIPI_DSI_MODE_LPM; - - drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); - - mipi_dsi_picture_parameter_set_multi(&ctx, &pps); + return ctx.accum_err; +} =20 - sw43408->link->mode_flags |=3D MIPI_DSI_MODE_LPM; +static void sw43408_reset(struct sw43408_panel *ctx) +{ + usleep_range(5000, 6000); =20 - /* - * This panel uses PPS selectors with offset: - * PPS 1 if pps_identifier is 0 - * PPS 2 if pps_identifier is 1 - */ - mipi_dsi_compression_mode_ext_multi(&ctx, true, - MIPI_DSI_COMPRESSION_DSC, 1); - return ctx.accum_err; + gpiod_set_value(ctx->reset_gpio, 0); + usleep_range(9000, 10000); + gpiod_set_value(ctx->reset_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value(ctx->reset_gpio, 0); + usleep_range(9000, 10000); } =20 static int sw43408_prepare(struct drm_panel *panel) @@ -128,14 +156,7 @@ static int sw43408_prepare(struct drm_panel *panel) if (ret < 0) return ret; =20 - usleep_range(5000, 6000); - - gpiod_set_value(ctx->reset_gpio, 0); - usleep_range(9000, 10000); - gpiod_set_value(ctx->reset_gpio, 1); - usleep_range(1000, 2000); - gpiod_set_value(ctx->reset_gpio, 0); - usleep_range(9000, 10000); + sw43408_reset(ctx); =20 ret =3D sw43408_program(panel); if (ret) @@ -208,6 +229,8 @@ static int sw43408_backlight_init(struct sw43408_panel = *ctx) } =20 static const struct drm_panel_funcs sw43408_funcs =3D { + .disable =3D sw43408_disable, + .enable =3D sw43408_enable, .unprepare =3D sw43408_unprepare, .prepare =3D sw43408_prepare, .get_modes =3D sw43408_get_modes, --=20 2.51.0 From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D099C33D6C6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-5-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=969; i=david@ixit.cz; h=from:subject:message-id; bh=Y2VpcT0lnlNKMeu4qU9FUOJhj3qUtxUucFEOrKlLOu0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpJhGy29DVW1ZDB4AQrSaDhfvGKsTmJDE2UwIEf zWzCqilo9yJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaSYRsgAKCRBgAj/E00kg csM/EACghuFzOX10G//floun9w+PWksjWHMluIIoxNB1BNjcHZiVDwbXWw0b2DByPunlJjqVL0o GaVNW/HLxaOPD+YMtLE/hv4meYeyL/4ttLOj+jfx6qXU4mourc+jQcML48i4UfgnjJeawkFAZTH EKDmGsO/NkYlbGpAEw1Oe6wQaRXnAJA/b25ZBFH72SrV7LtoOlPfehE7Q8w/bkKj8ewdpEUEm7z fi+PHmJgTGqfBvS2v/vKY7GjUSB2pZuS82lE0Ozqn3wCOxm/euoEyxfy2x0/Cd9WcFWlY4NZskg ZVKq0YiZFJowlzgsyjEtzjxenF4CXfY4+5XWLfHwpOyNJlE6NGC7hadWeS3/LXPF4bWgV/2qCFc iyyleeG5mKsh9TZXLTnJc5yHkUdqCx3r6Tnltxg7Zwhl6xQicCjLi971GLFOiPIUNUi3dP/v6Ss +ThqtrPzXZMTroMUJaoGI5cgIONH0oqJPGaE+q0g6olBH/VYA67unT6MQBxUrM+DditHFbGqc9v 5mq6a2xYUywoUd+jgH3oxCxdSuWXiyYcDP7ifBpVgNYgWUMd1s67Og6OtlqccM8pw5E6FUiiEu4 Q3eiucJg0e/sk+lKInzyj25p8jk4zicvNriI/1RcVL/3pVlsL5xv/hN/gKUNq+3BpjKwgR3nZHJ rwVCLO9Ui1p1Bnw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The drm_panel_remove should take care of disable/unprepare. Remove the manual call from the sw43408_remove function. Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver") Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 20217877e107f..b46599a0b957b 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -318,10 +318,6 @@ static void sw43408_remove(struct mipi_dsi_device *dsi) struct sw43408_panel *ctx =3D mipi_dsi_get_drvdata(dsi); int ret; =20 - ret =3D sw43408_unprepare(&ctx->base); - if (ret < 0) - dev_err(&dsi->dev, "failed to unprepare panel: %d\n", ret); - ret =3D mipi_dsi_detach(dsi); if (ret < 0) dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); --=20 2.51.0 From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D054333D6C5; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Switch to devm_regulator_bulk_get_const() to stop setting the supplies list in probe(), and move the regulator_bulk_data struct in static const. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index b46599a0b957b..b147f337a7861 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -20,13 +20,18 @@ #include #include =20 -#define NUM_SUPPLIES 2 +static const struct regulator_bulk_data sw43408_supplies[] =3D { + { .supply =3D "vddi", /* 1.88V */ + .init_load_uA =3D 62000 }, + { .supply =3D "vpnl", /* 3.0 V */ + .init_load_uA =3D 857000 }, +}; =20 struct sw43408_panel { struct drm_panel base; struct mipi_dsi_device *link; =20 - struct regulator_bulk_data supplies[NUM_SUPPLIES]; + struct regulator_bulk_data *supplies; =20 struct gpio_desc *reset_gpio; =20 @@ -59,7 +64,7 @@ static int sw43408_unprepare(struct drm_panel *panel) =20 gpiod_set_value(sw43408->reset_gpio, 1); =20 - ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->su= pplies); + ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), sw43408->sup= plies); =20 return ret; } @@ -152,7 +157,7 @@ static int sw43408_prepare(struct drm_panel *panel) struct sw43408_panel *ctx =3D to_panel_info(panel); int ret; =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + ret =3D regulator_bulk_enable(ARRAY_SIZE(sw43408_supplies), ctx->supplies= ); if (ret < 0) return ret; =20 @@ -166,7 +171,7 @@ static int sw43408_prepare(struct drm_panel *panel) =20 poweroff: gpiod_set_value(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), ctx->supplies); return ret; } =20 @@ -248,13 +253,10 @@ static int sw43408_add(struct sw43408_panel *ctx) struct device *dev =3D &ctx->link->dev; int ret; =20 - ctx->supplies[0].supply =3D "vddi"; /* 1.88 V */ - ctx->supplies[0].init_load_uA =3D 62000; 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Cosmetic: also inline PTR_ERR. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index b147f337a7861..c6384b02ad6e0 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -262,8 +262,8 @@ static int sw43408_add(struct sw43408_panel *ctx) =20 ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(ctx->reset_gpio)) { - ret =3D PTR_ERR(ctx->reset_gpio); - return dev_err_probe(dev, ret, "cannot get reset gpio\n"); + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); } =20 ret =3D sw43408_backlight_init(ctx); --=20 2.51.0 From nobody Tue Dec 2 00:03:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BBD33D6F4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pixel-3-v4-8-3b706f8dcc96@ixit.cz> References: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> In-Reply-To: <20251125-pixel-3-v4-0-3b706f8dcc96@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg , Amit Pundir , Casey Connolly , Joel Selvaraj , Bjorn Andersson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=17506; i=david@ixit.cz; h=from:subject:message-id; bh=ui5t/leneY/T0yz+SGqJUR196L6ucezUqK0cwjITc74=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpJhGyywElEDke12ehGw/g0PmzCzj4le0BqEvB8 RE2oQcRVg2JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaSYRsgAKCRBgAj/E00kg cvs9EACrae06JGkav0Rbh6AW2Vq3M3F7XxEcAKZ8lhz2bv8t8A+KuxGaewMhrthbo/9akNGzkMz +Jw5FXBE8JTvs7o2oPgaF8YFhkztXS8wO8n8paoFoU2NqAgzYr6gyxvLunfBpl3o7P+IDACzfx5 SRQPghylyF7TaYt6ISMUUMwQ4cDR4lHPpCUS3lGE0AUlZ1bO2zQ6h1Epg9GtSBzVso21UVgdpea uHIqiJTcE/AzS/a8Wq3ozK5rM4S4rUKwA/2x7D+IW+CC57mfdlKNRwVkdlyzyZVZ4ZETLlnOjn3 ee/QpHEwdBuiFfMVO2ItIozS+TwfoHfKaYtMz5oiHN4L7HqtBKzy+ra2TQ0lKp+vbLQ5B2VIBnq YvkQ7m6G2+iIymaX3VQ+WU5IUPcW3dYnhEauy7EtvqTRW7pQy7IRFKeILY8NA3Mx2rH5eUVoEPo L794FdilLcZ3LEEEY8i8jgH5Kqj90Z7WK1L6WK3pycrXDli4aZZuHcU1D1oUUo9TgJUb48fkuIK xjx4jC/3z0LRJD3uABvnjt1eS9najgQ5bfYpnzcR3JKUOPlCJYMJrV87mv6KyF9VlLBYI6F5bKU siWR1OqNHkvw78AbMoFA02kaDH/kINcCRRZVPfPnT5ZIQPgFzDl0nXZ2Ezq4TkXu4jijqdJsYP3 G3Wr7+tWDgbS67Q== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg This adds initial device tree support for the following phones: - Google Pixel 3 (blueline) - Google Pixel 3 XL (crosshatch) Both phone boards use the same identifiers and differ only slightly in their connected peripherals. Supported functionality includes: - Debug UART - UFS - USB-C (peripheral mode) - Display (Pixel 3 only, and the driver needs improvements) - GPU - Bluetooth - Wi-Fi The rmtfs region is allocated using UIO, making it technically "dynamic." Its address and size can be read from sysfs: $ cat /sys/class/uio/uio0/name /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 $ cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either side of the rmtfs region to work around an XPU bug that would otherwise cause erroneous violations when accessing the rmtfs_mem region. Co-developed-by: Amit Pundir Signed-off-by: Amit Pundir Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Co-developed-by: Casey Connolly Signed-off-by: Casey Connolly Co-developed-by: Joel Selvaraj Signed-off-by: Joel Selvaraj Co-developed-by: Sumit Semwal Signed-off-by: Sumit Semwal Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 77 +++ arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 528 +++++++++++++++++= ++++ .../boot/dts/qcom/sdm845-google-crosshatch.dts | 28 ++ 4 files changed, 635 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c4..c853b28b3b198 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -250,6 +250,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs :=3D sdm845-db845c.dtb sdm845-db84= 5c-navigation-mezzanine.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm= 64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 0000000000000..94252c3fcf638 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3"; + compatible =3D "google,blueline", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <2970000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; +}; + +&framebuffer0 { + width =3D <1080>; + height =3D <2160>; + stride =3D <(1080 * 4)>; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vdda_mipi_dsi0_1p2>; + + status =3D "okay"; + + panel@0 { + compatible =3D "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; + reg =3D <0>; + + vddi-supply =3D <&vreg_l14a_1p88>; + vpnl-supply =3D <&vreg_l28a_3p0>; + + reset-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&panel_default>; + pinctrl-names =3D "default"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; + qcom,te-source =3D "mdp_vsync_e"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vdda_mipi_dsi0_pll>; + + status =3D "okay"; +}; + +&tlmm { + panel_default: panel-default-state { + reset-pins { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + te-pins { + pins =3D "gpio12"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 0000000000000..ad3bfc5b761f2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type =3D "handset"; + qcom,board-id =3D <0x00021505 0>; + qcom,msm-id =3D ; + + aliases { + serial0 =3D &uart9; + serial1 =3D &uart6; + }; + + battery: battery { + compatible =3D "simple-battery"; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0:115200n8"; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + format =3D "a8r8g8b8"; + }; + }; + + reserved-memory { + cont_splash_mem: splash@9d400000 { + reg =3D <0 0x9d400000 0 0x02400000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg =3D <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg =3D <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg =3D <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg =3D <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg =3D <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg =3D <0 0x99B00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@f2700000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0 0xf2700000 0 0x202000>; + qcom,use-guard-pages; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + label =3D "Volume keys"; + autorepeat; + + pinctrl-0 =3D <&volume_up_gpio>; + pinctrl-names =3D "default"; + + key-vol-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: regulator-vreg-s4a-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&adsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/adsp.mbn"; + + status =3D "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-s11-supply =3D <&vph_pwr>; + vdd-s12-supply =3D <&vph_pwr>; + vdd-s13-supply =3D <&vph_pwr>; + vdd-l1-l27-supply =3D <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply =3D <&vreg_s3a_1p35>; + vdd-l3-l11-supply =3D <&vreg_s7a_1p025>; + vdd-l4-l5-supply =3D <&vreg_s7a_1p025>; + vdd-l6-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p04>; + vdd-l9-supply =3D <&vreg_bob>; + vdd-l10-l23-l25-supply =3D <&vreg_bob>; + vdd-l13-l19-l21-supply =3D <&vreg_bob>; + vdd-l16-l28-supply =3D <&vreg_bob>; + vdd-l18-l22-supply =3D <&vreg_bob>; + vdd-l20-l24-supply =3D <&vreg_bob>; + vdd-l26-supply =3D <&vreg_s3a_1p35>; + vin-lvs-1-2-supply =3D <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes =3D ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt =3D <3088000>; + regulator-max-microvolt =3D <3088000>; + regulator-initial-mode =3D ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt =3D <2856000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob-supply =3D <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt =3D <3312000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + }; + }; +}; + +&cdsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/cdsp.mbn"; + + status =3D "okay"; +}; + +&gcc { + protected-clocks =3D , + , + ; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sdm845/Google/blueline/a630_zap.mbn"; +}; + +&i2c2 { + /* ST,FTS @ 49 */ +}; + +&i2c12 { + /* Bottom spkr (right) CS35L36 @ 40 */ + + /* Top spkr (left) CS35L36 @ 41 */ +}; + +&ipa { + firmware-name =3D "qcom/sdm845/Google/blueline/ipa_fws.mbn"; + memory-region =3D <&ipa_fw_mem>; + + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mss_pil { + firmware-name =3D "qcom/sdm845/Google/blueline/mba.mbn", + "qcom/sdm845/Google/blueline/modem.mbn"; + + status =3D "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins =3D "gpio6"; + function =3D "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength =3D <0>; + }; +}; + +&pm8998_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8998_charger { + monitored-battery =3D <&battery>; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qup_uart9_rx { + drive-strength =3D <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength =3D <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges =3D < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ + <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + + touchscreen_reset: ts-reset-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins =3D "gpio27", "gpio28"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 =3D <&qup_uart6_4pin>; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3990-bt"; + + vddio-supply =3D <&vreg_s4a_1p8>; + vddxo-supply =3D <&vreg_l7a_1p8>; + vddrf-supply =3D <&vreg_l17a_1p3>; + vddch0-supply =3D <&vreg_l25a_3p3>; + max-speed =3D <3200000>; + }; +}; + +&uart9 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l20a_2p95>; + vcc-max-microamp =3D <800000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l26a_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value =3D <8>; + qcom,hstx-trim-value =3D ; + qcom,preemphasis-level =3D ; + qcom,preemphasis-width =3D ; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l26a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p875>; + + status =3D "okay"; +}; + +&venus { + firmware-name =3D "qcom/sdm845/Google/blueline/venus.mbn"; + + status =3D "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply =3D <&vreg_l5a_0p8>; + vdd-1.8-xo-supply =3D <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply =3D <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply =3D <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/a= rm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 0000000000000..5cb0aa8b37fda --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3 XL"; + compatible =3D "google,crosshatch", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <3480000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; +}; + +&framebuffer0 { + width =3D <1440>; + height =3D <2960>; + stride =3D <(1440 * 4)>; +}; + +&mdss { + /* until the panel is prepared */ + status =3D "disabled"; +}; + --=20 2.51.0