From nobody Tue Dec 2 00:25:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A512EE607; Tue, 25 Nov 2025 11:12:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=bCjEmQZpncFC4nV4bv/JVEA+nmsxAl5vTGSC0gE8l3c9WehDouFTPOxFqhnJMflaZF0zUxDTPj00SyYA4F+KGTDcSgAqgxWiLYCbGbkIR0VK3bDDTZqvSXDbP1JnyLjMs5RTXzE57HrfhVvRymZm+13rtVSrFoa821GZx9EMt8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=Edqa6OpPk8f7rB2jKU7f0A/LZHVbyTcG6DfDZ5FqVbA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gGFBRn9RgQqyTPZccUs5KtO+q7RPg673uOd6rrKyINCMORqdSPcZv3jpYQXvS7GQVLfh4LcThUuvw0qknXsyFz8MNmorBzBzrTICWzareJ1Q9PXf8pp+1gr0CUVjO66hG9sM0AqpCxKBuKb25anKpTnpKjg7xQMN7OfhhOXU3Dg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qgh/HTLt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qgh/HTLt" Received: by smtp.kernel.org (Postfix) with ESMTPS id C1C81C19421; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=Edqa6OpPk8f7rB2jKU7f0A/LZHVbyTcG6DfDZ5FqVbA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qgh/HTLt+jKCqcpnpVS8sHzYgi/zQDIaQCP8uHSrrGIYggrL/0uJsyZIfqkvKfu3H mil10lC/FK1KKMbZwihrXro0yCmcxsF7fLFNNHqJ1pQNJ92pK4QT3+b8p37ofsx/39 B8gpavrJ2h92tiJ145P62g16mS9YtUf7XtTgTtMDoLRRz6pvcVj0suiWRswpmRcoEI VzWVYhSUEFxDRz2FHYSKblyFHGhSyfOU+zLOjpi45mZWFoN5tyQdxDO++omtyGLSYd uGxIak+GAhN3i6lD2eNSi+ojUGBZY3lCzvzXOj9tZu5jZpCAl1vrwQ8xA0NZRh4mF6 QC/GGb1INGDHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9466D0E6C8; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:29 +0530 Subject: [PATCH v3 4/4] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-4-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7625; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=mzKLzX0N7HkTgchcdcukKH0GHh9HPu3ttPx9QsuX9Hc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dxIqY6I0iMS6V4M75VuKWcYXnEH5b8HlgW EI1TFIpW3SJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9R5oB/4wu6yKNvBO57TocCEjKvlaqxPbTup0xrwXCI7lyyK4WvLNQ7g6yLYwlfyiPirJhDab3PQ XQpJY5WYiXfRCkqc4TtkNQlMBqFFrrvc4baMaDs77Wrro+QlRfKeoHf+lNtBppec4PsTZ0/c+1u fotrX15c2DZ1cqVxKplS9I2f+aITdNhXCEGj10AOl0InEWaervLapGlXWl1X4d2cEKv8fWp7cmt cJ0gBWBRxCmuSgidFy+q5s6nML/jE1d3G2kUhTQM+BxgTVNxC6DUmomFAoC8HY7YQ+ssrFP62cj Iy+iKOMivvfhSlTgb8h8Bg/v2bB8kTo8tQ4R+CGyYZizGEms X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam This driver is used to control the PCIe M.2 connectors of different Mechanical Keys attached to the host machines and supporting different interfaces like PCIe/SATA, USB/UART etc... Currently, this driver supports only the Mechanical Key M connectors with PCIe interface. The driver also only supports driving the mandatory 3.3v and optional 1.8v power supplies. The optional signals of the Key M connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 7 ++ drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 160 ++++++++++++++++++++++++++= ++++ 4 files changed, 176 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..9b3f689d1f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20474,6 +20474,13 @@ F: Documentation/driver-api/pwrseq.rst F: drivers/power/sequencing/ F: include/linux/pwrseq/ =20 +PCIE M.2 POWER SEQUENCING +M: Manivannan Sadhasivam +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml +F: drivers/power/sequencing/pwrseq-pcie-m2.c + POWER STATE COORDINATION INTERFACE (PSCI) M: Mark Rutland M: Lorenzo Pieralisi diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 280f92beb5d0..f5fff84566ba 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU GPU. This driver handles the complex clock and reset sequence required to power on the Imagination BXM GPU on this platform. =20 +config POWER_SEQUENCING_PCIE_M2 + tristate "PCIe M.2 connector power sequencing driver" + depends on OF || COMPILE_TEST + help + Say Y here to enable the power sequencing driver for PCIe M.2 + connectors. This driver handles the power sequencing for the M.2 + connectors exposing multiple interfaces like PCIe, SATA, UART, etc... + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 96c1cf0a98ac..0911d4618298 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -5,3 +5,4 @@ pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o +obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c new file mode 100644 index 000000000000..4835d099d967 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_pcie_m2_pdata { + const struct pwrseq_target_data **targets; +}; + +struct pwrseq_pcie_m2_ctx { + struct pwrseq_device *pwrseq; + struct device_node *of_node; + const struct pwrseq_pcie_m2_pdata *pdata; + struct regulator_bulk_data *regs; + size_t num_vregs; + struct notifier_block nb; +}; + +static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_enable(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_disable(ctx->num_vregs, ctx->regs); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { + .name =3D "regulators-enable", + .enable =3D pwrseq_pcie_m2_m_vregs_enable, + .disable =3D pwrseq_pcie_m2_m_vregs_disable, +}; + +static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { + &pwrseq_pcie_m2_vregs_unit_data, + NULL +}; + +static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_m_unit_deps, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, +}; + +static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { + &pwrseq_pcie_m2_m_pcie_target_data, + NULL +}; + +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { + .targets =3D pwrseq_pcie_m2_m_targets, +}; + +static int pwrseq_pcie_m2_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + struct device_node *endpoint __free(device_node) =3D NULL; + + /* + * Traverse the 'remote-endpoint' nodes and check if the remote node's + * parent matches the OF node of 'dev'. + */ + for_each_endpoint_of_node(ctx->of_node, endpoint) { + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_port_parent(endpoint); + if (remote && (remote =3D=3D dev_of_node(dev))) + return PWRSEQ_MATCH_OK; + } + + return PWRSEQ_NO_MATCH; +} + +static int pwrseq_pcie_m2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwrseq_pcie_m2_ctx *ctx; + struct pwrseq_config config =3D {}; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->of_node =3D dev_of_node(dev); + ctx->pdata =3D device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + /* + * Currently, of_regulator_bulk_get_all() is the only regulator API that + * allows to get all supplies in the devicetree node without manually + * specifying them. + */ + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + ctx->num_vregs =3D ret; + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_pcie_m2_match; + config.targets =3D ctx->pdata->targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) { + regulator_bulk_free(ctx->num_vregs, ctx->regs); + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register the power sequencer\n"); + } + + return 0; +} + +static const struct of_device_id pwrseq_pcie_m2_of_match[] =3D { + { + .compatible =3D "pcie-m2-m-connector", + .data =3D &pwrseq_pcie_m2_m_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); + +static struct platform_driver pwrseq_pcie_m2_driver =3D { + .driver =3D { + .name =3D "pwrseq-pcie-m2", + .of_match_table =3D pwrseq_pcie_m2_of_match, + }, + .probe =3D pwrseq_pcie_m2_probe, +}; +module_platform_driver(pwrseq_pcie_m2_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Power Sequencing driver for PCIe M.2 connector"); +MODULE_LICENSE("GPL"); --=20 2.48.1