From nobody Tue Dec 2 00:25:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21F7329B795; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=iCblIuuaw4KLEo2T5Wh+GmEL40Db9gSONwcBa3UjGgDAJVLz8+6c8EH79Lo0BExUY70Tc48yEZAoGZnyWZCJccEgSruO+j+93VrtP1NLJmTzyU2jDffakeJFomRpxD1bf55vwsvuYCGd2hlsArTKUXLmjjCwNvIfdyKZTut5scc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=TdY/Q2esA7fjGCbY16Y/7BsFURyPP/oQf6cnQxXJtlU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ubpiLcYWOkAm6XJFkNMYG1W7OinScpE9Pw0gquuEsVVtQR0X9ZglRRZ+JnCSqF7V+Rr9+0urSATeofm/HxjL/xDMdM+tBndLdyy5zfmTB/08qhM1Ye3JTNRyjd9uFF63M/wqRpBtDHEz+VHuTAFJJgzcsDIPKEd4N3zKMs7iPCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BQV13Wz5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BQV13Wz5" Received: by smtp.kernel.org (Postfix) with ESMTPS id A4683C116B1; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=TdY/Q2esA7fjGCbY16Y/7BsFURyPP/oQf6cnQxXJtlU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BQV13Wz5PZqh202S2C7mM3FmFv7W0mvYwDB7WGQ1V6Qf8E12Pu5EibR1Q7UPFi1n+ cCpT6j0WSoAl/iLMWOs6aK6WkdPO79ANDo3s0YI5DXAEY3WJDUGN8U6akC2Cewpnsy nWIYrjFydQ2ZMYbWNI27TEQOo2EJuqmaF2U8WcxfyJlE6LnwKIK4z3q2Lu4f30/2l5 9OwonaJ7huvICVRSJnxuElQhXedMcRzGjOU50Vh06oXmDhIB8gaP06o2LL4s33RkTU JhUJc5tSnk16lLD7WFwroVRUenXWdeq83ZFtSxqOByp5rxKcFajtZe2Nsi5r3b2W5H A0LQiSZs0qKkg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95F15D0E6C7; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:27 +0530 Subject: [PATCH v3 2/4] PCI/pwrctrl: Add support for handling PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-2-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3872; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=HTvHAc0W+gqT3Gny5NRdE5ZGDr0iND6zrMawYcBU9kc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dw2Hnsq2BXwbXXvxR2p7knFdcX9j6VsUKh K7Y8RrGG3CJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9dcsB/4iw/bZmwyrAulLrLhnkj0HJ3jT02zpCt/xig3ohfMT8P5DAB1EzRr69yjxEvI8cDFR9NN GwyE2MMhlJzZCFMKT+GRqniTAoKeMNGUwtiTl2EYJHTPNe4CvxROx2YO2tNlaFivzIU6HjLVJjA l34KUHOCOZYj2MpEfPGEEi70gnpDFjsnCZOVY9uXh9hTLfY0DhCBhpZsl75imEugxirj972KGQe Ko2gUUekn2eNE9F2ZWOovC3SYqqQh/a8JYBEwrSSnU3BtyktARqhacqr3RhiDdP/KN03Bu/Dm+I gi7Jz+HNt3vJ+C4c6Js/BKdboitwqXA2cI8mozzuH0KeXMHF X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the PCIe M.2 connectors as Power Sequencing devices. These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 6956c1854811..9a195cb7e117 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; } =20 - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, - slot); - if (ret) - return ret; - clk =3D devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(clk)) { + regulator_bulk_disable(slot->num_supplies, slot->supplies); + regulator_bulk_free(slot->num_supplies, slot->supplies); return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); } =20 +skip_resources: + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + slot); + if (ret) + return ret; + pci_pwrctrl_init(&slot->ctx, dev); =20 ret =3D devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); --=20 2.48.1