From nobody Tue Dec 2 00:25:28 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDFC73148D7; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=PSP5IzTBLzWuAjUpNa64NjBL1GYr47Anp7jEQ+KDSk/6ubU7/yF2t61rKOvyJxMWFa0emTX42VPuto9j2PIR/pTgca9UX7sW0NttEvca35SK3/kYS8GQY/8nBW7PUcta4puOcDGqUGDWdYlcSwClYOl7LWaWkVR7V5ge7D10LsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=ncBuZsz3S9VpYYS3MhIzB+JWwuOwWOIy7kOlMKxIXr4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mFlvGXDBDdZ89miZaBR+v2F8FHow3Oe4OWC0GN34dZvFnt5zxfffOmFzkeMHFmIyOgtQfq4mWHEMaTo3+/vILSTwtY465YbgmN3254r6DCqTICvr7YvhO6jf76WO/2Q0s/ARA/AQVwBSMNNBvJj0hWU6yXv6zjCMAMRH00uZFlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u3Esag3f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u3Esag3f" Received: by smtp.kernel.org (Postfix) with ESMTPS id 93230C116D0; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=ncBuZsz3S9VpYYS3MhIzB+JWwuOwWOIy7kOlMKxIXr4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=u3Esag3flf3whGCC32nFs1OJ6jnWhk73ftd598cBYfcXVrsjasaBiWyWb7Cvfo0SI f8ne6w1Kl4vnPWJq/ooKn9NLi/iyBcpXEQZiHZau4AQX9SWGMWUnsvqu9i1um80yam ZLpYmsXu/fHBCXdsn2hAkvfPSMUItIsB/B7vgzZnBHROdBsXkYZub0kwNOVYVSZsI7 ZxrhRg7xEliWfSarqZ6HosLIRiIB/kqvHca+WJMbUPsC+8q86jVJ8Vppa37FnpdQTA 9WrH4aMAZJkQw4a9naDkL0ygOBCfBz93mz9cgceoQgENDUj9MutbYI7AZRzQ2zfThj lboeD8S7/tJuA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842A7D0E6C6; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:26 +0530 Subject: [PATCH v3 1/4] dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-1-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6096; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=R364tNw/jCl5Cu8x11j0DwL79urz2XK+pPjFAVTv1/w=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dhhgPVIMBaHWaxQntRNIqwuVBMufL8shON /cpJymbQDKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9ZvdB/4x53iErNy1kpDEL/7QY1lN3y1wK8ZnzZUncl44JMbcyLWdWdWNiNeqoVs7VYqSkEGG0Ep ymzbJMWv4+2BGIhCulL3VsPK8mP7JZqzV6etKindd7A8CxOmOnG1wUx8Kc1jEZx/7noxsyS9YFs zUU2CpbODg2kh8uj3PSsAsp0QDLFGIKQvUEEdKeAH2JA6nbpdhnwDZAz9lb4XErmzHepKn5F3w0 polaatAg3tGwf9tVe8QNiW7peuKD1Nf0OUfsZUIUtyWSPCJClZy1rWIaBXyHZI3gzOAZJyBoYqT cfx/w5XtnZ2+SDAy0y+lXsJCp9nYXNPRav9CH8c2I58RKMNU X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMB for debugging and supplementary features. At any point of time, the connector can only support either PCIe or SATA as the primary host interface. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- .../bindings/connector/pcie-m2-m-connector.yaml | 141 +++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..f65a05d93735 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMB. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Host interfaces of the connector + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: PCIe interface + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: SATA interface + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: SMB interface + + required: + - port@0 + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO controlled connection to PEDET signal. This signal i= s used + by the host systems to determine the communication protocol that the= M.2 + card uses; SATA signaling (low) or PCIe signaling (high). Refer, PCI + Express M.2 Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + led1-gpios: + description: GPIO controlled connection to LED_1# signal. This signal = is + used by the M.2 card to indicate the card status via the system moun= ted + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more + details. + maxItems: 1 + + viocfg-gpios: + description: GPIO controlled connection to IO voltage configuration + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to= the + host system that the card supports an independent IO voltage domain = for + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec + 3.1.15.1 for more details. + maxItems: 1 + + pwrdis-gpios: + description: GPIO controlled connection to Power Disable (PWRDIS) sign= al. + This signal is used by the host system to disable power on the M.2 c= ard. + Refer, PCI Express M.2 Specification r4.0, sec 3.3.5.2 for more deta= ils. + maxItems: 1 + + pln-gpios: + description: GPIO controlled connection to Power Loss Notification (PL= N#) + signal. This signal is use to notify the M.2 card by the host system= that + the power loss event is expected to occur. Refer, PCI Express M.2 + Specification r4.0, sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO controlled connection to Power Loss Acknowledge (PLA= _S3#) + signal. This signal is used by the M.2 card to notify the host syste= m, the + status of the M.2 card's preparation for power loss. + maxItems: 1 + +required: + - compatible + - vpcie3v3-supply + +additionalProperties: false + +examples: + # PCI M.2 Key M connector for SSDs with PCIe interface + - | + connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vreg_nvme>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie6_port0_ep>; + }; + }; + }; + }; --=20 2.48.1