From nobody Tue Dec 2 00:02:29 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDFC73148D7; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=PSP5IzTBLzWuAjUpNa64NjBL1GYr47Anp7jEQ+KDSk/6ubU7/yF2t61rKOvyJxMWFa0emTX42VPuto9j2PIR/pTgca9UX7sW0NttEvca35SK3/kYS8GQY/8nBW7PUcta4puOcDGqUGDWdYlcSwClYOl7LWaWkVR7V5ge7D10LsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=ncBuZsz3S9VpYYS3MhIzB+JWwuOwWOIy7kOlMKxIXr4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mFlvGXDBDdZ89miZaBR+v2F8FHow3Oe4OWC0GN34dZvFnt5zxfffOmFzkeMHFmIyOgtQfq4mWHEMaTo3+/vILSTwtY465YbgmN3254r6DCqTICvr7YvhO6jf76WO/2Q0s/ARA/AQVwBSMNNBvJj0hWU6yXv6zjCMAMRH00uZFlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u3Esag3f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u3Esag3f" Received: by smtp.kernel.org (Postfix) with ESMTPS id 93230C116D0; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=ncBuZsz3S9VpYYS3MhIzB+JWwuOwWOIy7kOlMKxIXr4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=u3Esag3flf3whGCC32nFs1OJ6jnWhk73ftd598cBYfcXVrsjasaBiWyWb7Cvfo0SI f8ne6w1Kl4vnPWJq/ooKn9NLi/iyBcpXEQZiHZau4AQX9SWGMWUnsvqu9i1um80yam ZLpYmsXu/fHBCXdsn2hAkvfPSMUItIsB/B7vgzZnBHROdBsXkYZub0kwNOVYVSZsI7 ZxrhRg7xEliWfSarqZ6HosLIRiIB/kqvHca+WJMbUPsC+8q86jVJ8Vppa37FnpdQTA 9WrH4aMAZJkQw4a9naDkL0ygOBCfBz93mz9cgceoQgENDUj9MutbYI7AZRzQ2zfThj lboeD8S7/tJuA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842A7D0E6C6; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:26 +0530 Subject: [PATCH v3 1/4] dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-1-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6096; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=R364tNw/jCl5Cu8x11j0DwL79urz2XK+pPjFAVTv1/w=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dhhgPVIMBaHWaxQntRNIqwuVBMufL8shON /cpJymbQDKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9ZvdB/4x53iErNy1kpDEL/7QY1lN3y1wK8ZnzZUncl44JMbcyLWdWdWNiNeqoVs7VYqSkEGG0Ep ymzbJMWv4+2BGIhCulL3VsPK8mP7JZqzV6etKindd7A8CxOmOnG1wUx8Kc1jEZx/7noxsyS9YFs zUU2CpbODg2kh8uj3PSsAsp0QDLFGIKQvUEEdKeAH2JA6nbpdhnwDZAz9lb4XErmzHepKn5F3w0 polaatAg3tGwf9tVe8QNiW7peuKD1Nf0OUfsZUIUtyWSPCJClZy1rWIaBXyHZI3gzOAZJyBoYqT cfx/w5XtnZ2+SDAy0y+lXsJCp9nYXNPRav9CH8c2I58RKMNU X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMB for debugging and supplementary features. At any point of time, the connector can only support either PCIe or SATA as the primary host interface. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- .../bindings/connector/pcie-m2-m-connector.yaml | 141 +++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..f65a05d93735 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMB. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Host interfaces of the connector + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: PCIe interface + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: SATA interface + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: SMB interface + + required: + - port@0 + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO controlled connection to PEDET signal. This signal i= s used + by the host systems to determine the communication protocol that the= M.2 + card uses; SATA signaling (low) or PCIe signaling (high). Refer, PCI + Express M.2 Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + led1-gpios: + description: GPIO controlled connection to LED_1# signal. This signal = is + used by the M.2 card to indicate the card status via the system moun= ted + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more + details. + maxItems: 1 + + viocfg-gpios: + description: GPIO controlled connection to IO voltage configuration + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to= the + host system that the card supports an independent IO voltage domain = for + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec + 3.1.15.1 for more details. + maxItems: 1 + + pwrdis-gpios: + description: GPIO controlled connection to Power Disable (PWRDIS) sign= al. + This signal is used by the host system to disable power on the M.2 c= ard. + Refer, PCI Express M.2 Specification r4.0, sec 3.3.5.2 for more deta= ils. + maxItems: 1 + + pln-gpios: + description: GPIO controlled connection to Power Loss Notification (PL= N#) + signal. This signal is use to notify the M.2 card by the host system= that + the power loss event is expected to occur. Refer, PCI Express M.2 + Specification r4.0, sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO controlled connection to Power Loss Acknowledge (PLA= _S3#) + signal. This signal is used by the M.2 card to notify the host syste= m, the + status of the M.2 card's preparation for power loss. + maxItems: 1 + +required: + - compatible + - vpcie3v3-supply + +additionalProperties: false + +examples: + # PCI M.2 Key M connector for SSDs with PCIe interface + - | + connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vreg_nvme>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie6_port0_ep>; + }; + }; + }; + }; --=20 2.48.1 From nobody Tue Dec 2 00:02:29 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21F7329B795; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=iCblIuuaw4KLEo2T5Wh+GmEL40Db9gSONwcBa3UjGgDAJVLz8+6c8EH79Lo0BExUY70Tc48yEZAoGZnyWZCJccEgSruO+j+93VrtP1NLJmTzyU2jDffakeJFomRpxD1bf55vwsvuYCGd2hlsArTKUXLmjjCwNvIfdyKZTut5scc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=TdY/Q2esA7fjGCbY16Y/7BsFURyPP/oQf6cnQxXJtlU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ubpiLcYWOkAm6XJFkNMYG1W7OinScpE9Pw0gquuEsVVtQR0X9ZglRRZ+JnCSqF7V+Rr9+0urSATeofm/HxjL/xDMdM+tBndLdyy5zfmTB/08qhM1Ye3JTNRyjd9uFF63M/wqRpBtDHEz+VHuTAFJJgzcsDIPKEd4N3zKMs7iPCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BQV13Wz5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BQV13Wz5" Received: by smtp.kernel.org (Postfix) with ESMTPS id A4683C116B1; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=TdY/Q2esA7fjGCbY16Y/7BsFURyPP/oQf6cnQxXJtlU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BQV13Wz5PZqh202S2C7mM3FmFv7W0mvYwDB7WGQ1V6Qf8E12Pu5EibR1Q7UPFi1n+ cCpT6j0WSoAl/iLMWOs6aK6WkdPO79ANDo3s0YI5DXAEY3WJDUGN8U6akC2Cewpnsy nWIYrjFydQ2ZMYbWNI27TEQOo2EJuqmaF2U8WcxfyJlE6LnwKIK4z3q2Lu4f30/2l5 9OwonaJ7huvICVRSJnxuElQhXedMcRzGjOU50Vh06oXmDhIB8gaP06o2LL4s33RkTU JhUJc5tSnk16lLD7WFwroVRUenXWdeq83ZFtSxqOByp5rxKcFajtZe2Nsi5r3b2W5H A0LQiSZs0qKkg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95F15D0E6C7; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:27 +0530 Subject: [PATCH v3 2/4] PCI/pwrctrl: Add support for handling PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-2-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3872; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=HTvHAc0W+gqT3Gny5NRdE5ZGDr0iND6zrMawYcBU9kc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dw2Hnsq2BXwbXXvxR2p7knFdcX9j6VsUKh K7Y8RrGG3CJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9dcsB/4iw/bZmwyrAulLrLhnkj0HJ3jT02zpCt/xig3ohfMT8P5DAB1EzRr69yjxEvI8cDFR9NN GwyE2MMhlJzZCFMKT+GRqniTAoKeMNGUwtiTl2EYJHTPNe4CvxROx2YO2tNlaFivzIU6HjLVJjA l34KUHOCOZYj2MpEfPGEEi70gnpDFjsnCZOVY9uXh9hTLfY0DhCBhpZsl75imEugxirj972KGQe Ko2gUUekn2eNE9F2ZWOovC3SYqqQh/a8JYBEwrSSnU3BtyktARqhacqr3RhiDdP/KN03Bu/Dm+I gi7Jz+HNt3vJ+C4c6Js/BKdboitwqXA2cI8mozzuH0KeXMHF X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the PCIe M.2 connectors as Power Sequencing devices. These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 6956c1854811..9a195cb7e117 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; } =20 - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, - slot); - if (ret) - return ret; - clk =3D devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(clk)) { + regulator_bulk_disable(slot->num_supplies, slot->supplies); + regulator_bulk_free(slot->num_supplies, slot->supplies); return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); } =20 +skip_resources: + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + slot); + if (ret) + return ret; + pci_pwrctrl_init(&slot->ctx, dev); =20 ret =3D devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); --=20 2.48.1 From nobody Tue Dec 2 00:02:29 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42ADE314D16; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-3-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1400; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=85qx2Om/7njPst0xF59AZpGkw5zpMb/2p4I8tf0rGZI=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8d8dHupd6VCH/oWWZ7QPaB9MbZJaUhUHcND zboN2Jf2ECJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9TkcB/9SuTMoRU5JJS6C646WFkzzsHd2Ulg4rKImNms7pLcqqyrc6/P7U0Bco+g0Cax4FvkIJzy iF/h8h/aXc+tjDqcq//6cF6mYbyfUxH22QfN0ePqMWbFkQ8TbV/mVKwLOqjexHCzX3AtMvuUuhi xKOUsCwhpKncFXKZ4lFt76UehmJiKM8bfEW0G6ILwrcuSmrIFs3osDINLRceMHuN2/54MEb1iYf y07jsNw+NtFtNEBcQ4MaXNK1Dg3p2xrjlG9jT3Dsfw8Fo1hFo5q9pedfto3QmEcuQyFsq8VBkUm AEqmE7RCcFuAw/UEp4ZiWk5C7HcNKIV0lzQdlrQc61jzdTEv X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam The devicetree node of the PCIe Root Port/Slot could have the graph port to link the PCIe M.2 connector node. Since the M.2 connectors are modelled as Power Sequencing devices, they need to be controlled by the pwrctrl driver as like the Root Port/Slot supplies. Hence, create the pwrctrl device if the graph port is found in the node. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index c83e75a0ec12..9c8669e2fe72 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -2555,7 +2556,7 @@ static struct platform_device *pci_pwrctrl_create_dev= ice(struct pci_bus *bus, in * not. This is decided based on at least one of the power supplies * being defined in the devicetree node of the device. */ - if (!of_pci_supply_present(np)) { + if (!of_pci_supply_present(np) && !of_graph_is_present(np)) { pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name); goto err_put_of_node; } --=20 2.48.1 From nobody Tue Dec 2 00:02:29 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A512EE607; Tue, 25 Nov 2025 11:12:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; cv=none; b=bCjEmQZpncFC4nV4bv/JVEA+nmsxAl5vTGSC0gE8l3c9WehDouFTPOxFqhnJMflaZF0zUxDTPj00SyYA4F+KGTDcSgAqgxWiLYCbGbkIR0VK3bDDTZqvSXDbP1JnyLjMs5RTXzE57HrfhVvRymZm+13rtVSrFoa821GZx9EMt8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764069153; c=relaxed/simple; bh=Edqa6OpPk8f7rB2jKU7f0A/LZHVbyTcG6DfDZ5FqVbA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gGFBRn9RgQqyTPZccUs5KtO+q7RPg673uOd6rrKyINCMORqdSPcZv3jpYQXvS7GQVLfh4LcThUuvw0qknXsyFz8MNmorBzBzrTICWzareJ1Q9PXf8pp+1gr0CUVjO66hG9sM0AqpCxKBuKb25anKpTnpKjg7xQMN7OfhhOXU3Dg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qgh/HTLt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qgh/HTLt" Received: by smtp.kernel.org (Postfix) with ESMTPS id C1C81C19421; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764069152; bh=Edqa6OpPk8f7rB2jKU7f0A/LZHVbyTcG6DfDZ5FqVbA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qgh/HTLt+jKCqcpnpVS8sHzYgi/zQDIaQCP8uHSrrGIYggrL/0uJsyZIfqkvKfu3H mil10lC/FK1KKMbZwihrXro0yCmcxsF7fLFNNHqJ1pQNJ92pK4QT3+b8p37ofsx/39 B8gpavrJ2h92tiJ145P62g16mS9YtUf7XtTgTtMDoLRRz6pvcVj0suiWRswpmRcoEI VzWVYhSUEFxDRz2FHYSKblyFHGhSyfOU+zLOjpi45mZWFoN5tyQdxDO++omtyGLSYd uGxIak+GAhN3i6lD2eNSi+ojUGBZY3lCzvzXOj9tZu5jZpCAl1vrwQ8xA0NZRh4mF6 QC/GGb1INGDHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9466D0E6C8; Tue, 25 Nov 2025 11:12:32 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 25 Nov 2025 16:42:29 +0530 Subject: [PATCH v3 4/4] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-pci-m2-v3-4-c528042aea47@oss.qualcomm.com> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> In-Reply-To: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7625; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=mzKLzX0N7HkTgchcdcukKH0GHh9HPu3ttPx9QsuX9Hc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpJY8dxIqY6I0iMS6V4M75VuKWcYXnEH5b8HlgW EI1TFIpW3SJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaSWPHQAKCRBVnxHm/pHO 9R5oB/4wu6yKNvBO57TocCEjKvlaqxPbTup0xrwXCI7lyyK4WvLNQ7g6yLYwlfyiPirJhDab3PQ XQpJY5WYiXfRCkqc4TtkNQlMBqFFrrvc4baMaDs77Wrro+QlRfKeoHf+lNtBppec4PsTZ0/c+1u fotrX15c2DZ1cqVxKplS9I2f+aITdNhXCEGj10AOl0InEWaervLapGlXWl1X4d2cEKv8fWp7cmt cJ0gBWBRxCmuSgidFy+q5s6nML/jE1d3G2kUhTQM+BxgTVNxC6DUmomFAoC8HY7YQ+ssrFP62cj Iy+iKOMivvfhSlTgb8h8Bg/v2bB8kTo8tQ4R+CGyYZizGEms X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam This driver is used to control the PCIe M.2 connectors of different Mechanical Keys attached to the host machines and supporting different interfaces like PCIe/SATA, USB/UART etc... Currently, this driver supports only the Mechanical Key M connectors with PCIe interface. The driver also only supports driving the mandatory 3.3v and optional 1.8v power supplies. The optional signals of the Key M connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 7 ++ drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 160 ++++++++++++++++++++++++++= ++++ 4 files changed, 176 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..9b3f689d1f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20474,6 +20474,13 @@ F: Documentation/driver-api/pwrseq.rst F: drivers/power/sequencing/ F: include/linux/pwrseq/ =20 +PCIE M.2 POWER SEQUENCING +M: Manivannan Sadhasivam +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml +F: drivers/power/sequencing/pwrseq-pcie-m2.c + POWER STATE COORDINATION INTERFACE (PSCI) M: Mark Rutland M: Lorenzo Pieralisi diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 280f92beb5d0..f5fff84566ba 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU GPU. This driver handles the complex clock and reset sequence required to power on the Imagination BXM GPU on this platform. =20 +config POWER_SEQUENCING_PCIE_M2 + tristate "PCIe M.2 connector power sequencing driver" + depends on OF || COMPILE_TEST + help + Say Y here to enable the power sequencing driver for PCIe M.2 + connectors. This driver handles the power sequencing for the M.2 + connectors exposing multiple interfaces like PCIe, SATA, UART, etc... + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 96c1cf0a98ac..0911d4618298 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -5,3 +5,4 @@ pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o +obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c new file mode 100644 index 000000000000..4835d099d967 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_pcie_m2_pdata { + const struct pwrseq_target_data **targets; +}; + +struct pwrseq_pcie_m2_ctx { + struct pwrseq_device *pwrseq; + struct device_node *of_node; + const struct pwrseq_pcie_m2_pdata *pdata; + struct regulator_bulk_data *regs; + size_t num_vregs; + struct notifier_block nb; +}; + +static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_enable(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_disable(ctx->num_vregs, ctx->regs); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { + .name =3D "regulators-enable", + .enable =3D pwrseq_pcie_m2_m_vregs_enable, + .disable =3D pwrseq_pcie_m2_m_vregs_disable, +}; + +static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { + &pwrseq_pcie_m2_vregs_unit_data, + NULL +}; + +static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_m_unit_deps, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, +}; + +static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { + &pwrseq_pcie_m2_m_pcie_target_data, + NULL +}; + +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { + .targets =3D pwrseq_pcie_m2_m_targets, +}; + +static int pwrseq_pcie_m2_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + struct device_node *endpoint __free(device_node) =3D NULL; + + /* + * Traverse the 'remote-endpoint' nodes and check if the remote node's + * parent matches the OF node of 'dev'. + */ + for_each_endpoint_of_node(ctx->of_node, endpoint) { + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_port_parent(endpoint); + if (remote && (remote =3D=3D dev_of_node(dev))) + return PWRSEQ_MATCH_OK; + } + + return PWRSEQ_NO_MATCH; +} + +static int pwrseq_pcie_m2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwrseq_pcie_m2_ctx *ctx; + struct pwrseq_config config =3D {}; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->of_node =3D dev_of_node(dev); + ctx->pdata =3D device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + /* + * Currently, of_regulator_bulk_get_all() is the only regulator API that + * allows to get all supplies in the devicetree node without manually + * specifying them. + */ + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + ctx->num_vregs =3D ret; + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_pcie_m2_match; + config.targets =3D ctx->pdata->targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) { + regulator_bulk_free(ctx->num_vregs, ctx->regs); + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register the power sequencer\n"); + } + + return 0; +} + +static const struct of_device_id pwrseq_pcie_m2_of_match[] =3D { + { + .compatible =3D "pcie-m2-m-connector", + .data =3D &pwrseq_pcie_m2_m_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); + +static struct platform_driver pwrseq_pcie_m2_driver =3D { + .driver =3D { + .name =3D "pwrseq-pcie-m2", + .of_match_table =3D pwrseq_pcie_m2_of_match, + }, + .probe =3D pwrseq_pcie_m2_probe, +}; +module_platform_driver(pwrseq_pcie_m2_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Power Sequencing driver for PCIe M.2 connector"); +MODULE_LICENSE("GPL"); --=20 2.48.1