From nobody Tue Dec 2 00:45:23 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEDC27C866; Tue, 25 Nov 2025 16:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087469; cv=none; b=ixWt0nkq0+tFrOTEXrAt0se9vuD03JSLjV1YhXLITs1NZ15s1lKw/WP5/cLc7qEkMeGBobjQ7zzAZjK0Kc+dGNLixSP1C4phYiTkyXic5hCdrmsJR8AR0YgvYj0nzp7pbiHNW0ypmjm16ZX/zLuslHViQEWK/fTEd+eC2kdkRBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087469; c=relaxed/simple; bh=pR1IE4WebbzH89QX1WykiV6Po5ZL5j65/b5UxVLzG/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=t/Dmy6k0nOgDA2K8/YfXx6pmDNPPjO45CBF5Hd0bfDGTaabjGZ1U0n442Jqz21ZpKKSpqpmkxkI1DnzCuROlfgaqlDwIYSqar+bDes1oC2fnXRQwXBD/IxO7vJJ1Bxs0VG40kSzBF+/vSqUgYDZTzJhlC8/fcv917kAu9DOznfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GeBngakk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GeBngakk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764087466; bh=pR1IE4WebbzH89QX1WykiV6Po5ZL5j65/b5UxVLzG/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GeBngakkvWJ1zzP8mgVBCsyzM2g5WXE5pnyXv0DxwVAQh5zsjnMx3HpgRrTfCYLEt hJonBqugh3TBc7W0crUvjnVgwem67GuoGtnYZe8vAywzwerx3Vv96CZwJ7HhkfLVxR uTto6R3FEB/eDEcaidUjtprwNQ8jgaq1zDp1LQPbG0KCjDpPFx+0K862jMkFVzFec7 qw0NTw0CJThdt3R0z3b9x8TjNMcO4gNU5k6V0jtcFBazQFeAGNG23EA8lguNy+Iwdd Pbq7+PwSarl2xnR0Y89u/lNP36uS4M+N6frS4dKTrfAFuMt6h456Fbl7FN6rEo9mhG Uap2bKtN5ptfg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:feae:4183:be92:e051]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id C434D17E13CD; Tue, 25 Nov 2025 17:17:44 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 6/8] thermal/drivers/mediatek/lvts: Support MSR offset for 16-bit calibration data Date: Tue, 25 Nov 2025 17:16:56 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-6-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On MT8196/MT6991, per-sensor calibration data read from eFuses is 16-bit. When the LVTS controller operates in 16-bit mode, a fixed offset must be added to MSR values during post-processing to obtain correct temperature readings. Introduce a new msr_offset field in lvts_data, program the respective register and apply the offset to the calibration data read from eFuses. Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index b53d6a4a7474..93eb62cae512 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,7 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSROFT(__base) (__base + 0x006C) #define LVTS_ATP0(__base) (__base + 0x0070) #define LVTS_ATP1(__base) (__base + 0x0074) #define LVTS_ATP2(__base) (__base + 0x0078) @@ -151,6 +152,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + u16 msr_offset; }; =20 struct lvts_sensor { @@ -219,6 +221,7 @@ static const struct debugfs_reg32 lvts_regs[] =3D { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSROFT), LVTS_DEBUG_FS_REGS(LVTS_ATP0), LVTS_DEBUG_FS_REGS(LVTS_ATP1), LVTS_DEBUG_FS_REGS(LVTS_ATP2), @@ -811,6 +814,8 @@ static int lvts_calibration_init(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl =20 if (gt) { lvts_ctrl->calibration[i] =3D calib; + if (lvts_ctrl->lvts_data->msr_offset) + lvts_ctrl->calibration[i] +=3D lvts_ctrl->lvts_data->msr_offset; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] =3D lvts_ctrl->lvts_data->def_calibration; } else { @@ -1118,6 +1123,17 @@ static int lvts_ctrl_calibrate(struct device *dev, s= truct lvts_ctrl *lvts_ctrl) for (i =3D 0; i < LVTS_SENSOR_MAX; i++) writel(lvts_ctrl->calibration[i], lvts_edata[i]); =20 + /* LVTS_MSROFT : Constant offset applied to MSR values + * for post-processing + * + * Bits: + * + * 20-0 : Constant data added to MSR values + */ + if (lvts_ctrl->lvts_data->msr_offset) + writel(lvts_ctrl->lvts_data->msr_offset, + LVTS_MSROFT(lvts_ctrl->base)); + return 0; } =20 --=20 2.39.5