From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6424278F51; Tue, 25 Nov 2025 16:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087462; cv=none; b=bVMN2KOQVrUqQbN9Y8BmbFUSyLXNdycHnR10DhxWtaV0kpAukfb621W9DOBuTiwp29skH2xKFoMm5cMpzptnw0BI6Z+lf0KbRBxGks4jJd6Ac6Z5xKeyfKC9zWEYkUs4G7528rjcINrSsq15rjAkU/v2QH5FTFWnCI4wqWFh7uI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087462; c=relaxed/simple; bh=wA3DIGO1oIoEB6lNDjSI7psqvT6nGHbhXESVUEEIA40=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=E977kscWI59dMDtoXDqCf1nq6yOpazGTTpE0y7JLQ5l7TdmpqE/OKxSjaCX9O8YiqdNy6IQJMYwoxYkRvrzUiOnMjjVMzGB2de60IILHCylLQkUWtIlGH0zaNjZBzyBtg1UPcix7M8sCxgPlRwchn6RL5UigKHTSXqvhdWLlBwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=iNbRyOAM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="iNbRyOAM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764087458; bh=wA3DIGO1oIoEB6lNDjSI7psqvT6nGHbhXESVUEEIA40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iNbRyOAMQh38tdj75MP0NNuwgPM8OdZVrXIskWaix9m9LTcbMoSKWus+lfLXECudS iKtiMhfbnWwOOXUrr8iKMX/g4X1O48GtPwGhDSC30hFinVJpEMBLkbjeV30l7/9bP5 yK7uzzrh7jZ1WxndSqto7igFVH5oq/lBDDEmsAPGmPI/lliqSX2mH2uSKUSFPqjmZe gLNb7domjMX7y/4Qys0e4ShVAf+a8Zxvyda2RC9uW8ipBCTudGO0TIP/2gdMmcqJQ3 qjWiHVouKt6t9mDJs/uGhgI1pWfKck+xA56Qi3jxV1w6liOSDMfNxgl5LWwbrzra5j ROD0U3DkwMLcA== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:feae:4183:be92:e051]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0159C17E10E7; Tue, 25 Nov 2025 17:17:36 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao , Krzysztof Kozlowski Subject: [PATCH v5 1/8] dt-bindings: thermal: mediatek: Add LVTS thermal controller support for MT8196 Date: Tue, 25 Nov 2025 17:16:51 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-1-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add LVTS thermal controller binding for MediaTek MT8196. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- .../bindings/thermal/mediatek,lvts-thermal.yaml | 2 ++ .../dt-bindings/thermal/mediatek,lvts-thermal.h | 26 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-therma= l.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.ya= ml index 0259cd3ce9c5..beccdabe110b 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -26,6 +26,8 @@ properties: - mediatek,mt8192-lvts-mcu - mediatek,mt8195-lvts-ap - mediatek,mt8195-lvts-mcu + - mediatek,mt8196-lvts-ap + - mediatek,mt8196-lvts-mcu =20 reg: maxItems: 1 diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index ddc7302a510a..0ec8ad184d47 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -80,4 +80,30 @@ #define MT8192_AP_MD1 15 #define MT8192_AP_MD2 16 =20 +#define MT8196_MCU_MEDIUM_CPU6_0 0 +#define MT8196_MCU_MEDIUM_CPU6_1 1 +#define MT8196_MCU_DSU2 2 +#define MT8196_MCU_DSU3 3 +#define MT8196_MCU_LITTLE_CPU3 4 +#define MT8196_MCU_LITTLE_CPU0 5 +#define MT8196_MCU_LITTLE_CPU1 6 +#define MT8196_MCU_LITTLE_CPU2 7 +#define MT8196_MCU_MEDIUM_CPU4_0 8 +#define MT8196_MCU_MEDIUM_CPU4_1 9 +#define MT8196_MCU_MEDIUM_CPU5_0 10 +#define MT8196_MCU_MEDIUM_CPU5_1 11 +#define MT8196_MCU_DSU0 12 +#define MT8196_MCU_DSU1 13 +#define MT8196_MCU_BIG_CPU7_0 14 +#define MT8196_MCU_BIG_CPU7_1 15 + +#define MT8196_AP_TOP0 0 +#define MT8196_AP_TOP1 1 +#define MT8196_AP_TOP2 2 +#define MT8196_AP_TOP3 3 +#define MT8196_AP_BOT0 4 +#define MT8196_AP_BOT1 5 +#define MT8196_AP_BOT2 6 +#define MT8196_AP_BOT3 7 + #endif /* __MEDIATEK_LVTS_DT_H */ --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBCF924397A; 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Tue, 25 Nov 2025 17:17:38 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 2/8] thermal/drivers/mediatek/lvts: Make number of calibration offsets configurable Date: Tue, 25 Nov 2025 17:16:52 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-2-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MT8196/MT6991 use 2-byte eFuse calibration data, whereas other SoCs supported by the driver rely on 3 bytes. Make the number of calibration bytes per sensor configurable, enabling support for SoCs with varying calibration formats. Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 55 ++++++++++++++++++++++++++---= ---- 1 file changed, 44 insertions(+), 11 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index ab55b20cda47..babffdea9a4d 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -96,12 +96,15 @@ =20 #define LVTS_MINIMUM_THRESHOLD 20000 =20 +#define LVTS_MAX_CAL_OFFSETS 3 +#define LVTS_NUM_CAL_OFFSETS_MT7988 3 + static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 struct lvts_sensor_data { int dt_id; - u8 cal_offsets[3]; + u8 cal_offsets[LVTS_MAX_CAL_OFFSETS]; }; =20 struct lvts_ctrl_data { @@ -127,6 +130,7 @@ struct lvts_data { const struct lvts_ctrl_data *lvts_ctrl; const u32 *conn_cmd; const u32 *init_cmd; + int num_cal_offsets; int num_lvts_ctrl; int num_conn_cmd; int num_init_cmd; @@ -646,6 +650,26 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, return 0; } =20 +static int lvts_decode_sensor_calibration(const struct lvts_sensor_data *s= ensor, + const u8 *efuse_calibration, u32 calib_len, + u8 num_offsets, u32 *calib) +{ + int i; + u32 calib_val =3D 0; + + for (i =3D 0; i < num_offsets; i++) { + u8 offset =3D sensor->cal_offsets[i]; + + if (offset >=3D calib_len) + return -EINVAL; + // Pack each calibration byte into the correct position + calib_val |=3D efuse_calibration[offset] << (8 * i); + } + + *calib =3D calib_val; + return 0; +} + /* * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: @@ -711,26 +735,27 @@ static int lvts_calibration_init(struct device *dev, = struct lvts_ctrl *lvts_ctrl u8 *efuse_calibration, size_t calib_len) { - int i; + const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; + int i, ret; u32 gt; =20 /* A zero value for gt means that device has invalid efuse data */ - gt =3D (((u32 *)efuse_calibration)[0] >> lvts_ctrl->lvts_data->gt_calib_b= it_offset) & 0xff; + gt =3D (((u32 *)efuse_calibration)[0] >> lvts_data->gt_calib_bit_offset) = & 0xff; =20 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { const struct lvts_sensor_data *sensor =3D &lvts_ctrl_data->lvts_sensor[i]; + u32 calib =3D 0; =20 - if (sensor->cal_offsets[0] >=3D calib_len || - sensor->cal_offsets[1] >=3D calib_len || - sensor->cal_offsets[2] >=3D calib_len) - return -EINVAL; + ret =3D lvts_decode_sensor_calibration(sensor, efuse_calibration, + calib_len, + lvts_data->num_cal_offsets, + &calib); + if (ret) + return ret; =20 if (gt) { - lvts_ctrl->calibration[i] =3D - (efuse_calibration[sensor->cal_offsets[0]] << 0) + - (efuse_calibration[sensor->cal_offsets[1]] << 8) + - (efuse_calibration[sensor->cal_offsets[2]] << 16); + lvts_ctrl->calibration[i] =3D calib; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] =3D lvts_ctrl->lvts_data->def_calibration; } else { @@ -1763,6 +1788,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8186_lvts_data =3D { @@ -1776,6 +1802,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { @@ -1789,6 +1816,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8188_lvts_ap_data =3D { @@ -1802,6 +1830,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { @@ -1815,6 +1844,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8192_lvts_ap_data =3D { @@ -1828,6 +1858,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { @@ -1841,6 +1872,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; =20 static const struct lvts_data mt8195_lvts_ap_data =3D { @@ -1854,6 +1886,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, }; 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Tue, 25 Nov 2025 17:17:40 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 3/8] thermal/drivers/mediatek/lvts: Add platform ops to support alternative conversion logic Date: Tue, 25 Nov 2025 17:16:53 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-3-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introduce lvts_platform_ops struct to support SoC-specific versions of lvts_raw_to_temp() and lvts_temp_to_raw() conversion functions. This is in preparation for supporting SoCs like MT8196/MT6991, which require a different lvts_temp_to_raw() implementation. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 39 ++++++++++++++++++++++++++++-= ---- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index babffdea9a4d..a684f73d3698 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -126,8 +126,14 @@ struct lvts_ctrl_data { continue; \ else =20 +struct lvts_platform_ops { + int (*lvts_raw_to_temp)(u32 raw_temp, int temp_factor); + u32 (*lvts_temp_to_raw)(int temperature, int temp_factor); +}; + struct lvts_data { const struct lvts_ctrl_data *lvts_ctrl; + const struct lvts_platform_ops *ops; const u32 *conn_cmd; const u32 *init_cmd; int num_cal_offsets; @@ -273,7 +279,17 @@ static inline int lvts_debugfs_init(struct device *dev, =20 #endif =20 -static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) +static int lvts_raw_to_temp(u32 raw_temp, const struct lvts_data *lvts_dat= a) +{ + return lvts_data->ops->lvts_raw_to_temp(raw_temp & 0xFFFF, lvts_data->tem= p_factor); +} + +static u32 lvts_temp_to_raw(int temperature, const struct lvts_data *lvts_= data) +{ + return lvts_data->ops->lvts_temp_to_raw(temperature, lvts_data->temp_fact= or); +} + +static int lvts_raw_to_temp_mt7988(u32 raw_temp, int temp_factor) { int temperature; =20 @@ -283,7 +299,7 @@ static int lvts_raw_to_temp(u32 raw_temp, int temp_fact= or) return temperature; } =20 -static u32 lvts_temp_to_raw(int temperature, int temp_factor) +static u32 lvts_temp_to_raw_mt7988(int temperature, int temp_factor) { u32 raw_temp =3D ((s64)(golden_temp_offset - temperature)) << 14; =20 @@ -330,7 +346,7 @@ static int lvts_get_temp(struct thermal_zone_device *tz= , int *temp) if (rc) return -EAGAIN; =20 - *temp =3D lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); + *temp =3D lvts_raw_to_temp(value, lvts_data); =20 return 0; } @@ -400,8 +416,8 @@ static int lvts_set_trips(struct thermal_zone_device *t= z, int low, int high) const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; void __iomem *base =3D lvts_sensor->base; u32 raw_low =3D lvts_temp_to_raw(low !=3D -INT_MAX ? low : LVTS_MINIMUM_T= HRESHOLD, - lvts_data->temp_factor); - u32 raw_high =3D lvts_temp_to_raw(high, lvts_data->temp_factor); + lvts_data); + u32 raw_high =3D lvts_temp_to_raw(high, lvts_data); bool should_update_thresh; =20 lvts_sensor->low_thresh =3D low; @@ -1778,6 +1794,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_platform_ops lvts_platform_ops_mt7988 =3D { + .lvts_raw_to_temp =3D lvts_raw_to_temp_mt7988, + .lvts_temp_to_raw =3D lvts_temp_to_raw_mt7988, +}; + static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, .conn_cmd =3D mt7988_conn_cmds, @@ -1789,6 +1810,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8186_lvts_data =3D { @@ -1803,6 +1825,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { @@ -1817,6 +1840,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8188_lvts_ap_data =3D { @@ -1831,6 +1855,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { @@ -1845,6 +1870,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8192_lvts_ap_data =3D { @@ -1859,6 +1885,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { @@ -1873,6 +1900,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct lvts_data mt8195_lvts_ap_data =3D { @@ -1887,6 +1915,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT7988, + .ops =3D &lvts_platform_ops_mt7988, }; =20 static const struct of_device_id lvts_of_match[] =3D { --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A3B626F2AD; Tue, 25 Nov 2025 16:17:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 25 Nov 2025 17:17:41 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 4/8] thermal/drivers/mediatek/lvts: Add lvts_temp_to_raw variant Date: Tue, 25 Nov 2025 17:16:54 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-4-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MT8196/MT6991 require a different version of lvts_temp_to_raw(), specifically the multiplicative inverse of the existing implementation. Introduce a variant of the function with inverted calculation logic to match this requirement. This ensures accurate raw value generation for temperature thresholds, avoiding spurious thermal interrupts or unintended hardware resets on MT8196/MT6991. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index a684f73d3698..e9b9c1c35020 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -308,6 +308,15 @@ static u32 lvts_temp_to_raw_mt7988(int temperature, in= t temp_factor) return raw_temp; } =20 +static u32 lvts_temp_to_raw_mt8196(int temperature, int temp_factor) +{ + u32 raw_temp; + + raw_temp =3D temperature - golden_temp_offset; + + return div_s64((s64)temp_factor << 14, raw_temp); +} + static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) { struct lvts_sensor *lvts_sensor =3D thermal_zone_device_priv(tz); --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 309862773D3; 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Tue, 25 Nov 2025 17:17:43 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 5/8] thermal/drivers/mediatek/lvts: Add support for ATP mode Date: Tue, 25 Nov 2025 17:16:55 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-5-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MT8196/MT6991 uses ATP (Abnormal Temperature Prevention) mode to detect abnormal temperature conditions, which involves reading temperature data from a dedicated set of registers separate from the ones used for immediate and filtered modes. Add support for ATP mode and its relative registers to ensure accurate temperature readings and proper thermal management on MT8196/MT6991 devices. While at it, convert mode defines to enum. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 44 +++++++++++++++++++++++++++--= ---- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index e9b9c1c35020..b53d6a4a7474 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,10 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_ATP0(__base) (__base + 0x0070) +#define LVTS_ATP1(__base) (__base + 0x0074) +#define LVTS_ATP2(__base) (__base + 0x0078) +#define LVTS_ATP3(__base) (__base + 0x007C) #define LVTS_MSR0(__base) (__base + 0x0090) #define LVTS_MSR1(__base) (__base + 0x0094) #define LVTS_MSR2(__base) (__base + 0x0098) @@ -88,9 +92,6 @@ #define LVTS_COEFF_A_MT7988 -204650 #define LVTS_COEFF_B_MT7988 204650 =20 -#define LVTS_MSR_IMMEDIATE_MODE 0 -#define LVTS_MSR_FILTERED_MODE 1 - #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) =20 @@ -102,6 +103,12 @@ static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 +enum lvts_msr_mode { + LVTS_MSR_IMMEDIATE_MODE, + LVTS_MSR_FILTERED_MODE, + LVTS_MSR_ATP_MODE, +}; + struct lvts_sensor_data { int dt_id; u8 cal_offsets[LVTS_MAX_CAL_OFFSETS]; @@ -111,7 +118,7 @@ struct lvts_ctrl_data { struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; u8 valid_sensor_mask; int offset; - int mode; + enum lvts_msr_mode mode; }; =20 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \ @@ -212,6 +219,10 @@ static const struct debugfs_reg32 lvts_regs[] =3D { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_ATP0), + LVTS_DEBUG_FS_REGS(LVTS_ATP1), + LVTS_DEBUG_FS_REGS(LVTS_ATP2), + LVTS_DEBUG_FS_REGS(LVTS_ATP3), LVTS_DEBUG_FS_REGS(LVTS_MSR0), LVTS_DEBUG_FS_REGS(LVTS_MSR1), LVTS_DEBUG_FS_REGS(LVTS_MSR2), @@ -628,6 +639,13 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, LVTS_IMMD3(lvts_ctrl->base) }; =20 + void __iomem *atp_regs[] =3D { + LVTS_ATP0(lvts_ctrl->base), + LVTS_ATP1(lvts_ctrl->base), + LVTS_ATP2(lvts_ctrl->base), + LVTS_ATP3(lvts_ctrl->base) + }; + int i; =20 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { @@ -663,8 +681,20 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, /* * Each sensor has its own register address to read from. */ - lvts_sensor[i].msr =3D lvts_ctrl_data->mode =3D=3D LVTS_MSR_IMMEDIATE_MO= DE ? - imm_regs[i] : msr_regs[i]; + switch (lvts_ctrl_data->mode) { + case LVTS_MSR_IMMEDIATE_MODE: + lvts_sensor[i].msr =3D imm_regs[i]; + break; + case LVTS_MSR_FILTERED_MODE: + lvts_sensor[i].msr =3D msr_regs[i]; + break; + case LVTS_MSR_ATP_MODE: + lvts_sensor[i].msr =3D atp_regs[i]; + break; + default: + lvts_sensor[i].msr =3D imm_regs[i]; + break; + } =20 lvts_sensor[i].low_thresh =3D INT_MIN; lvts_sensor[i].high_thresh =3D INT_MIN; @@ -934,7 +964,7 @@ static void lvts_ctrl_monitor_enable(struct device *dev= , struct lvts_ctrl *lvts_ u32 sensor_map =3D 0; int i; =20 - if (lvts_ctrl->mode !=3D LVTS_MSR_FILTERED_MODE) + if (lvts_ctrl->mode =3D=3D LVTS_MSR_IMMEDIATE_MODE) return; =20 if (enable) { --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEDC27C866; Tue, 25 Nov 2025 16:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087469; cv=none; b=ixWt0nkq0+tFrOTEXrAt0se9vuD03JSLjV1YhXLITs1NZ15s1lKw/WP5/cLc7qEkMeGBobjQ7zzAZjK0Kc+dGNLixSP1C4phYiTkyXic5hCdrmsJR8AR0YgvYj0nzp7pbiHNW0ypmjm16ZX/zLuslHViQEWK/fTEd+eC2kdkRBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764087469; c=relaxed/simple; bh=pR1IE4WebbzH89QX1WykiV6Po5ZL5j65/b5UxVLzG/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=t/Dmy6k0nOgDA2K8/YfXx6pmDNPPjO45CBF5Hd0bfDGTaabjGZ1U0n442Jqz21ZpKKSpqpmkxkI1DnzCuROlfgaqlDwIYSqar+bDes1oC2fnXRQwXBD/IxO7vJJ1Bxs0VG40kSzBF+/vSqUgYDZTzJhlC8/fcv917kAu9DOznfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GeBngakk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GeBngakk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764087466; bh=pR1IE4WebbzH89QX1WykiV6Po5ZL5j65/b5UxVLzG/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GeBngakkvWJ1zzP8mgVBCsyzM2g5WXE5pnyXv0DxwVAQh5zsjnMx3HpgRrTfCYLEt hJonBqugh3TBc7W0crUvjnVgwem67GuoGtnYZe8vAywzwerx3Vv96CZwJ7HhkfLVxR uTto6R3FEB/eDEcaidUjtprwNQ8jgaq1zDp1LQPbG0KCjDpPFx+0K862jMkFVzFec7 qw0NTw0CJThdt3R0z3b9x8TjNMcO4gNU5k6V0jtcFBazQFeAGNG23EA8lguNy+Iwdd Pbq7+PwSarl2xnR0Y89u/lNP36uS4M+N6frS4dKTrfAFuMt6h456Fbl7FN6rEo9mhG Uap2bKtN5ptfg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:feae:4183:be92:e051]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id C434D17E13CD; Tue, 25 Nov 2025 17:17:44 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 6/8] thermal/drivers/mediatek/lvts: Support MSR offset for 16-bit calibration data Date: Tue, 25 Nov 2025 17:16:56 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-6-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On MT8196/MT6991, per-sensor calibration data read from eFuses is 16-bit. When the LVTS controller operates in 16-bit mode, a fixed offset must be added to MSR values during post-processing to obtain correct temperature readings. Introduce a new msr_offset field in lvts_data, program the respective register and apply the offset to the calibration data read from eFuses. Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index b53d6a4a7474..93eb62cae512 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,7 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSROFT(__base) (__base + 0x006C) #define LVTS_ATP0(__base) (__base + 0x0070) #define LVTS_ATP1(__base) (__base + 0x0074) #define LVTS_ATP2(__base) (__base + 0x0078) @@ -151,6 +152,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + u16 msr_offset; }; =20 struct lvts_sensor { @@ -219,6 +221,7 @@ static const struct debugfs_reg32 lvts_regs[] =3D { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSROFT), LVTS_DEBUG_FS_REGS(LVTS_ATP0), LVTS_DEBUG_FS_REGS(LVTS_ATP1), LVTS_DEBUG_FS_REGS(LVTS_ATP2), @@ -811,6 +814,8 @@ static int lvts_calibration_init(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl =20 if (gt) { lvts_ctrl->calibration[i] =3D calib; + if (lvts_ctrl->lvts_data->msr_offset) + lvts_ctrl->calibration[i] +=3D lvts_ctrl->lvts_data->msr_offset; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] =3D lvts_ctrl->lvts_data->def_calibration; } else { @@ -1118,6 +1123,17 @@ static int lvts_ctrl_calibrate(struct device *dev, s= truct lvts_ctrl *lvts_ctrl) for (i =3D 0; i < LVTS_SENSOR_MAX; i++) writel(lvts_ctrl->calibration[i], lvts_edata[i]); =20 + /* LVTS_MSROFT : Constant offset applied to MSR values + * for post-processing + * + * Bits: + * + * 20-0 : Constant data added to MSR values + */ + if (lvts_ctrl->lvts_data->msr_offset) + writel(lvts_ctrl->lvts_data->msr_offset, + LVTS_MSROFT(lvts_ctrl->base)); + return 0; } =20 --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1066525CC6C; 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Tue, 25 Nov 2025 17:17:46 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 7/8] thermal/drivers/mediatek/lvts_thermal: Add MT8196 support Date: Tue, 25 Nov 2025 17:16:57 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-7-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add LVTS driver support for MT8196. Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- drivers/thermal/mediatek/lvts_thermal.c | 165 ++++++++++++++++++++++++++++= ++++ 1 file changed, 165 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 93eb62cae512..cb68494f086c 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -92,6 +92,10 @@ #define LVTS_COEFF_B_MT8195 250460 #define LVTS_COEFF_A_MT7988 -204650 #define LVTS_COEFF_B_MT7988 204650 +#define LVTS_COEFF_A_MT8196 391460 +#define LVTS_COEFF_B_MT8196 -391460 + +#define LVTS_MSR_OFFSET_MT8196 -984 =20 #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) @@ -100,6 +104,7 @@ =20 #define LVTS_MAX_CAL_OFFSETS 3 #define LVTS_NUM_CAL_OFFSETS_MT7988 3 +#define LVTS_NUM_CAL_OFFSETS_MT8196 2 =20 static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; @@ -784,6 +789,39 @@ static int lvts_decode_sensor_calibration(const struct= lvts_sensor_data *sensor, * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * + * MT8196 : + * Stream index map for MCU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B + * + * <-sensor#5--> <-sensor#4--> <-sensor#7--> <-sensor#6--> + * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 + * + * <-sensor#9--> <-sensor#8--> <-sensor#11-> <-sensor#10-> + * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0X1B + * + * <-sensor#13-> <-sensor#12-> <-sensor#15-> <-sensor#14-> + * 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 + * + * Stream index map for APU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B + * + * Stream index map for GPU Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> + * 0x2C | 0x2D | 0x2E | 0x2F + * + * Stream index map for AP Domain mt8196 : + * + * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2--> + * 0x30 | 0x31 | 0x32 | 0x33 | 0x34 | 0x35 | 0x36 | 0x37 + * + * <-sensor#5--> <-sensor#4--> <-sensor#6--> <-sensor#7--> + * 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F + * * Note: In some cases, values don't strictly follow a little endian order= ing. * The data description gives byte offsets constituting each calibration v= alue * for each sensor. @@ -1849,11 +1887,112 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_= data_ctrl[] =3D { } }; =20 +static const struct lvts_ctrl_data mt8196_lvts_mcu_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_MEDIUM_CPU6_0, + .cal_offsets =3D { 0x06, 0x07 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU6_1, + .cal_offsets =3D { 0x04, 0x05 } }, + { .dt_id =3D MT8196_MCU_DSU2, + .cal_offsets =3D { 0x0A, 0x0B } }, + { .dt_id =3D MT8196_MCU_DSU3, + .cal_offsets =3D { 0x08, 0x09 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_LITTLE_CPU3, + .cal_offsets =3D { 0x0E, 0x0F } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU0, + .cal_offsets =3D { 0x0C, 0x0D } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU1, + .cal_offsets =3D { 0x12, 0x13 } }, + { .dt_id =3D MT8196_MCU_LITTLE_CPU2, + .cal_offsets =3D { 0x10, 0x11 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x100, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_MEDIUM_CPU4_0, + .cal_offsets =3D { 0x16, 0x17 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU4_1, + .cal_offsets =3D { 0x14, 0x15 } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU5_0, + .cal_offsets =3D { 0x1A, 0x1B } }, + { .dt_id =3D MT8196_MCU_MEDIUM_CPU5_1, + .cal_offsets =3D { 0x18, 0x19 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x200, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_MCU_DSU0, + .cal_offsets =3D { 0x1E, 0x1F } }, + { .dt_id =3D MT8196_MCU_DSU1, + .cal_offsets =3D { 0x1C, 0x1D } }, + { .dt_id =3D MT8196_MCU_BIG_CPU7_0, + .cal_offsets =3D { 0x22, 0x23 } }, + { .dt_id =3D MT8196_MCU_BIG_CPU7_1, + .cal_offsets =3D { 0x20, 0x21 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x300, + .mode =3D LVTS_MSR_ATP_MODE, + } +}; + +static const struct lvts_ctrl_data mt8196_lvts_ap_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_AP_TOP0, + .cal_offsets =3D { 0x32, 0x33 } }, + { .dt_id =3D MT8196_AP_TOP1, + .cal_offsets =3D { 0x30, 0x31 } }, + { .dt_id =3D MT8196_AP_TOP2, + .cal_offsets =3D { 0x36, 0x37 } }, + { .dt_id =3D MT8196_AP_TOP3, + .cal_offsets =3D { 0x34, 0x35 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + .mode =3D LVTS_MSR_ATP_MODE, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8196_AP_BOT0, + .cal_offsets =3D { 0x3A, 0x3B } }, + { .dt_id =3D MT8196_AP_BOT1, + .cal_offsets =3D { 0x38, 0x39 } }, + { .dt_id =3D MT8196_AP_BOT2, + .cal_offsets =3D { 0x3E, 0x3F } }, + { .dt_id =3D MT8196_AP_BOT3, + .cal_offsets =3D { 0x3C, 0x3D } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x100, + .mode =3D LVTS_MSR_ATP_MODE, + } +}; + static const struct lvts_platform_ops lvts_platform_ops_mt7988 =3D { .lvts_raw_to_temp =3D lvts_raw_to_temp_mt7988, .lvts_temp_to_raw =3D lvts_temp_to_raw_mt7988, }; =20 +static const struct lvts_platform_ops lvts_platform_ops_mt8196 =3D { + .lvts_raw_to_temp =3D lvts_raw_to_temp_mt7988, + .lvts_temp_to_raw =3D lvts_temp_to_raw_mt8196, +}; + static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, .conn_cmd =3D mt7988_conn_cmds, @@ -1973,6 +2112,30 @@ static const struct lvts_data mt8195_lvts_ap_data = =3D { .ops =3D &lvts_platform_ops_mt7988, }; =20 +static const struct lvts_data mt8196_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8196_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8196_lvts_mcu_data_ctrl), + .temp_factor =3D LVTS_COEFF_A_MT8196, + .temp_offset =3D LVTS_COEFF_B_MT8196, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 14437, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT8196, + .msr_offset =3D LVTS_MSR_OFFSET_MT8196, + .ops =3D &lvts_platform_ops_mt8196, +}; + +static const struct lvts_data mt8196_lvts_ap_data =3D { + .lvts_ctrl =3D mt8196_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8196_lvts_ap_data_ctrl), + .temp_factor =3D LVTS_COEFF_A_MT8196, + .temp_offset =3D LVTS_COEFF_B_MT8196, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 14437, + .num_cal_offsets =3D LVTS_NUM_CAL_OFFSETS_MT8196, + .msr_offset =3D LVTS_MSR_OFFSET_MT8196, + .ops =3D &lvts_platform_ops_mt8196, +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt7988-lvts-ap", .data =3D &mt7988_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8186-lvts", .data =3D &mt8186_lvts_data }, @@ -1982,6 +2145,8 @@ static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta }, + { .compatible =3D "mediatek,mt8196-lvts-mcu", .data =3D &mt8196_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8196-lvts-ap", .data =3D &mt8196_lvts_ap_da= ta }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match); --=20 2.39.5 From nobody Tue Dec 2 00:04:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1562325734; 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Tue, 25 Nov 2025 17:17:47 +0100 (CET) From: Laura Nao To: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: nfraprado@collabora.com, arnd@arndb.de, colin.i.king@gmail.com, u.kleine-koenig@baylibre.com, andrew-ct.chen@mediatek.com, lala.lin@mediatek.com, bchihi@baylibre.com, frank-w@public-files.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, fshao@chromium.org, Laura Nao Subject: [PATCH v5 8/8] dt-bindings: nvmem: mediatek: efuse: Add support for MT8196 Date: Tue, 25 Nov 2025 17:16:58 +0100 Message-Id: <20251125-mt8196-lvts-v4-v5-8-6db7eb903fb7@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> References: <20251125-mt8196-lvts-v4-v5-0-6db7eb903fb7@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The MT8196 eFuse layout is compatible with MT8186 and shares the same decoding scheme for the gpu-speedbin cell. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Tested-by: AngeloGioacchino Del Regno Tested-by: Frank Wunderlich Signed-off-by: Laura Nao --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index c9bf34ee0efb..f9323b3ecfc8 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -28,6 +28,7 @@ properties: - enum: - mediatek,mt8188-efuse - mediatek,mt8189-efuse + - mediatek,mt8196-efuse - const: mediatek,mt8186-efuse - const: mediatek,mt8186-efuse =20 --=20 2.39.5