From nobody Tue Dec 2 00:04:44 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74B712D2391 for ; Tue, 25 Nov 2025 08:22:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764058948; cv=none; b=tuIKwn1kbmurhJNmboub3rcS8c29/1aU1m6xbkH7k8HFcApJhPDJZqrvp+wNx94WtqpkgXmbDdmbSipgAr3Je8ZNCAo5sTF1v2lnWW3bw6zy15gL60riie8pouBpBmzGtzXcn/N217l+0eaxrs6i8BiwhhRW7ysc2Cgd6EIBfv0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764058948; c=relaxed/simple; bh=WB24QFNmXXWomGiUjxHlvGtx4Nh8ZCf8Vo0oBbEPwS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=hk8Qsro1VOzIZjyqZYrt/iOoIi2CmVCPZRcrodooXktSSeDi2TwsW375LkaDAj6aa8SUWqsI2+5+Jkiluz0Ds/R7QHPUu5ZbxaSwuhOTAQXKzo6RN7udUOQom3QeHGWsAHsbvI+eL8lO+XPjJv+7vPPlkhSrd+sI9CFC5o5ECQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=l8SXRchO; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dZQnaPe9; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="l8SXRchO"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dZQnaPe9" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AP2goP01979156 for ; Tue, 25 Nov 2025 08:22:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=YRjpKsqoY99+JF5M3oGMFE Bu2vsC0vfO0ibxsB+T3/Q=; b=l8SXRchOnF7TCQ9kqERONX+G5/lFAuL0hV2Zql thJufKpP9ueAgi1A7JMVX21KIe7GyPlYdQgAzA81R8wzNk4sks/IYV+3JEu2M+sp JVxJfMVEsjQK96f93f5517OmFNr4Uii91jwVhbM+IllVQ5+xaJsITLRnwxZ5hTdY iUmu5IQsK7gHXRhBSdHmKs9kDsig5p77z0BRNovGm5Md8MccPyWqk3Wn/wZ+jrJc UHTh75Nlnq4z03INALaN37cQVgAlVACKkh/JQt+U7swZi3OAwWT93KD6peaWRDFf nzZu/EniSdwOIJ8FpJOYNFV5WwU3zyxUpm4uA5keTNJdrdGg== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4amw9gsuah-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Nov 2025 08:22:25 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8b2e235d4d2so1967237885a.3 for ; Tue, 25 Nov 2025 00:22:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764058944; x=1764663744; darn=vger.kernel.org; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=YRjpKsqoY99+JF5M3oGMFEBu2vsC0vfO0ibxsB+T3/Q=; b=dZQnaPe9m9eMdOw2r3W5HqY3PQ/OMPDTjX1//Tic0KZSKKCzkwoOO1V9/WAvAkfPvc cgqfDlIL/D79MUgrqfOnz0njRTlh9tWp7gHPlx0yUqlleMW52//1oswjo0tPvfAI3ZxF nQCp1OhXkvZDh/5Sk04eGdwJkDUAp0Ksuhnxrlrz7n9Vi0gJlfCLiyw8NUgSK0Zedv2q tvM0VvXBRacpBgJFLZGwqkRWZN4u7AJKYBH5OuUE3AFbA8KMRmnMzYPm2iikKn/2R/y+ xIYl0yWIL212azbJyaeojFPHkW0QJdqlFFIcdLVChewc30k37GGmqDaAoM8ux7n7/MY7 eS7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764058944; x=1764663744; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=YRjpKsqoY99+JF5M3oGMFEBu2vsC0vfO0ibxsB+T3/Q=; b=diercO5hMD33e4y5TyL8ZP1rvSap7EMPu0F0MPdMymUsqZI9SYBeCxTeCw4VKb5GE7 ckcJmep/IBrU4VJhPtASZOQ6WvkgkAd1lm85hnfXlYolXvm9H4YYOdrmPh4JaM4XT3E2 e3cDGsYxnCk4bRT9MKdEic1fD3xzloFa5tac7WideugSzXOXXfcpUsIWQxZfnjJrFSub 6UpNwNeH2lMx5CnI+Yhse47hC91xw7UahW7C3bt7gyaQDVMsKicHIzu+V6Afswi95ADm HTaG5k0lmKdq/2kF0VNxHq1moPDpBCtzTV+jQTcC4sIN3lP9jKREiw3pNxeNBr03PsJa eg4w== X-Forwarded-Encrypted: i=1; AJvYcCXLUITRGeWoYcI5Xa7QTpQ0dnwaDllsJYyLyCjnNFhkbFXgEg0u3UAVlb0EdjdefaXzwQtTLWdkMtsQFsE=@vger.kernel.org X-Gm-Message-State: AOJu0YxZdh5/9dsmxupBaQRnDHd93m6KcxskGr7/ZyCQoBfznn5G8Sr3 ktAv7/hMtN759hWHYfM1Kc1Xq9bvI6xJkSgGVvgKH+1vWH5iS1VELTmjh2uC5znRgk70McqP3ZI eZKEbk7/ubI+eyC7PAfraE/5U0mTEI5W15siwUjzw4RY7McPdYJ46kk7cXi0hO0iq/Ew= X-Gm-Gg: ASbGnctNaLpNiGcyG56dlJGXb2dbLLgJ31sVOxZSbOqOLnnVx7NXlMpv+MpPpRZjq9c RuUv6zYAvhnUO3j6ND68XZpkC/OyjCSVp/oOxrWsFDIm9/n4Jl42upgDG1SLyy3RdZ5ljEAMdyA 7M1EfWPrA++1B1AhACRCkIAyIhmOko/VmlQa18rtAjISIi966ewDLa7YmXO4RUB1s4ts96lUA1P OzdZ4cTHkcjJFjnXdOX1n0U40zoO1Uz0za4dbpDyFyugh4BrC3NZ0DohNHfQQsfrJik0Ji6BIvC Z48yb9QOmvIvmXCkfhZVOuLcXul3gx5rOsc4WONbcVWAyUEbprcfJfanIjZaJY0W6xjtJaGXUv6 joqwBlTilQ+kkPccXpTtCMrzheCsRKxVy9qqMW0knWFIn3J/CGqQZdYcNhikHmda3xs9F/omGWO c= X-Received: by 2002:a05:620a:44ca:b0:8b2:e4f0:74d2 with SMTP id af79cd13be357-8b33d5e0708mr2088684785a.88.1764058944617; Tue, 25 Nov 2025 00:22:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IEgbw5+t2RFxd5vwgHS2/xP58ds7tCi3xfgDuWhOL9/5kLj/9xSxrzjaWShPdduWP/LVNaZPg== X-Received: by 2002:a05:620a:44ca:b0:8b2:e4f0:74d2 with SMTP id af79cd13be357-8b33d5e0708mr2088681185a.88.1764058944092; Tue, 25 Nov 2025 00:22:24 -0800 (PST) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee48d6aab4sm103530771cf.15.2025.11.25.00.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 00:22:23 -0800 (PST) From: Yongxing Mou Date: Tue, 25 Nov 2025 16:22:12 +0800 Subject: [PATCH v4] drm/msm/dp: fix the intf_type of MST interfaces Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-mdss_catalog-v4-1-df651fba2702@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIADNnJWkC/yXM2QrCMBCF4Vcpc20gmS6JfRUpkmWmBuxiUkUof XeDvfwPnG+HTClShr7aIdEn5rjMJZpLBf5h55FEDKUBJbZKYSumkPPd280+l1HUlo027Dr2Dsp lTcTx++duw9mJXu+ibucIzmYSfpmmuPVVFzTp4gZZ89UwdoxEMnBA5Zy0sjHSotIGhuP4AQ+Z2 RuqAAAA X-Change-ID: 20251125-mdss_catalog-3af878fb6fcb To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764058938; l=5994; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=T4+veceh43Iz1HC9uB499V8TtofoUBw/GEaYL11J+pk=; b=gJUYv20WEI5ukHHHm1d/Hca0uVR3M5CdBme19aSpBo0+vWXjKk2qdxhhWSGVE1YlGSQEUNfa7 Leti51tE9+XDypwOYKNC0lxZzQfg/JyqJA4B59QQLLKLiFeZRAHXaDz X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDA2OCBTYWx0ZWRfX6dWQnX7egDtW YvAgybFvxmN1UYLGEVGgRKLKrKos56ctkSFqU3idd282qsGbXgRVRh/ytgX3KtwArcz1pl3w/M2 tP7ilBAYmMc3l8jkcKnyrjJ3ZjdGYomWmhBiHNkqK0/l60p41IUc0IZ6AeURs+yq8GXr0vKtFwF srg1Esl5o5aaGhs/tn+AVdsPXAY8VMsn2QxzbGCUx7oG9IOiLZ1K4c6ITKlZJdCAPwaO7rsz6yZ iPxeMYn+bpuxeSFtwhJf+qTNIlesTnoZG+sT3YO1W/K+Tocoa8OMArAWdpyIyuIZf7OTukrTRmn NVnd01m2ETr+cnQTqratMimo/WFT7RdPzrMzMuC3Mf978BB1+qEj2Zsrxv8ZZbo6kEHPCvJP6// nAjgybcR8zeI9ESisBHKhFGJyNRWsA== X-Authority-Analysis: v=2.4 cv=H53WAuYi c=1 sm=1 tr=0 ts=69256741 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=3SrrOXIG8BVLCHsxiMcA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: zbr35CWDkgepEynVWIm1GTg9c0hEd02w X-Proofpoint-GUID: zbr35CWDkgepEynVWIm1GTg9c0hEd02w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250068 From: Abhinav Kumar Interface type of MST interfaces is currently INTF_NONE. Update this to INTF_DP. And correct the intf_6 intr_underrun/intr_vsync index for dpu_8_4_sa8775p. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- This patch was split out from the MST V3 patch series: https://lore.kernel.org/all/20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualc= omm.com/ --- Changes in v4: - Splite chagne out from the MST V3 series. - Link to v3: https://lore.kernel.org/all/20250825-msm-dp-mst-v3-37-01faacf= cdedd@oss.qualcomm.com/ Changes in v3: - Fix through the whole catalog - Link to v2: https://lore.kernel.org/all/20250609-msm-dp-mst-v2-37-a54d890= 2a23d@quicinc.com/ Changes in v2: - Change the patch order in the series. - Link to v1: https://lore.kernel.org/all/20241205-dp_mst-v1-3-f8618d42a99a= @quicinc.com/ --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 303d33dc7783..ea2329f0b5e9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -319,7 +319,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -351,7 +351,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -359,7 +359,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 0f7b4a224e4c..00fd0c8cc115 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -347,7 +347,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -363,15 +363,15 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, - .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), - .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -379,7 +379,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 7243eebb85f3..826f65adb18b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -367,7 +367,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -375,7 +375,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), --- base-commit: 6d7e7251d03f98f26f2ee0dfd21bb0a0480a2178 change-id: 20251125-mdss_catalog-3af878fb6fcb Best regards, --=20 Yongxing Mou