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Tue, 25 Nov 2025 09:45:36 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29b5b13964dsm174500785ad.38.2025.11.25.09.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 09:45:35 -0800 (PST) From: Taniya Das Date: Tue, 25 Nov 2025 23:15:10 +0530 Subject: [PATCH v2 01/11] clk: qcom: clk-alpha-pll: Update the PLL support for cal_l Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-kaanapali-mmcc-v2-v2-1-fb44e78f300b@oss.qualcomm.com> References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> In-Reply-To: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das , Jingyi Wang , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDE0OCBTYWx0ZWRfX1yeez7QtWG37 ehXRvpN/3PDP/7gmVzv+y0Az/H2uJC/b2ZKQXyqfmDCTey4cFe1bQX+MJl5RRB7w/gEpW/fMWgU QOwcxbEHhC7bEw1Y38FMV0ssnBlNsjNCXCofZ4JslRB/TOwQ5ay5DCPzZBh5Gmj0ThPBCN4n24U jorvYxreislq9x/zXDIRQxMdsNoTnOb47aGxlKSvbFG2Fay5yG6J81fR6geQwY5VWVuAO8Rnu7R N0Bst/xRwlKU57rQuKO8hORl6RwaVApwu5IGWVPwryxX2m1rC0WLKNhGQb4/z5o9g4vG/ayUnxC 560ak86GWOW1hxYNu51TrUQgaiCcRkoL9iJis8kyw== X-Authority-Analysis: v=2.4 cv=RvTI7SmK c=1 sm=1 tr=0 ts=6925eb41 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=QKPxMsH92d9TYhJkRyAA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: 5UKAAjQDf9dBQ3MWnXw03lWdDzgHFag1 X-Proofpoint-GUID: 5UKAAjQDf9dBQ3MWnXw03lWdDzgHFag1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Recent QCOM PLLs require the CAL_L field to be programmed according to specific hardware recommendations, rather than using the legacy default value of 0x44. Hardcoding this value can lead to suboptimal or incorrect behavior on newer platforms. To address this, introduce a `cal_l` field in the PLL configuration structure, allowing CAL_L to be set explicitly based on platform requirements. This improves flexibility and ensures correct PLL initialization across different hardware variants. Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 6 +++++- drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 6aeba40358c11e44c5f39d15f149d62149393cd3..6f50f0c4b984e991982ee8914a4= 96c00c4ee063b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2338,7 +2338,11 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pl= l *pll, struct regmap *regma return; } =20 - lval |=3D TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; + if (config->cal_l) + lval |=3D config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; + else + lval |=3D TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ct= l_val); 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Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index ec5b4e4810300fa787420356bb073c24bb05da62..fc55a42fac2ffe589ba270010eb= 47c0816832ca7 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -28,6 +28,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_PONGO_ELU, + CLK_ALPHA_PLL_TYPE_PONGO_EKO_T =3D CLK_ALPHA_PLL_TYPE_PONGO_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T =3D CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, @@ -207,6 +208,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid= _evo_ops; #define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid= _evo_ops =20 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; +#define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 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Tue, 25 Nov 2025 09:45:48 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29b5b13964dsm174500785ad.38.2025.11.25.09.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 09:45:47 -0800 (PST) From: Taniya Das Date: Tue, 25 Nov 2025 23:15:12 +0530 Subject: [PATCH v2 03/11] clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-kaanapali-mmcc-v2-v2-3-fb44e78f300b@oss.qualcomm.com> References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> In-Reply-To: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das , Jingyi Wang , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=I6tohdgg c=1 sm=1 tr=0 ts=6925eb4d cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fFf9reVGpRxvdFVPZdQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDE0OCBTYWx0ZWRfX4MCiUIUpAsll KbaRD+n3BHabHTgzSkbUGTuSa97rgE91wLteFZQOoqKMldUeBprbdL+ccat3cFNhxtDTs/59qLy Lsu6iDRMvKXMLd6iPfj7IipLmigfgKRFmz246ifuGSxEuBdg6MLIQfoBh42IrebGhnGURxHpmd0 tAHFSX9oXCo868gsvdLr6F/OhNh8DJOjJ8M/KSqd+ArvIzF+YwgEVAIEUdADeOQZtIVI33V+1p0 EiBaqhIkDVOu65DL19XthaTRfVVUrXCjfGpOBPif/PxwcKd0vPOBslhJb84IemXs//S15gyN++4 OmPnSkYhzPKz+xCgab50EFymXMJ4Bf9gz/iywhHbQ== X-Proofpoint-ORIG-GUID: hl9HLNm4l55x-AdhoAMdYya_M1JuhIEf X-Proofpoint-GUID: hl9HLNm4l55x-AdhoAMdYya_M1JuhIEf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Add clock ops for Rivian ELU and EKO_T PLLs, add the register offsets for the Rivian ELU PLL. Since ELU and EKO_T shared the same offsets and PLL ops, reuse the Rivian EKO_T enum. Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 14 ++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 6f50f0c4b984e991982ee8914a496c00c4ee063b..3fbdee6e67f9c82a2b93f2624a1= 12934f01686d5 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -243,6 +243,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_TEST_CTL] =3D 0x28, [PLL_OFF_TEST_CTL_U] =3D 0x2c, }, + [CLK_ALPHA_PLL_TYPE_RIVIAN_ELU] =3D { + [PLL_OFF_OPMODE] =3D 0x04, + [PLL_OFF_STATUS] =3D 0x0c, + [PLL_OFF_L_VAL] =3D 0x10, + [PLL_OFF_USER_CTL] =3D 0x14, + [PLL_OFF_USER_CTL_U] =3D 0x18, + [PLL_OFF_CONFIG_CTL] =3D 0x1c, + [PLL_OFF_CONFIG_CTL_U] =3D 0x20, + [PLL_OFF_CONFIG_CTL_U1] =3D 0x24, + [PLL_OFF_CONFIG_CTL_U2] =3D 0x28, + [PLL_OFF_TEST_CTL] =3D 0x2c, + [PLL_OFF_TEST_CTL_U] =3D 0x30, + }, [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] =3D { [PLL_OFF_L_VAL] =3D 0x04, [PLL_OFF_ALPHA_VAL] =3D 0x08, @@ -3006,6 +3019,7 @@ void qcom_clk_alpha_pll_configure(struct clk_alpha_pl= l *pll, struct regmap *regm clk_taycan_elu_pll_configure(pll, regmap, pll->config); break; case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: + case CLK_ALPHA_PLL_TYPE_RIVIAN_ELU: clk_rivian_evo_pll_configure(pll, regmap, pll->config); break; case CLK_ALPHA_PLL_TYPE_TRION: diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index fc55a42fac2ffe589ba270010eb47c0816832ca7..da7d3d75592373cb2df472b9976= f8c7063dc5021 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -32,6 +32,8 @@ enum { CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T =3D CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_ELU, + CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T =3D CLK_ALPHA_PLL_TYPE_RIVIAN_ELU, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, @@ -210,6 +212,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid= _evo_ops; extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; #define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 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Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 2 + include/dt-bindings/clock/qcom,kaanapali-dispcc.h | 109 +++++++++++++++++= ++++ 2 files changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index 30e4b46315752b93754ab2f946c684e13b06ab93..591ce91b8d54dd6f78a66d02988= 2bcd94b53beda 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -15,6 +15,7 @@ description: | domains on SM8550, SM8650, SM8750 and few other platforms. =20 See also: + - include/dt-bindings/clock/qcom,kaanapali-dispcc.h - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h - include/dt-bindings/clock/qcom,sm8750-dispcc.h @@ -23,6 +24,7 @@ description: | properties: compatible: enum: + - qcom,kaanapali-dispcc - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc diff --git a/include/dt-bindings/clock/qcom,kaanapali-dispcc.h b/include/dt= -bindings/clock/qcom,kaanapali-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..05146f9dfe077a0841c253b7fc0= b6e76347f8e3a --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-dispcc.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H + +/* DISP_CC clocks */ +#define DISP_CC_ESYNC0_CLK 0 +#define DISP_CC_ESYNC0_CLK_SRC 1 +#define DISP_CC_ESYNC1_CLK 2 +#define DISP_CC_ESYNC1_CLK_SRC 3 +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4 +#define DISP_CC_MDSS_AHB1_CLK 5 +#define DISP_CC_MDSS_AHB_CLK 6 +#define DISP_CC_MDSS_AHB_CLK_SRC 7 +#define DISP_CC_MDSS_AHB_SWI_CLK 8 +#define DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE0_CLK 10 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 11 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 12 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 13 +#define DISP_CC_MDSS_BYTE1_CLK 14 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 15 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 17 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 18 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 20 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 21 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 22 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 23 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 24 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 25 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 27 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 28 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 29 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 30 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 31 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 32 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 33 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 34 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 42 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 44 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 45 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 47 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 48 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 49 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 50 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 51 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 52 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 53 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 54 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reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Update the compatible and the bindings for CAMCC support on Kaanapali SoC. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8450-camcc.yaml | 6 + .../clock/qcom,kaanapali-cambistmclkcc.h | 33 +++++ include/dt-bindings/clock/qcom,kaanapali-camcc.h | 147 +++++++++++++++++= ++++ 3 files changed, 186 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index c1e06f39431e68a3cd2f6c2dba84be2a3c143bb1..3ec9bf4d82ad3b0fbb3e58fe312= a416b3580c30c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -15,6 +15,8 @@ description: | domains on SM8450. =20 See also: + include/dt-bindings/clock/qcom,kaanapali-camcc.h + include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -22,6 +24,8 @@ description: | properties: compatible: enum: + - qcom,kaanapali-cambistmclkcc + - qcom,kaanapali-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc @@ -63,6 +67,8 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-cambistmclkcc + - qcom,kaanapali-camcc - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc diff --git a/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h b/inc= lude/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h new file mode 100644 index 0000000000000000000000000000000000000000..ddb083b5289ecc5ddbf9ce0b8af= a5e2b3bd7ccad --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H + +/* CAM_BIST_MCLK_CC clocks */ +#define CAM_BIST_MCLK_CC_DEBUG_CLK 0 +#define CAM_BIST_MCLK_CC_DEBUG_DIV_CLK_SRC 1 +#define CAM_BIST_MCLK_CC_MCLK0_CLK 2 +#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 3 +#define CAM_BIST_MCLK_CC_MCLK1_CLK 4 +#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 5 +#define CAM_BIST_MCLK_CC_MCLK2_CLK 6 +#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 7 +#define CAM_BIST_MCLK_CC_MCLK3_CLK 8 +#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 9 +#define CAM_BIST_MCLK_CC_MCLK4_CLK 10 +#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 11 +#define CAM_BIST_MCLK_CC_MCLK5_CLK 12 +#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 13 +#define CAM_BIST_MCLK_CC_MCLK6_CLK 14 +#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 15 +#define CAM_BIST_MCLK_CC_MCLK7_CLK 16 +#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 17 +#define CAM_BIST_MCLK_CC_PLL0 18 +#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 19 +#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 20 +#define CAM_BIST_MCLK_CC_SLEEP_CLK 21 + +#endif diff --git a/include/dt-bindings/clock/qcom,kaanapali-camcc.h b/include/dt-= bindings/clock/qcom,kaanapali-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..58835136b356a558f001fa8ff74= a42ae698734bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-camcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H + +/* CAM_CC clocks */ +#define CAM_CC_CAM_TOP_AHB_CLK 0 +#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 3 +#define CAM_CC_CAMNOC_NRT_CRE_CLK 4 +#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5 +#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 6 +#define CAM_CC_CAMNOC_RT_AXI_CLK 7 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 8 +#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 9 +#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 10 +#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 11 +#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 12 +#define CAM_CC_CAMNOC_XO_CLK 13 +#define CAM_CC_CCI_0_CLK 14 +#define CAM_CC_CCI_0_CLK_SRC 15 +#define CAM_CC_CCI_1_CLK 16 +#define CAM_CC_CCI_1_CLK_SRC 17 +#define CAM_CC_CCI_2_CLK 18 +#define CAM_CC_CCI_2_CLK_SRC 19 +#define CAM_CC_CORE_AHB_CLK 20 +#define CAM_CC_CPHY_RX_CLK_SRC 21 +#define CAM_CC_CRE_AHB_CLK 22 +#define CAM_CC_CRE_CLK 23 +#define CAM_CC_CRE_CLK_SRC 24 +#define CAM_CC_CSI0PHYTIMER_CLK 25 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSI1PHYTIMER_CLK 27 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 28 +#define CAM_CC_CSI2PHYTIMER_CLK 29 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 30 +#define CAM_CC_CSI3PHYTIMER_CLK 31 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 32 +#define CAM_CC_CSI4PHYTIMER_CLK 33 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 34 +#define CAM_CC_CSI5PHYTIMER_CLK 35 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 36 +#define CAM_CC_CSID_CLK 37 +#define CAM_CC_CSID_CLK_SRC 38 +#define CAM_CC_CSID_CSIPHY_RX_CLK 39 +#define CAM_CC_CSIPHY0_CLK 40 +#define CAM_CC_CSIPHY1_CLK 41 +#define CAM_CC_CSIPHY2_CLK 42 +#define CAM_CC_CSIPHY3_CLK 43 +#define CAM_CC_CSIPHY4_CLK 44 +#define CAM_CC_CSIPHY5_CLK 45 +#define CAM_CC_DRV_AHB_CLK 46 +#define CAM_CC_DRV_XO_CLK 47 +#define CAM_CC_FAST_AHB_CLK_SRC 48 +#define CAM_CC_GDSC_CLK 49 +#define CAM_CC_ICP_0_AHB_CLK 50 +#define CAM_CC_ICP_0_CLK 51 +#define CAM_CC_ICP_0_CLK_SRC 52 +#define CAM_CC_ICP_1_AHB_CLK 53 +#define CAM_CC_ICP_1_CLK 54 +#define CAM_CC_ICP_1_CLK_SRC 55 +#define CAM_CC_IFE_LITE_AHB_CLK 56 +#define CAM_CC_IFE_LITE_CLK 57 +#define CAM_CC_IFE_LITE_CLK_SRC 58 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 59 +#define CAM_CC_IFE_LITE_CSID_CLK 60 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 61 +#define CAM_CC_IPE_NPS_AHB_CLK 62 +#define CAM_CC_IPE_NPS_CLK 63 +#define CAM_CC_IPE_NPS_CLK_SRC 64 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 65 +#define CAM_CC_IPE_PPS_CLK 66 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 67 +#define CAM_CC_JPEG_CLK 68 +#define CAM_CC_JPEG_CLK_SRC 69 +#define CAM_CC_OFE_AHB_CLK 70 +#define CAM_CC_OFE_ANCHOR_CLK 71 +#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 72 +#define CAM_CC_OFE_CLK_SRC 73 +#define CAM_CC_OFE_HDR_CLK 74 +#define CAM_CC_OFE_HDR_FAST_AHB_CLK 75 +#define CAM_CC_OFE_MAIN_CLK 76 +#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 77 +#define CAM_CC_PLL0 78 +#define CAM_CC_PLL0_OUT_EVEN 79 +#define CAM_CC_PLL0_OUT_ODD 80 +#define CAM_CC_PLL1 81 +#define CAM_CC_PLL1_OUT_EVEN 82 +#define CAM_CC_PLL2 83 +#define CAM_CC_PLL2_OUT_EVEN 84 +#define CAM_CC_PLL3 85 +#define CAM_CC_PLL3_OUT_EVEN 86 +#define CAM_CC_PLL4 87 +#define CAM_CC_PLL4_OUT_EVEN 88 +#define CAM_CC_PLL5 89 +#define CAM_CC_PLL5_OUT_EVEN 90 +#define CAM_CC_PLL6 91 +#define CAM_CC_PLL6_OUT_EVEN 92 +#define CAM_CC_PLL6_OUT_ODD 93 +#define CAM_CC_PLL7 94 +#define CAM_CC_PLL7_OUT_EVEN 95 +#define CAM_CC_QDSS_DEBUG_CLK 96 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 97 +#define CAM_CC_QDSS_DEBUG_XO_CLK 98 +#define CAM_CC_SLEEP_CLK 99 +#define CAM_CC_SLOW_AHB_CLK_SRC 100 +#define CAM_CC_TFE_0_BAYER_CLK 101 +#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 102 +#define CAM_CC_TFE_0_CLK_SRC 103 +#define CAM_CC_TFE_0_MAIN_CLK 104 +#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 105 +#define CAM_CC_TFE_1_BAYER_CLK 106 +#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 107 +#define CAM_CC_TFE_1_CLK_SRC 108 +#define CAM_CC_TFE_1_MAIN_CLK 109 +#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 110 +#define CAM_CC_TFE_2_BAYER_CLK 111 +#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 112 +#define CAM_CC_TFE_2_CLK_SRC 113 +#define CAM_CC_TFE_2_MAIN_CLK 114 +#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 115 +#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK 116 +#define CAM_CC_XO_CLK_SRC 117 + +/* CAM_CC power domains */ +#define CAM_CC_IPE_0_GDSC 0 +#define CAM_CC_OFE_GDSC 1 +#define CAM_CC_TFE_0_GDSC 2 +#define CAM_CC_TFE_1_GDSC 3 +#define CAM_CC_TFE_2_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_DRV_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IPE_0_BCR 2 +#define CAM_CC_OFE_BCR 3 +#define CAM_CC_QDSS_DEBUG_BCR 4 +#define CAM_CC_TFE_0_BCR 5 +#define CAM_CC_TFE_1_BCR 6 +#define CAM_CC_TFE_2_BCR 7 + +#endif --=20 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Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ include/dt-bindings/clock/qcom,kaanapali-videocc.h | 58 ++++++++++++++++++= ++++ 2 files changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index b31bd833552937fa896f69966cfe5c79d9cfdd21..e6beebd6a36ee1ce213a816f60d= f8a76fa5c44d6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -15,6 +15,7 @@ description: | domains on SM8450. =20 See also: + include/dt-bindings/clock/qcom,kaanapali-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -22,6 +23,7 @@ description: | properties: compatible: enum: + - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc @@ -61,6 +63,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8550-videocc - qcom,sm8750-videocc diff --git a/include/dt-bindings/clock/qcom,kaanapali-videocc.h b/include/d= t-bindings/clock/qcom,kaanapali-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..cc0d41b895c92e1d0b84067093d= 2d7220c671a91 --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-videocc.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_FREERUN_CLK 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0_VPP0_CLK 6 +#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7 +#define VIDEO_CC_MVS0_VPP1_CLK 8 +#define VIDEO_CC_MVS0_VPP1_FREERUN_CLK 9 +#define VIDEO_CC_MVS0A_CLK 10 +#define VIDEO_CC_MVS0A_CLK_SRC 11 +#define VIDEO_CC_MVS0A_FREERUN_CLK 12 +#define VIDEO_CC_MVS0B_CLK 13 +#define VIDEO_CC_MVS0B_CLK_SRC 14 +#define VIDEO_CC_MVS0B_FREERUN_CLK 15 +#define VIDEO_CC_MVS0C_CLK 16 +#define VIDEO_CC_MVS0C_CLK_SRC 17 +#define VIDEO_CC_MVS0C_FREERUN_CLK 18 +#define VIDEO_CC_MVS0C_SHIFT_CLK 19 +#define VIDEO_CC_PLL0 20 +#define VIDEO_CC_PLL1 21 +#define VIDEO_CC_PLL2 22 +#define VIDEO_CC_PLL3 23 +#define VIDEO_CC_SLEEP_CLK 24 +#define VIDEO_CC_TS_XO_CLK 25 +#define VIDEO_CC_XO_CLK 26 +#define VIDEO_CC_XO_CLK_SRC 27 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0A_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS0_VPP1_GDSC 2 +#define VIDEO_CC_MVS0_VPP0_GDSC 3 +#define VIDEO_CC_MVS0C_GDSC 4 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0_VPP0_BCR 2 +#define VIDEO_CC_MVS0_VPP1_BCR 3 +#define VIDEO_CC_MVS0A_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS0C_BCR 6 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 7 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 8 +#define VIDEO_CC_XO_CLK_ARES 9 + +#endif --=20 2.34.1 From nobody Tue Dec 2 00:04:38 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B77932ED26 for ; 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Signed-off-by: Jingyi Wang Reviewed-by: Bryan O'Donoghue Signed-off-by: Taniya Das --- .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 63 ++++++++++++++++++= ++++ .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + include/dt-bindings/clock/qcom,kaanapali-gpucc.h | 47 ++++++++++++++++ .../dt-bindings/clock/qcom,kaanapali-gxclkctl.h | 12 +++++ 4 files changed, 124 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..31398aec839d88007c9f1de7e1a= 248beae826640 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics power domain Controller on Kaanapali + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics power domain control module provides the power + domains on Qualcomm SoCs. This module exposes the GDSC power domain + which helps the recovery of Graphics subsystem. + + See also:: + include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h + +properties: + compatible: + enum: + - qcom,kaanapali-gxclkctl + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: GFX power domain + - description: GMXC power domain + - description: GPUCC(CX) power domain + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - '#power-domain-cells' + +unevaluatedProperties: false + +examples: + - | + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d68024 { + compatible =3D "qcom,kaanapali-gxclkctl"; + reg =3D <0 0x3d68024 0x0 0x8>; + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc 0>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 44380f6f81368339c2b264bde4d8ad9a23baca72..6feaa32569f9a852c2049fee00e= e7a2e2aefb558 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. =20 See also:: + include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h @@ -26,6 +27,7 @@ description: | properties: compatible: enum: + - qcom,kaanapali-gpucc - qcom,milos-gpucc - qcom,sar2130p-gpucc - qcom,sm4450-gpucc diff --git a/include/dt-bindings/clock/qcom,kaanapali-gpucc.h b/include/dt-= bindings/clock/qcom,kaanapali-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..e8dc2009c71b705b4369a6c8cf8= 3024a18c611d5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-gpucc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DPM_CLK 7 +#define GPU_CC_FF_CLK_SRC 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_GPU_SMMU_VOTE_CLK 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_HUB_AON_CLK 14 +#define GPU_CC_HUB_CLK_SRC 15 +#define GPU_CC_HUB_CX_INT_CLK 16 +#define GPU_CC_HUB_DIV_CLK_SRC 17 +#define GPU_CC_MEMNOC_GFX_CLK 18 +#define GPU_CC_PLL0 19 +#define GPU_CC_PLL0_OUT_EVEN 20 +#define GPU_CC_RSCC_HUB_AON_CLK 21 +#define GPU_CC_RSCC_XO_AON_CLK 22 +#define GPU_CC_SLEEP_CLK 23 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_FF_BCR 3 +#define GPU_CC_GMU_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif diff --git a/include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h b/include/= dt-bindings/clock/qcom,kaanapali-gxclkctl.h new file mode 100644 index 0000000000000000000000000000000000000000..460e21881c4fec46f2b50ccf10f= e504636a52ef1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H + +/* GX_CLKCTL power domains */ +#define GX_CLKCTL_GX_GDSC 0 + +#endif --=20 2.34.1 From nobody Tue Dec 2 00:04:38 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F7A32F74B for ; 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Tue, 25 Nov 2025 09:46:18 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29b5b13964dsm174500785ad.38.2025.11.25.09.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 09:46:17 -0800 (PST) From: Taniya Das Date: Tue, 25 Nov 2025 23:15:17 +0530 Subject: [PATCH v2 08/11] clk: qcom: dispcc: Add support for display clock controller Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251125-kaanapali-mmcc-v2-v2-8-fb44e78f300b@oss.qualcomm.com> References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> In-Reply-To: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=C53kCAP+ c=1 sm=1 tr=0 ts=6925eb6c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=CTeyeF6quU7oAeRjbeoA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI1MDE0OCBTYWx0ZWRfX8Wlhe6YfJuAs vgzrqaH0Z2PMFDpe8uN2jzoJjmGAZJFWDdWlZOoluka1xX5QUbwf/jVabmJzkAbj3jqB1PWKmWq TD1dNwJvoR4albsN9Sz+DXTlRVODVDQ3cinL4zfBPuMGItErYh4qmrc2hReGYGE3z5FM/UsYHq6 abizCkCUDGRMUlgpOenPlFe6/aQzG71MrueRbIshN9ndYUhY7yQJrxBRfGrEWKTiCcc8mVlSgR+ /43p/+w5HgzBw5r/3PAaqOK0E7vhW6VWVQTPg7KcCKw8023OZQq8fJpIkbD3NCQpcQFxQk+qUeZ qhiSF8gEcqHGx9B24VS5u0MYEC7cpH8sO59sIUpAKneQUJ07tXpidIcgd5k1/dX/9BJrEIOSHoW Ia5Itc8jx3F2IZ/M6YjIh35AwKwOjQ== X-Proofpoint-ORIG-GUID: _sD0CK6Pi3XAwzv2FCCHAobj4JbLUjJS X-Proofpoint-GUID: _sD0CK6Pi3XAwzv2FCCHAobj4JbLUjJS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Support the clock controller driver for Kaanapali to enable display SW to be able to control the clocks. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-kaanapali.c | 1956 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 1967 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a284ba040b78ba2f7b7c7ead14023c0ec637f841..e293d1a816c2eece0291e9ee707= 698e97ed75cd8 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -46,6 +46,16 @@ config CLK_GLYMUR_TCSRCC Support for the TCSR clock controller on GLYMUR devices. Say Y if you want to use peripheral devices such as USB/PCIe/EDP. =20 +config CLK_KAANAPALI_DISPCC + tristate "Kaanapali Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_KAANAPALI_GCC + help + Support for the display clock controller on Qualcomm Technologies, Inc + Kaanapali devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0ac8a9055a43230d848c6a0c1ac118c03c3e18d2..98ec8aeb5d5049855bb65f7371a= 10fb2418a468f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o +obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/dispcc-kaanapali.c b/drivers/clk/qcom/dispcc-= kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..baae2ec1f72aac04b265fb62433= c75e9bd425d4d --- /dev/null +++ b/drivers/clk/qcom/dispcc-kaanapali.c @@ -0,0 +1,1956 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +#define DISP_CC_MISC_CMD 0xF000 + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_AHB_CLK, + DT_SLEEP_CLK, + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, + DT_DP1_PHY_PLL_LINK_CLK, + DT_DP1_PHY_PLL_VCO_DIV_CLK, + DT_DP2_PHY_PLL_LINK_CLK, + DT_DP2_PHY_PLL_VCO_DIV_CLK, + DT_DP3_PHY_PLL_LINK_CLK, + DT_DP3_PHY_PLL_VCO_DIV_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DISP_CC_PLL1_OUT_EVEN, + P_DISP_CC_PLL1_OUT_MAIN, + P_DISP_CC_PLL2_OUT_MAIN, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DP1_PHY_PLL_LINK_CLK, + P_DP1_PHY_PLL_VCO_DIV_CLK, + P_DP2_PHY_PLL_LINK_CLK, + P_DP2_PHY_PLL_VCO_DIV_CLK, + P_DP3_PHY_PLL_LINK_CLK, + P_DP3_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, +}; + +static const struct pll_vco pongo_eko_t_vco[] =3D { + { 38400000, 153600000, 0 }, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 257.142858 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0xd, + .cal_l =3D 0x48, + .alpha =3D 0x6492, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &disp_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 300.0 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll1_config =3D { + .l =3D 0xf, + .cal_l =3D 0x48, + .alpha =3D 0xa000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll disp_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &disp_cc_pll1_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 38.4 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll2_config =3D { + .l =3D 0x493, + .cal_l =3D 0x493, + .alpha =3D 0x0, + .config_ctl_val =3D 0x60000f68, + .config_ctl_hi_val =3D 0x0001c808, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x040082f4, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x0080c496, + .test_ctl_hi1_val =3D 0x40100080, + .test_ctl_hi2_val =3D 0x001001bc, + .test_ctl_hi3_val =3D 0x002003d8, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00e50302, +}; + +static struct clk_alpha_pll disp_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &disp_cc_pll2_config, + .vco_table =3D pongo_eko_t_vco, + .num_vco =3D ARRAY_SIZE(pongo_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_SLEEP_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_pongo_eko_t_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DISP_CC_PLL2_OUT_MAIN, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .hw =3D &disp_cc_pll2.clkr.hw }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll1.clkr.hw }, + { .hw =3D &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_9[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .hw =3D &disp_cc_pll1.clkr.hw }, + { .hw =3D &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_10[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL2_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_10[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll2.clkr.hw }, +}; + +static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_esync0_clk_src =3D { + .cmd_rcgr =3D 0x80d4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_esync0_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_esync1_clk_src =3D { + .cmd_rcgr =3D 0x80ec, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_esync1_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(120000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(165000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(200000000, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(233333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(261666667, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + F(283333333, P_DISP_CC_PLL1_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8378, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_7, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x8194, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x81b0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x8248, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x81fc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_8, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_parent_data_8, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8218, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8230, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src =3D { + .cmd_rcgr =3D 0x82ac, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_aux_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src =3D { + .cmd_rcgr =3D 0x8290, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_link_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8260, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_pixel0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8278, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src =3D { + .cmd_rcgr =3D 0x8310, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_aux_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src =3D { + .cmd_rcgr =3D 0x82c4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_link_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x82e0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_pixel0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x82f8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src =3D { + .cmd_rcgr =3D 0x835c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_aux_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src =3D { + .cmd_rcgr =3D 0x8340, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_link_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8328, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_pixel0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x81cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_6, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x81e4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_6, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(650000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x8164, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_9, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_9, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x811c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x8134, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src =3D { + .cmd_rcgr =3D 0x814c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk2_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x817c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_esync0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] =3D { + F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_osc_clk_src =3D { + .cmd_rcgr =3D 0x8104, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_10, + .freq_tbl =3D ftbl_disp_cc_osc_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_osc_clk_src", + .parent_data =3D disp_cc_parent_data_10, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_10), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_ahb_swi_div_clk_src =3D { + .reg =3D 0x8374, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_swi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x81ac, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x81c8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src =3D { + .reg =3D 0x8214, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src =3D { + .reg =3D 0x82a8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src =3D { + .reg =3D 0x82dc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src =3D { + .reg =3D 0x8358, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_esync0_clk =3D { + .halt_reg =3D 0x80cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_esync0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_esync0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_esync1_clk =3D { + .halt_reg =3D 0x80d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_esync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_esync1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_accu_shift_clk =3D { + .halt_reg =3D 0xe060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xe060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0xa028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x80c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_swi_clk =3D { + .halt_reg =3D 0x80c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_swi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_swi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x8050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x8074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x8068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x806c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x806c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk =3D { + .halt_reg =3D 0x8060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_aux_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_crypto_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_link_clk =3D { + .halt_reg =3D 0x8080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk =3D { + .halt_reg =3D 0x8078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk =3D { + .halt_reg =3D 0x8084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx1_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_aux_clk =3D { + .halt_reg =3D 0x80a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_crypto_clk =3D { + .halt_reg =3D 0x80a4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_link_clk =3D { + .halt_reg =3D 0x809c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x809c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk =3D { + .halt_reg =3D 0x8094, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk =3D { + .halt_reg =3D 0x8098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx2_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx3_aux_clk =3D { + .halt_reg =3D 0x80b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx3_crypto_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx3_link_clk =3D { + .halt_reg =3D 0x80b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk =3D { + .halt_reg =3D 0x80ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx3_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x8054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x8058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x8010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0xa014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xa014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x8020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_ss_ip_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_ss_ip_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xc004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xc004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk2_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0xa024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_osc_clk =3D { + .halt_reg =3D 0x80c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_osc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_osc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct gdsc disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xb000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct clk_regmap *disp_cc_kaanapali_clocks[] =3D { + [DISP_CC_ESYNC0_CLK] =3D &disp_cc_esync0_clk.clkr, + [DISP_CC_ESYNC0_CLK_SRC] =3D &disp_cc_esync0_clk_src.clkr, + [DISP_CC_ESYNC1_CLK] =3D &disp_cc_esync1_clk.clkr, + [DISP_CC_ESYNC1_CLK_SRC] =3D &disp_cc_esync1_clk_src.clkr, + [DISP_CC_MDSS_ACCU_SHIFT_CLK] =3D &disp_cc_mdss_accu_shift_clk.clkr, + [DISP_CC_MDSS_AHB1_CLK] =3D &disp_cc_mdss_ahb1_clk.clkr, + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_AHB_SWI_CLK] =3D &disp_cc_mdss_ahb_swi_clk.clkr, + [DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC] =3D &disp_cc_mdss_ahb_swi_div_clk_src.= clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK] =3D &disp_cc_mdss_byte1_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &disp_cc_mdss_byte1_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &disp_cc_mdss_byte1_intf_clk.clkr, + [DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &disp_cc_mdss_dptx0_aux_clk.clkr, + [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx0_aux_clk_src.clkr, + [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &disp_cc_mdss_dptx0_crypto_clk.clkr, + [DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &disp_cc_mdss_dptx0_link_clk.clkr, + [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_clk_src.cl= kr, + [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_div_cl= k_src.clkr, + [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx0_link_intf_clk.= clkr, + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &disp_cc_mdss_dptx0_pixel0_clk.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel0_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &disp_cc_mdss_dptx0_pixel1_clk.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel1_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &disp_cc_mdss_dptx1_aux_clk.clkr, + [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx1_aux_clk_src.clkr, + [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &disp_cc_mdss_dptx1_crypto_clk.clkr, + [DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &disp_cc_mdss_dptx1_link_clk.clkr, + [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx1_link_clk_src.cl= kr, + [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx1_link_div_cl= k_src.clkr, + [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx1_link_intf_clk.= clkr, + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &disp_cc_mdss_dptx1_pixel0_clk.clkr, + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx1_pixel0_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &disp_cc_mdss_dptx1_pixel1_clk.clkr, + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx1_pixel1_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D + &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, + [DISP_CC_MDSS_DPTX2_AUX_CLK] =3D &disp_cc_mdss_dptx2_aux_clk.clkr, + [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx2_aux_clk_src.clkr, + [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] =3D &disp_cc_mdss_dptx2_crypto_clk.clkr, + [DISP_CC_MDSS_DPTX2_LINK_CLK] =3D &disp_cc_mdss_dptx2_link_clk.clkr, + [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx2_link_clk_src.cl= kr, + [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx2_link_div_cl= k_src.clkr, + [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx2_link_intf_clk.= clkr, + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] =3D &disp_cc_mdss_dptx2_pixel0_clk.clkr, + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx2_pixel0_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] =3D &disp_cc_mdss_dptx2_pixel1_clk.clkr, + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx2_pixel1_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX3_AUX_CLK] =3D &disp_cc_mdss_dptx3_aux_clk.clkr, + [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx3_aux_clk_src.clkr, + [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] =3D &disp_cc_mdss_dptx3_crypto_clk.clkr, + [DISP_CC_MDSS_DPTX3_LINK_CLK] =3D &disp_cc_mdss_dptx3_link_clk.clkr, + [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx3_link_clk_src.cl= kr, + [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx3_link_div_cl= k_src.clkr, + [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx3_link_intf_clk.= clkr, + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] =3D &disp_cc_mdss_dptx3_pixel0_clk.clkr, + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx3_pixel0_clk_sr= c.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_ESC1_CLK] =3D &disp_cc_mdss_esc1_clk.clkr, + [DISP_CC_MDSS_ESC1_CLK_SRC] =3D &disp_cc_mdss_esc1_clk_src.clkr, + [DISP_CC_MDSS_MDP1_CLK] =3D &disp_cc_mdss_mdp1_clk.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT1_CLK] =3D &disp_cc_mdss_mdp_lut1_clk.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_MDP_SS_IP_CLK] =3D &disp_cc_mdss_mdp_ss_ip_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_PCLK1_CLK] =3D &disp_cc_mdss_pclk1_clk.clkr, + [DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &disp_cc_mdss_pclk1_clk_src.clkr, + [DISP_CC_MDSS_PCLK2_CLK] =3D &disp_cc_mdss_pclk2_clk.clkr, + [DISP_CC_MDSS_PCLK2_CLK_SRC] =3D &disp_cc_mdss_pclk2_clk_src.clkr, + [DISP_CC_MDSS_VSYNC1_CLK] =3D &disp_cc_mdss_vsync1_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_OSC_CLK] =3D &disp_cc_osc_clk.clkr, + [DISP_CC_OSC_CLK_SRC] =3D &disp_cc_osc_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, + [DISP_CC_PLL1] =3D &disp_cc_pll1.clkr, + [DISP_CC_PLL2] =3D &disp_cc_pll2.clkr, +}; + +static struct gdsc *disp_cc_kaanapali_gdscs[] =3D { + [DISP_CC_MDSS_CORE_GDSC] =3D &disp_cc_mdss_core_gdsc, + [DISP_CC_MDSS_CORE_INT2_GDSC] =3D &disp_cc_mdss_core_int2_gdsc, +}; + +static const struct qcom_reset_map disp_cc_kaanapali_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [DISP_CC_MDSS_CORE_INT2_BCR] =3D { 0xa000 }, + [DISP_CC_MDSS_RSCC_BCR] =3D { 0xc000 }, +}; + +static struct clk_alpha_pll *disp_cc_kaanapali_plls[] =3D { + &disp_cc_pll0, + &disp_cc_pll1, + &disp_cc_pll2, +}; + +static u32 disp_cc_kaanapali_critical_cbcrs[] =3D { + 0xe064, /* DISP_CC_SLEEP_CLK */ + 0xe05c, /* DISP_CC_XO_CLK */ + 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */ + 0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */ +}; + +static const struct regmap_config disp_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x12094, + .fast_io =3D true, +}; + +static void clk_kaanapali_regs_configure(struct device *dev, struct regmap= *regmap) +{ + /* Enable clock gating for MDP clocks */ + regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4)); +} + +static struct qcom_cc_driver_data disp_cc_kaanapali_driver_data =3D { + .alpha_plls =3D disp_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_kaanapali_plls), + .clk_cbcrs =3D disp_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_kaanapali_critical_cbcrs), + .clk_regs_configure =3D clk_kaanapali_regs_configure, +}; + +static const struct qcom_cc_desc disp_cc_kaanapali_desc =3D { + .config =3D &disp_cc_kaanapali_regmap_config, + .clks =3D disp_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_kaanapali_clocks), + .resets =3D disp_cc_kaanapali_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_kaanapali_resets), + .gdscs =3D disp_cc_kaanapali_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_kaanapali_gdscs), + .use_rpm =3D true, + .driver_data =3D &disp_cc_kaanapali_driver_data, +}; + +static const struct of_device_id disp_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_kaanapali_match_table); + +static int disp_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_kaanapali_desc); +} + +static struct platform_driver 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classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Add support for the Camera Clock Controller (CAMCC) on the Kaanapali platform. The CAMCC block on Kaanapali includes both the primary camera clock controller and the Camera BIST clock controller, which provides the functional MCLK required for camera operations. Signed-off-by: Jingyi Wang Reviewed-by: Bryan O'Donoghue Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/cambistmclkcc-kaanapali.c | 437 +++++ drivers/clk/qcom/camcc-kaanapali.c | 2661 ++++++++++++++++++++++++= ++++ 4 files changed, 3109 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e293d1a816c2eece0291e9ee707698e97ed75cd8..085f75f8ab1e2e6797767f88e36= 28961f2d3ba0a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -46,6 +46,16 @@ config CLK_GLYMUR_TCSRCC Support for the TCSR clock controller on GLYMUR devices. Say Y if you want to use peripheral devices such as USB/PCIe/EDP. =20 +config CLK_KAANAPALI_CAMCC + tristate "Kaanapali Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_KAANAPALI_GCC + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Kaanapali devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_KAANAPALI_DISPCC tristate "Kaanapali Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 98ec8aeb5d5049855bb65f7371a10fb2418a468f..8b3ad2c68d489cc38a22d3b665c= afb495fb698f1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o +obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-kaa= napali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/cambistmclkcc-kaanapali.c b/drivers/clk/qcom/= cambistmclkcc-kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..066c1087b0b65c4a90e885db236= 2eda046e99bb5 --- /dev/null +++ b/drivers/clk/qcom/cambistmclkcc-kaanapali.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_AHB_CLK, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, + P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco rivian_eko_t_vco[] =3D { + { 883200000, 1171200000, 0 }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config =3D { + .l =3D 0x32, + .cal_l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x12000000, + .config_ctl_hi_val =3D 0x00890263, + .config_ctl_hi1_val =3D 0x1af04237, + .config_ctl_hi2_val =3D 0x00000000, +}; + +static struct clk_alpha_pll cam_bist_mclk_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_bist_mclk_cc_pll0_config, + .vco_table =3D rivian_eko_t_vco, + .num_vco =3D ARRAY_SIZE(rivian_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_rivian_eko_t_ops, + }, + }, +}; + +static const struct parent_map cam_bist_mclk_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 }, + { P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_bist_mclk_cc_pll0.clkr.hw }, + { .hw =3D &cam_bist_mclk_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4), + F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x4000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk0_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src =3D { + .cmd_rcgr =3D 0x401c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk1_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src =3D { + .cmd_rcgr =3D 0x4038, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk2_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src =3D { + .cmd_rcgr =3D 0x4054, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk3_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src =3D { + .cmd_rcgr =3D 0x4070, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk4_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src =3D { + .cmd_rcgr =3D 0x408c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk5_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src =3D { + .cmd_rcgr =3D 0x40a8, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk6_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src =3D { + .cmd_rcgr =3D 0x40c4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk7_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk0_clk =3D { + .halt_reg =3D 0x4018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk1_clk =3D { + .halt_reg =3D 0x4034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk2_clk =3D { + .halt_reg =3D 0x4050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk3_clk =3D { + .halt_reg =3D 0x406c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x406c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk4_clk =3D { + .halt_reg =3D 0x4088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk5_clk =3D { + .halt_reg =3D 0x40a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk6_clk =3D { + .halt_reg =3D 0x40c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk7_clk =3D { + .halt_reg =3D 0x40dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *cam_bist_mclk_cc_kaanapali_clocks[] =3D { + [CAM_BIST_MCLK_CC_MCLK0_CLK] =3D &cam_bist_mclk_cc_mclk0_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] =3D &cam_bist_mclk_cc_mclk0_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK1_CLK] =3D &cam_bist_mclk_cc_mclk1_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] =3D &cam_bist_mclk_cc_mclk1_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK2_CLK] =3D &cam_bist_mclk_cc_mclk2_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] =3D &cam_bist_mclk_cc_mclk2_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK3_CLK] =3D &cam_bist_mclk_cc_mclk3_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] =3D &cam_bist_mclk_cc_mclk3_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK4_CLK] =3D &cam_bist_mclk_cc_mclk4_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] =3D &cam_bist_mclk_cc_mclk4_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK5_CLK] =3D &cam_bist_mclk_cc_mclk5_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] =3D &cam_bist_mclk_cc_mclk5_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK6_CLK] =3D &cam_bist_mclk_cc_mclk6_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] =3D &cam_bist_mclk_cc_mclk6_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK7_CLK] =3D &cam_bist_mclk_cc_mclk7_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] =3D &cam_bist_mclk_cc_mclk7_clk_src.clkr, + [CAM_BIST_MCLK_CC_PLL0] =3D &cam_bist_mclk_cc_pll0.clkr, +}; + +static struct clk_alpha_pll *cam_bist_mclk_cc_kaanapali_plls[] =3D { + &cam_bist_mclk_cc_pll0, +}; + +static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] =3D { + 0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config= =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5010, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = =3D { + .alpha_plls =3D cam_bist_mclk_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls), + .clk_cbcrs =3D cam_bist_mclk_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_bist_mclk_cc_kaanapali_desc =3D { + .config =3D &cam_bist_mclk_cc_kaanapali_regmap_config, + .clks =3D cam_bist_mclk_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_clocks), + .use_rpm =3D true, + .driver_data =3D &cam_bist_mclk_cc_kaanapali_driver_data, +}; + +static const struct of_device_id cam_bist_mclk_cc_kaanapali_match_table[] = =3D { + { .compatible =3D "qcom,kaanapali-cambistmclkcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_kaanapali_match_table); + +static int cam_bist_mclk_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_bist_mclk_cc_kaanapali_desc); +} + +static struct platform_driver cam_bist_mclk_cc_kaanapali_driver =3D { + .probe =3D cam_bist_mclk_cc_kaanapali_probe, + .driver =3D { + .name =3D "cambistmclkcc-kaanapali", + .of_match_table =3D cam_bist_mclk_cc_kaanapali_match_table, + }, +}; + +module_platform_driver(cam_bist_mclk_cc_kaanapali_driver); + +MODULE_DESCRIPTION("QTI CAMBISTMCLKCC Kaanapali Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/camcc-kaanapali.c b/drivers/clk/qcom/camcc-ka= anapali.c new file mode 100644 index 0000000000000000000000000000000000000000..82967993fcffe9dc0707d1ddda0= fbb278e67d42b --- /dev/null +++ b/drivers/clk/qcom/camcc-kaanapali.c @@ -0,0 +1,2661 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_AHB_CLK, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL6_OUT_ODD, + P_CAM_CC_PLL7_OUT_EVEN, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x3e, + .cal_l =3D 0x48, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00008408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd =3D { + .offset =3D 0x0, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll0_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 665.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll1_config =3D { + .l =3D 0x22, + .cal_l =3D 0x48, + .alpha =3D 0xa2aa, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even =3D { + .offset =3D 0x1000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll1_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 677.6 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x23, + .cal_l =3D 0x48, + .alpha =3D 0x4aaa, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll2_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 720.56 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x25, + .cal_l =3D 0x48, + .alpha =3D 0x8777, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even =3D { + .offset =3D 0x3000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll3_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 720.56 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config =3D { + .l =3D 0x25, + .cal_l =3D 0x48, + .alpha =3D 0x8777, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll4 =3D { + .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 720.56 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config =3D { + .l =3D 0x25, + .cal_l =3D 0x48, + .alpha =3D 0x8777, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll5 =3D { + .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even =3D { + .offset =3D 0x5000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll5_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config =3D { + .l =3D 0x32, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00008408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll6 =3D { + .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even =3D { + .offset =3D 0x6000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll6_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd =3D { + .offset =3D 0x6000, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll6_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +/* 1000.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll7_config =3D { + .l =3D 0x34, + .cal_l =3D 0x48, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll7 =3D { + .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll7", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even =3D { + .offset =3D 0x7000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll7_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll7_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll7_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src =3D { + .cmd_rcgr =3D 0x212cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_camnoc_rt_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src =3D { + .cmd_rcgr =3D 0x21250, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src =3D { + .cmd_rcgr =3D 0x2126c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src =3D { + .cmd_rcgr =3D 0x21288, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(266666667, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x21064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] =3D { + F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src =3D { + .cmd_rcgr =3D 0x211a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20024, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src =3D { + .cmd_rcgr =3D 0x200a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csid_clk_src =3D { + .cmd_rcgr =3D 0x212a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x200dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] =3D { + F(500000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(740000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(875000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(1000000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_0_clk_src =3D { + .cmd_rcgr =3D 0x211f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_1_clk_src =3D { + .cmd_rcgr =3D 0x21220, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0x21144, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0x21170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] =3D { + F(332500000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src =3D { + .cmd_rcgr =3D 0x20188, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ipe_nps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src =3D { + .cmd_rcgr =3D 0x211c4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] =3D { + F(338800000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(484000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(586000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ofe_clk_src =3D { + .cmd_rcgr =3D 0x2011c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ofe_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] =3D { + F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), + F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), + F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), + F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src =3D { + .cmd_rcgr =3D 0x21314, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_qdss_debug_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x20100, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] =3D { + F(360280000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(716000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_0_clk_src =3D { + .cmd_rcgr =3D 0x21018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_tfe_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] =3D { + F(360280000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(716000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_1_clk_src =3D { + .cmd_rcgr =3D 0x21094, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6, + .freq_tbl =3D ftbl_cam_cc_tfe_1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_clk_src", + .parent_data =3D cam_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] =3D { + F(360280000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(716000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_2_clk_src =3D { + .cmd_rcgr =3D 0x210f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_7, + .freq_tbl =3D ftbl_cam_cc_tfe_2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_clk_src", + .parent_data =3D cam_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x2134c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_8, + .freq_tbl =3D ftbl_cam_cc_xo_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_xo_clk_src", + .parent_data =3D cam_cc_parent_data_8, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch cam_cc_cam_top_ahb_clk =3D { + .halt_reg =3D 0x2137c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2137c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cam_top_fast_ahb_clk =3D { + .halt_reg =3D 0x2136c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2136c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_axi_clk =3D { + .halt_reg =3D 0x212f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_cre_clk =3D { + .halt_reg =3D 0x211bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk =3D { + .halt_reg =3D 0x201b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk =3D { + .halt_reg =3D 0x20144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_axi_clk =3D { + .halt_reg =3D 0x212e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk =3D { + .halt_reg =3D 0x2116c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2116c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk =3D { + .halt_reg =3D 0x21040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk =3D { + .halt_reg =3D 0x210bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk =3D { + .halt_reg =3D 0x21120, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21120, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk =3D { + .halt_reg =3D 0x2130c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2130c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk =3D { + .halt_reg =3D 0x21268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk =3D { + .halt_reg =3D 0x21284, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21284, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk =3D { + .halt_reg =3D 0x212a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk =3D { + .halt_reg =3D 0x21348, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x21348, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_core_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk =3D { + .halt_reg =3D 0x211c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk =3D { + .halt_reg =3D 0x211b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x20018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x2003c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2003c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x2005c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2005c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk =3D { + .halt_reg =3D 0x2007c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2007c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk =3D { + .halt_reg =3D 0x2009c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2009c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk =3D { + .halt_reg =3D 0x200bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk =3D { + .halt_reg =3D 0x212bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk =3D { + .halt_reg =3D 0x20020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x2001c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2001c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x20040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x20060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk =3D { + .halt_reg =3D 0x20080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk =3D { + .halt_reg =3D 0x200a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk =3D { + .halt_reg =3D 0x200c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_ahb_clk =3D { + .halt_reg =3D 0x21248, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21248, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_clk =3D { + .halt_reg =3D 0x21210, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21210, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_ahb_clk =3D { + .halt_reg =3D 0x2124c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2124c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_clk =3D { + .halt_reg =3D 0x21238, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21238, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk =3D { + .halt_reg =3D 0x2119c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2119c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0x2115c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2115c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0x21198, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21198, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0x21188, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21188, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk =3D { + .halt_reg =3D 0x201cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk =3D { + .halt_reg =3D 0x201a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk =3D { + .halt_reg =3D 0x201d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk =3D { + .halt_reg =3D 0x201b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk =3D { + .halt_reg =3D 0x201d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk =3D { + .halt_reg =3D 0x211dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_ahb_clk =3D { + .halt_reg =3D 0x20118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_clk =3D { + .halt_reg =3D 0x20148, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk =3D { + .halt_reg =3D 0x200f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_clk =3D { + .halt_reg =3D 0x20158, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20158, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk =3D { + .halt_reg =3D 0x200fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_clk =3D { + .halt_reg =3D 0x20134, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_fast_ahb_clk =3D { + .halt_reg =3D 0x200f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk =3D { + .halt_reg =3D 0x2132c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2132c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x21330, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21330, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_clk =3D { + .halt_reg =3D 0x21044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x21060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_clk =3D { + .halt_reg =3D 0x21030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk =3D { + .halt_reg =3D 0x2105c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2105c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_clk =3D { + .halt_reg =3D 0x210c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x210dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_clk =3D { + .halt_reg =3D 0x210ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk =3D { + .halt_reg =3D 0x210d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_clk =3D { + .halt_reg =3D 0x21124, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21124, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x21140, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21140, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_clk =3D { + .halt_reg =3D 0x21110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk =3D { + .halt_reg =3D 0x2113c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2113c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tracenoc_tpdm_1_cmb_clk =3D { + .halt_reg =3D 0x21394, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21394, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tracenoc_tpdm_1_cmb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc =3D { + .gdscr =3D 0x21334, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc =3D { + .gdscr =3D 0x20174, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ipe_0_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct gdsc cam_cc_ofe_gdsc =3D { + .gdscr =3D 0x200c8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ofe_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_0_gdsc =3D { + .gdscr =3D 0x21004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_1_gdsc =3D { + .gdscr =3D 0x21080, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_2_gdsc =3D { + .gdscr =3D 0x210e4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct clk_regmap *cam_cc_kaanapali_clocks[] =3D { + [CAM_CC_CAM_TOP_AHB_CLK] =3D &cam_cc_cam_top_ahb_clk.clkr, + [CAM_CC_CAM_TOP_FAST_AHB_CLK] =3D &cam_cc_cam_top_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_NRT_AXI_CLK] =3D &cam_cc_camnoc_nrt_axi_clk.clkr, + [CAM_CC_CAMNOC_NRT_CRE_CLK] =3D &cam_cc_camnoc_nrt_cre_clk.clkr, + [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] =3D &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, + [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] =3D &cam_cc_camnoc_nrt_ofe_main_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK] =3D &cam_cc_camnoc_rt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] =3D &cam_cc_camnoc_rt_axi_clk_src.clkr, + [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] =3D &cam_cc_camnoc_rt_ife_lite_clk.clkr, + [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_0_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_1_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_2_main_clk.cl= kr, + [CAM_CC_CAMNOC_XO_CLK] =3D &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] =3D &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] =3D &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] =3D &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] =3D &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] =3D &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] =3D &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] =3D &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] =3D &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] =3D &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] =3D &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] =3D &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] =3D &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] =3D &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] =3D &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] =3D &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] =3D &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] =3D &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] =3D &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] =3D &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] =3D &cam_cc_csiphy5_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_0_AHB_CLK] =3D &cam_cc_icp_0_ahb_clk.clkr, + [CAM_CC_ICP_0_CLK] =3D &cam_cc_icp_0_clk.clkr, + [CAM_CC_ICP_0_CLK_SRC] =3D &cam_cc_icp_0_clk_src.clkr, + [CAM_CC_ICP_1_AHB_CLK] =3D &cam_cc_icp_1_ahb_clk.clkr, + [CAM_CC_ICP_1_CLK] =3D &cam_cc_icp_1_clk.clkr, + [CAM_CC_ICP_1_CLK_SRC] =3D &cam_cc_icp_1_clk_src.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] =3D &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] =3D &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] =3D &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] =3D &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] =3D &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] =3D &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] =3D &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_JPEG_CLK] =3D &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] =3D &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_OFE_AHB_CLK] =3D &cam_cc_ofe_ahb_clk.clkr, + [CAM_CC_OFE_ANCHOR_CLK] =3D &cam_cc_ofe_anchor_clk.clkr, + [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] =3D &cam_cc_ofe_anchor_fast_ahb_clk.clkr, + [CAM_CC_OFE_CLK_SRC] =3D &cam_cc_ofe_clk_src.clkr, + [CAM_CC_OFE_HDR_CLK] =3D &cam_cc_ofe_hdr_clk.clkr, + [CAM_CC_OFE_HDR_FAST_AHB_CLK] =3D &cam_cc_ofe_hdr_fast_ahb_clk.clkr, + [CAM_CC_OFE_MAIN_CLK] =3D &cam_cc_ofe_main_clk.clkr, + [CAM_CC_OFE_MAIN_FAST_AHB_CLK] =3D &cam_cc_ofe_main_fast_ahb_clk.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] =3D &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] =3D &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] =3D &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] =3D &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_EVEN] =3D &cam_cc_pll2_out_even.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] =3D &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] =3D &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] =3D &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] =3D &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] =3D &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] =3D &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] =3D &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL6_OUT_ODD] =3D &cam_cc_pll6_out_odd.clkr, + [CAM_CC_PLL7] =3D &cam_cc_pll7.clkr, + [CAM_CC_PLL7_OUT_EVEN] =3D &cam_cc_pll7_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] =3D &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] =3D &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_TFE_0_BAYER_CLK] =3D &cam_cc_tfe_0_bayer_clk.clkr, + [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_0_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_0_CLK_SRC] =3D &cam_cc_tfe_0_clk_src.clkr, + [CAM_CC_TFE_0_MAIN_CLK] =3D &cam_cc_tfe_0_main_clk.clkr, + [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_0_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_1_BAYER_CLK] =3D &cam_cc_tfe_1_bayer_clk.clkr, + [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_1_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_1_CLK_SRC] =3D &cam_cc_tfe_1_clk_src.clkr, + [CAM_CC_TFE_1_MAIN_CLK] =3D &cam_cc_tfe_1_main_clk.clkr, + [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_1_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_2_BAYER_CLK] =3D &cam_cc_tfe_2_bayer_clk.clkr, + [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_2_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_2_CLK_SRC] =3D &cam_cc_tfe_2_clk_src.clkr, + [CAM_CC_TFE_2_MAIN_CLK] =3D &cam_cc_tfe_2_main_clk.clkr, + [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_2_main_fast_ahb_clk.clkr, + [CAM_CC_TRACENOC_TPDM_1_CMB_CLK] =3D &cam_cc_tracenoc_tpdm_1_cmb_clk.clkr, + [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_kaanapali_gdscs[] =3D { + [CAM_CC_IPE_0_GDSC] =3D &cam_cc_ipe_0_gdsc, + [CAM_CC_OFE_GDSC] =3D &cam_cc_ofe_gdsc, + [CAM_CC_TFE_0_GDSC] =3D &cam_cc_tfe_0_gdsc, + [CAM_CC_TFE_1_GDSC] =3D &cam_cc_tfe_1_gdsc, + [CAM_CC_TFE_2_GDSC] =3D &cam_cc_tfe_2_gdsc, + [CAM_CC_TITAN_TOP_GDSC] =3D &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_kaanapali_resets[] =3D { + [CAM_CC_DRV_BCR] =3D { 0x2138c }, + [CAM_CC_ICP_BCR] =3D { 0x211f4 }, + [CAM_CC_IPE_0_BCR] =3D { 0x20170 }, + [CAM_CC_OFE_BCR] =3D { 0x200c4 }, + [CAM_CC_QDSS_DEBUG_BCR] =3D { 0x21310 }, + [CAM_CC_TFE_0_BCR] =3D { 0x21000 }, + [CAM_CC_TFE_1_BCR] =3D { 0x2107c }, + [CAM_CC_TFE_2_BCR] =3D { 0x210e0 }, +}; + +static struct clk_alpha_pll *cam_cc_kaanapali_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, +}; + +static u32 cam_cc_kaanapali_critical_cbcrs[] =3D { + 0x21398, /* CAM_CC_DRV_AHB_CLK */ + 0x21390, /* CAM_CC_DRV_XO_CLK */ + 0x21364, /* CAM_CC_GDSC_CLK */ + 0x21368, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2601c, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data cam_cc_kaanapali_driver_data =3D { + .alpha_plls =3D cam_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_kaanapali_plls), + .clk_cbcrs =3D cam_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_kaanapali_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_kaanapali_desc =3D { + .config =3D &cam_cc_kaanapali_regmap_config, + .clks =3D cam_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_kaanapali_clocks), + .resets =3D cam_cc_kaanapali_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_kaanapali_resets), + .gdscs =3D cam_cc_kaanapali_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_kaanapali_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_kaanapali_driver_data, +}; + +static const struct of_device_id cam_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_kaanapali_match_table); + +static int cam_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_kaanapali_desc); +} + +static struct platform_driver cam_cc_kaanapali_driver =3D { + .probe =3D cam_cc_kaanapali_probe, + .driver =3D { + .name =3D "camcc-kaanapali", + .of_match_table =3D cam_cc_kaanapali_match_table, + }, +}; + +module_platform_driver(cam_cc_kaanapali_driver); + +MODULE_DESCRIPTION("QTI CAMCC Kaanapali Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Dec 2 00:04:38 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D92B532C957 for ; Tue, 25 Nov 2025 17:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764092796; cv=none; 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authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511250148 Enable Kaanapali video clock driver for video SW to be able to control the clocks from the Video SW driver. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-kaanapali.c | 821 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 831 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 085f75f8ab1e2e6797767f88e3628961f2d3ba0a..4f9980da465128b2c172ed8309b= 30596f4ca765b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -66,6 +66,15 @@ config CLK_KAANAPALI_DISPCC Say Y if you want to support display devices and functionality such as splash screen. =20 +config CLK_KAANAPALI_VIDEOCC + tristate "Kaanapali Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_KAANAPALI_GCC + help + Support for the video clock controller on Kaanapali devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 8b3ad2c68d489cc38a22d3b665cafb495fb698f1..6b04b29f1b42938f16e1ac702db= 6aa6755695c43 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-kaa= napali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o +obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/videocc-kaanapali.c b/drivers/clk/qcom/videoc= c-kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..a335e94761a097614c1b602d17f= 9ea236b9d5140 --- /dev/null +++ b/drivers/clk/qcom/videocc-kaanapali.c @@ -0,0 +1,821 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +#define ACCU_CFG_MASK GENMASK(25, 21) + +enum { + DT_BI_TCXO, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, + P_VIDEO_CC_PLL2_OUT_MAIN, + P_VIDEO_CC_PLL3_OUT_MAIN, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 360.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x12, + .cal_l =3D 0x48, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll1_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll2_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &video_cc_pll2_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll3_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &video_cc_pll3_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll1.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL3_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll3.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL2_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll2.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8060, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0a_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0a_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs0a_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(850000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0b_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_3, + .freq_tbl =3D ftbl_video_cc_mvs0b_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk_src", + .parent_data =3D video_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] =3D { + F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0c_clk_src =3D { + .cmd_rcgr =3D 0x8048, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_4, + .freq_tbl =3D ftbl_video_cc_mvs0c_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk_src", + .parent_data =3D video_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x8194, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80d0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch video_cc_mvs0_freerun_clk =3D { + .mem_enable_reg =3D 0x80E4, + .mem_ack_reg =3D 0x80E4, + .mem_enable_mask =3D BIT(3), + .mem_enable_ack_mask =3D 0xc00, + .mem_enable_invert =3D true, + .branch =3D { + .halt_reg =3D 0x80e0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x81b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_clk =3D { + .halt_reg =3D 0x8134, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8134, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_freerun_clk =3D { + .halt_reg =3D 0x8144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp1_clk =3D { + .halt_reg =3D 0x8108, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8108, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp1_freerun_clk =3D { + .halt_reg =3D 0x8118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp1_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0a_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8090, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0a_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0a_freerun_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0a_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80bc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_freerun_clk =3D { + .halt_reg =3D 0x80cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x8164, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8164, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x8174, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8174, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x81b8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0_vpp0_gdsc =3D { + .gdscr =3D 0x8120, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0_vpp0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_vpp1_gdsc =3D { + .gdscr =3D 0x80f4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0_vpp1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0a_gdsc =3D { + .gdscr =3D 0x807c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0a_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x814c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x80a8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_kaanapali_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.branch.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0_VPP0_CLK] =3D &video_cc_mvs0_vpp0_clk.clkr, + [VIDEO_CC_MVS0_VPP0_FREERUN_CLK] =3D &video_cc_mvs0_vpp0_freerun_clk.clkr, + [VIDEO_CC_MVS0_VPP1_CLK] =3D &video_cc_mvs0_vpp1_clk.clkr, + [VIDEO_CC_MVS0_VPP1_FREERUN_CLK] =3D &video_cc_mvs0_vpp1_freerun_clk.clkr, + [VIDEO_CC_MVS0A_CLK] =3D &video_cc_mvs0a_clk.clkr, + [VIDEO_CC_MVS0A_CLK_SRC] =3D &video_cc_mvs0a_clk_src.clkr, + [VIDEO_CC_MVS0A_FREERUN_CLK] =3D &video_cc_mvs0a_freerun_clk.clkr, + [VIDEO_CC_MVS0B_CLK] =3D &video_cc_mvs0b_clk.clkr, + [VIDEO_CC_MVS0B_CLK_SRC] =3D &video_cc_mvs0b_clk_src.clkr, + [VIDEO_CC_MVS0B_FREERUN_CLK] =3D &video_cc_mvs0b_freerun_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_CLK_SRC] =3D &video_cc_mvs0c_clk_src.clkr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] =3D &video_cc_pll1.clkr, + [VIDEO_CC_PLL2] =3D &video_cc_pll2.clkr, + [VIDEO_CC_PLL3] =3D &video_cc_pll3.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_kaanapali_gdscs[] =3D { + [VIDEO_CC_MVS0A_GDSC] =3D &video_cc_mvs0a_gdsc, + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0_VPP1_GDSC] =3D &video_cc_mvs0_vpp1_gdsc, + [VIDEO_CC_MVS0_VPP0_GDSC] =3D &video_cc_mvs0_vpp0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_kaanapali_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x8178 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x80a4 }, + [VIDEO_CC_MVS0_VPP0_BCR] =3D { 0x811c }, + [VIDEO_CC_MVS0_VPP1_BCR] =3D { 0x80f0 }, + [VIDEO_CC_MVS0A_BCR] =3D { 0x8078 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x8164, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8148 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x80e0, 2 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x8174, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x81ac, 2 }, +}; + +static struct clk_alpha_pll *video_cc_kaanapali_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, + &video_cc_pll2, + &video_cc_pll3, +}; + +static u32 video_cc_kaanapali_critical_cbcrs[] =3D { + 0x817c, /* VIDEO_CC_AHB_CLK */ + 0x81bc, /* VIDEO_CC_SLEEP_CLK */ + 0x81b0, /* VIDEO_CC_TS_XO_CLK */ + 0x81ac, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xa010, + .fast_io =3D true, +}; + +static void clk_kaanapali_regs_configure(struct device *dev, struct regmap= *regmap) +{ + /* + * Enable clk_on sync for MVS0 and VPP clocks via VIDEO_CC_SPARE1 + * during core reset by default. + */ + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); + + /* + * As per HW design recommendation + * Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for the below GDSCs + * MVS0A CFG3, MVS0 CFG3, MVS0 VPP1 CFG3, MVS0 VPP0 CFG3, MVS0C CFG3 + */ + regmap_set_bits(regmap, 0x8088, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x8100, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK); +} + +static struct qcom_cc_driver_data video_cc_kaanapali_driver_data =3D { + .alpha_plls =3D video_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_kaanapali_plls), + .clk_cbcrs =3D video_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_kaanapali_critical_cbcrs), + .clk_regs_configure =3D clk_kaanapali_regs_configure, +}; + +static const struct qcom_cc_desc video_cc_kaanapali_desc =3D { + .config =3D &video_cc_kaanapali_regmap_config, + .clks =3D video_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_kaanapali_clocks), + .resets =3D video_cc_kaanapali_resets, + .num_resets =3D ARRAY_SIZE(video_cc_kaanapali_resets), + .gdscs =3D video_cc_kaanapali_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_kaanapali_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_kaanapali_driver_data, +}; + +static const struct of_device_id video_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_kaanapali_match_table); + +static int video_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_kaanapali_desc); +} + +static struct platform_driver video_cc_kaanapali_driver =3D { + .probe =3D video_cc_kaanapali_probe, + .driver =3D { + .name =3D "videocc-kaanapali", + .of_match_table =3D video_cc_kaanapali_match_table, + }, +}; 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GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-kaanapali.c | 494 ++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/gxclkctl-kaanapali.c | 76 ++++++ 4 files changed, 580 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 4f9980da465128b2c172ed8309b30596f4ca765b..ec24ca3691467ec246d0633a692= 178460d3ef2cd 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -66,6 +66,15 @@ config CLK_KAANAPALI_DISPCC Say Y if you want to support display devices and functionality such as splash screen. =20 +config CLK_KAANAPALI_GPUCC + tristate "Kaanapali Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_KAANAPALI_GCC + help + Support for the graphics clock controller on Kaanapali devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_KAANAPALI_VIDEOCC tristate "Kaanapali Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b04b29f1b42938f16e1ac702db6aa6755695c43..82719fb9b7b153a9fefa05f908f= 8c39522224862 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-kaa= napali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o +obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/gpucc-kaanapali.c b/drivers/clk/qcom/gpucc-ka= anapali.c new file mode 100644 index 0000000000000000000000000000000000000000..5d31977d8108a09275d22007674= ff14e33bcfc45 --- /dev/null +++ b/drivers/clk/qcom/gpucc-kaanapali.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 950.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x31, + .cal_l =3D 0x48, + .alpha =3D 0x7aaa, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000408, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpu_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eko_t_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0_out_even.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(475000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .hw_clk_ctrl =3D true, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x9430, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x9104, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9104, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x90e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9108, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x9060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93ec, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93ec, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90ec, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90ec, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_kaanapali_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] =3D &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_kaanapali_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_kaanapali_resets[] =3D { + [GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, + [GPU_CC_FF_BCR] =3D { 0x9470 }, + [GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_XO_BCR] =3D { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_cc_kaanapali_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_kaanapali_critical_cbcrs[] =3D { + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */ + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ +}; + +static const struct regmap_config gpu_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x95e8, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data =3D { + .alpha_plls =3D gpu_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_kaanapali_plls), + .clk_cbcrs =3D gpu_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_kaanapali_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_kaanapali_desc =3D { + .config =3D &gpu_cc_kaanapali_regmap_config, + .clks =3D gpu_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_kaanapali_clocks), + .resets =3D gpu_cc_kaanapali_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_kaanapali_resets), + .gdscs =3D gpu_cc_kaanapali_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_kaanapali_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_kaanapali_driver_data, +}; + +static const struct of_device_id gpu_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_kaanapali_match_table); + +static int gpu_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_kaanapali_desc); +} + +static struct platform_driver gpu_cc_kaanapali_driver =3D { + .probe =3D gpu_cc_kaanapali_probe, + .driver =3D { + .name =3D "gpucc-kaanapali", + .of_match_table =3D gpu_cc_kaanapali_match_table, + }, +}; + +module_platform_driver(gpu_cc_kaanapali_driver); + +MODULE_DESCRIPTION("QTI GPUCC Kaanapali Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclk= ctl-kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..a4bab24f8d29b8c90ef09080a75= 248dfdde3c4a6 --- /dev/null +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, +}; + +static struct gdsc gx_clkctl_gx_gdsc =3D { + .gdscr =3D 0x0, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gx_clkctl_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gx_clkctl_gdscs[] =3D { + [GX_CLKCTL_GX_GDSC] =3D &gx_clkctl_gx_gdsc, +}; + +static const struct regmap_config gx_clkctl_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gx_clkctl_kaanapali_desc =3D { + .config =3D &gx_clkctl_regmap_config, + .gdscs =3D gx_clkctl_gdscs, + .num_gdscs =3D ARRAY_SIZE(gx_clkctl_gdscs), + .use_rpm =3D true, +}; + +static const struct of_device_id gx_clkctl_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-gxclkctl" }, + { } +}; +MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table); + +static int gx_clkctl_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gx_clkctl_kaanapali_desc); +} + +static struct platform_driver gx_clkctl_kaanapali_driver =3D { + .probe =3D gx_clkctl_kaanapali_probe, + .driver =3D { + .name =3D "gxclkctl-kaanapali", + .of_match_table =3D gx_clkctl_kaanapali_match_table, + }, +}; + +module_platform_driver(gx_clkctl_kaanapali_driver); + +MODULE_DESCRIPTION("QTI GXCLKCTL Kaanapali Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1