From nobody Tue Dec 2 01:06:31 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7963431C567 for ; Mon, 24 Nov 2025 18:54:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764010490; cv=none; b=EmuvmgPzHxaBDFdGtjMp2FZ10c9paPyKy+kZAUqZhSC/k/miCshM28zE01jXr/r6129PUSQAgIVXLiHppFBa9713/+cKB/l3iCLUFcEvSRIFWdqJN+AvgH5fzhSSwKTqv+Fovmqtiy7JNKdn643M4r4SBU4B4POa72GyvA00pHs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764010490; c=relaxed/simple; bh=eOCoKsoV5cP5MAWG4ZVEVrCDCAab/3aeP6x7Owf3cfM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nIGgJqXXh3sLSAtPxWx7+7X2nyF0BA+SmMJTcPeRAzwPqwjcNOUmxD8k7sHozBkE5R2Hk+mBVU/DCy5PxKKBB7DnbKQKmv+TUYW93W3uz4myLa/n8Re1sFNRAXMqqGWSW4v3pkd9Aayvow4NAKrj9FEvW/arKuPjhwzRW49GJgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A9vGs1qO; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A9vGs1qO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764010488; x=1795546488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eOCoKsoV5cP5MAWG4ZVEVrCDCAab/3aeP6x7Owf3cfM=; b=A9vGs1qOkmh26zSfLYqL5uACCINpT+sPnktkBUKjRK9wZzdslGtpYHZv ZvPqSs0qD1KCrQW1WkHDjnC5KW/1/TaQDevxmHbEUpzRtLV42q5cXHFOH X/7nW+ViTl+leAkHABuQzFKOrTmPqXBDec/qNrUJouwwilQrNAQrvQknO nUfrg9skAb14rc+29vVcQj9oRjcrpUKgNSHCFYc7Z4E65cNAx0z5sJvT2 9/v27dQndCXyVjz6o7HCRZFoFJz7lf5NEcAiiMjbtEndgwzxawkxQoibu 9cJwAvuLTQmIsucDR1pkBeyFaIs+In0+OhfZQ7/tdo5i37dTPPJwWHci6 g==; X-CSE-ConnectionGUID: OoZrJrM5SKOhB/Opy2/yhg== X-CSE-MsgGUID: ggE8XB0uQoq1pPtCdSj7Eg== X-IronPort-AV: E=McAfee;i="6800,10657,11623"; a="76636525" X-IronPort-AV: E=Sophos;i="6.20,223,1758610800"; d="scan'208";a="76636525" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2025 10:54:24 -0800 X-CSE-ConnectionGUID: L1u0A+GiT5q0KLbizbb+6w== X-CSE-MsgGUID: 16XPu04oTpuIr2VIQzCVyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,223,1758610800"; d="scan'208";a="192224962" Received: from rfrazer-mobl3.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.153]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2025 10:54:23 -0800 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v14 07/32] x86,fs/resctrl: Use struct rdt_domain_hdr when reading counters Date: Mon, 24 Nov 2025 10:53:44 -0800 Message-ID: <20251124185412.24155-8-tony.luck@intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251124185412.24155-1-tony.luck@intel.com> References: <20251124185412.24155-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the whole call sequence from mon_event_read() to resctrl_arch_rmid_= read() to pass resource independent struct rdt_domain_hdr instead of an L3 specific domain structure to prepare for monitoring events in other resources. Signed-off-by: Tony Luck --- include/linux/resctrl.h | 4 +- fs/resctrl/internal.h | 18 ++++--- arch/x86/kernel/cpu/resctrl/monitor.c | 12 +++-- fs/resctrl/ctrlmondata.c | 9 +--- fs/resctrl/monitor.c | 72 +++++++++++++++++---------- 5 files changed, 68 insertions(+), 47 deletions(-) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 5db37c7e89c5..9b9877fb3238 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -517,7 +517,7 @@ void resctrl_offline_cpu(unsigned int cpu); * resctrl_arch_rmid_read() - Read the eventid counter corresponding to rm= id * for this resource and domain. * @r: resource that the counter should be read from. - * @d: domain that the counter should be read from. + * @hdr: Header of domain that the counter should be read from. * @closid: closid that matches the rmid. Depending on the architecture, = the * counter may match traffic of both @closid and @rmid, or @rmid * only. @@ -538,7 +538,7 @@ void resctrl_offline_cpu(unsigned int cpu); * Return: * 0 on success, or -EIO, -EINVAL etc on error. */ -int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, u32 closid, u32 rmid, enum resctrl_event_id eventid, u64 *val, void *arch_mon_ctx); =20 diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 5e52269b391e..9912b774a580 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -106,24 +106,26 @@ struct mon_data { * resource group then its event count is summed with the count from all * its child resource groups. * @r: Resource describing the properties of the event being read. - * @d: Domain that the counter should be read from. If NULL then sum all - * domains in @r sharing L3 @ci.id + * @hdr: Header of domain that the counter should be read from. If NULL = then + * sum all domains in @r sharing L3 @ci.id * @evtid: Which monitor event to read. * @first: Initialize MBM counter when true. - * @ci: Cacheinfo for L3. Only set when @d is NULL. Used when summing d= omains. + * @ci: Cacheinfo for L3. Only set when @hdr is NULL. Used when summing + * domains. * @is_mbm_cntr: true if "mbm_event" counter assignment mode is enabled an= d it * is an MBM event. * @err: Error encountered when reading counter. - * @val: Returned value of event counter. If @rgrp is a parent resource = group, - * @val includes the sum of event counts from its child resource groups. - * If @d is NULL, @val includes the sum of all domains in @r sharing @c= i.id, - * (summed across child resource groups if @rgrp is a parent resource g= roup). + * @val: Returned value of event counter. If @rgrp is a parent resource + * group, @val includes the sum of event counts from its child + * resource groups. If @hdr is NULL, @val includes the sum of all + * domains in @r sharing @ci.id, (summed across child resource groups + * if @rgrp is a parent resource group). * @arch_mon_ctx: Hardware monitor allocated for this read request (MPAM o= nly). */ struct rmid_read { struct rdtgroup *rgrp; struct rdt_resource *r; - struct rdt_mon_domain *d; + struct rdt_domain_hdr *hdr; enum resctrl_event_id evtid; bool first; struct cacheinfo *ci; diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index dffcc8307500..3da970ea1903 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -238,19 +238,25 @@ static u64 get_corrected_val(struct rdt_resource *r, = struct rdt_mon_domain *d, return chunks * hw_res->mon_scale; } =20 -int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, u32 unused, u32 rmid, enum resctrl_event_id eventid, u64 *val, void *ignored) { - struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); - int cpu =3D cpumask_any(&d->hdr.cpu_mask); + struct rdt_hw_mon_domain *hw_dom; struct arch_mbm_state *am; + struct rdt_mon_domain *d; u64 msr_val; u32 prmid; + int cpu; int ret; =20 resctrl_arch_rmid_read_context_check(); + if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) + return -EINVAL; =20 + d =3D container_of(hdr, struct rdt_mon_domain, hdr); + hw_dom =3D resctrl_to_arch_mon_dom(d); + cpu =3D cpumask_any(&hdr->cpu_mask); prmid =3D logical_rmid_to_physical_rmid(cpu, rmid); ret =3D __rmid_read_phys(prmid, eventid, &msr_val); =20 diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 3154cdc98a31..9242a2982e77 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -554,25 +554,18 @@ void mon_event_read(struct rmid_read *rr, struct rdt_= resource *r, struct rdt_domain_hdr *hdr, struct rdtgroup *rdtgrp, cpumask_t *cpumask, int evtid, int first) { - struct rdt_mon_domain *d =3D NULL; int cpu; =20 /* When picking a CPU from cpu_mask, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); =20 - if (hdr) { - if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) - return; - d =3D container_of(hdr, struct rdt_mon_domain, hdr); - } - /* * Setup the parameters to pass to mon_event_count() to read the data. */ rr->rgrp =3D rdtgrp; rr->evtid =3D evtid; rr->r =3D r; - rr->d =3D d; + rr->hdr =3D hdr; rr->first =3D first; if (resctrl_arch_mbm_cntr_assign_enabled(r) && resctrl_is_mbm_event(evtid)) { diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index 179962a81362..7765491ddb4c 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -159,7 +159,7 @@ void __check_limbo(struct rdt_mon_domain *d, bool force= _free) break; =20 entry =3D __rmid_entry(idx); - if (resctrl_arch_rmid_read(r, d, entry->closid, entry->rmid, + if (resctrl_arch_rmid_read(r, &d->hdr, entry->closid, entry->rmid, QOS_L3_OCCUP_EVENT_ID, &val, arch_mon_ctx)) { rmid_dirty =3D true; @@ -421,11 +421,16 @@ static int __l3_mon_event_count(struct rdtgroup *rdtg= rp, struct rmid_read *rr) struct rdt_mon_domain *d; int cntr_id =3D -ENOENT; struct mbm_state *m; - int err, ret; u64 tval =3D 0; =20 + if (!domain_header_is_valid(rr->hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)= ) { + rr->err =3D -EIO; + return -EINVAL; + } + d =3D container_of(rr->hdr, struct rdt_mon_domain, hdr); + if (rr->is_mbm_cntr) { - cntr_id =3D mbm_cntr_get(rr->r, rr->d, rdtgrp, rr->evtid); + cntr_id =3D mbm_cntr_get(rr->r, d, rdtgrp, rr->evtid); if (cntr_id < 0) { rr->err =3D -ENOENT; return -EINVAL; @@ -434,32 +439,41 @@ static int __l3_mon_event_count(struct rdtgroup *rdtg= rp, struct rmid_read *rr) =20 if (rr->first) { if (rr->is_mbm_cntr) - resctrl_arch_reset_cntr(rr->r, rr->d, closid, rmid, cntr_id, rr->evtid); + resctrl_arch_reset_cntr(rr->r, d, closid, rmid, cntr_id, rr->evtid); else - resctrl_arch_reset_rmid(rr->r, rr->d, closid, rmid, rr->evtid); - m =3D get_mbm_state(rr->d, closid, rmid, rr->evtid); + resctrl_arch_reset_rmid(rr->r, d, closid, rmid, rr->evtid); + m =3D get_mbm_state(d, closid, rmid, rr->evtid); if (m) memset(m, 0, sizeof(struct mbm_state)); return 0; } =20 - if (rr->d) { - /* Reading a single domain, must be on a CPU in that domain. */ - if (!cpumask_test_cpu(cpu, &rr->d->hdr.cpu_mask)) - return -EINVAL; - if (rr->is_mbm_cntr) - rr->err =3D resctrl_arch_cntr_read(rr->r, rr->d, closid, rmid, cntr_id, - rr->evtid, &tval); - else - rr->err =3D resctrl_arch_rmid_read(rr->r, rr->d, closid, rmid, - rr->evtid, &tval, rr->arch_mon_ctx); - if (rr->err) - return rr->err; + /* Reading a single domain, must be on a CPU in that domain. */ + if (!cpumask_test_cpu(cpu, &d->hdr.cpu_mask)) + return -EINVAL; + if (rr->is_mbm_cntr) + rr->err =3D resctrl_arch_cntr_read(rr->r, d, closid, rmid, cntr_id, + rr->evtid, &tval); + else + rr->err =3D resctrl_arch_rmid_read(rr->r, rr->hdr, closid, rmid, + rr->evtid, &tval, rr->arch_mon_ctx); + if (rr->err) + return rr->err; =20 - rr->val +=3D tval; + rr->val +=3D tval; =20 - return 0; - } + return 0; +} + +static int __l3_mon_event_count_sum(struct rdtgroup *rdtgrp, struct rmid_r= ead *rr) +{ + int cpu =3D smp_processor_id(); + u32 closid =3D rdtgrp->closid; + u32 rmid =3D rdtgrp->mon.rmid; + struct rdt_mon_domain *d; + int cntr_id =3D -ENOENT; + u64 tval =3D 0; + int err, ret; =20 /* Summing domains that share a cache, must be on a CPU for that cache. */ if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) @@ -480,7 +494,7 @@ static int __l3_mon_event_count(struct rdtgroup *rdtgrp= , struct rmid_read *rr) err =3D resctrl_arch_cntr_read(rr->r, d, closid, rmid, cntr_id, rr->evtid, &tval); else - err =3D resctrl_arch_rmid_read(rr->r, d, closid, rmid, + err =3D resctrl_arch_rmid_read(rr->r, &d->hdr, closid, rmid, rr->evtid, &tval, rr->arch_mon_ctx); if (!err) { rr->val +=3D tval; @@ -498,8 +512,10 @@ static int __mon_event_count(struct rdtgroup *rdtgrp, = struct rmid_read *rr) { switch (rr->r->rid) { case RDT_RESOURCE_L3: - return __l3_mon_event_count(rdtgrp, rr); - + if (rr->hdr) + return __l3_mon_event_count(rdtgrp, rr); + else + return __l3_mon_event_count_sum(rdtgrp, rr); default: rr->err =3D -EINVAL; return -EINVAL; @@ -523,9 +539,13 @@ static void mbm_bw_count(struct rdtgroup *rdtgrp, stru= ct rmid_read *rr) u64 cur_bw, bytes, cur_bytes; u32 closid =3D rdtgrp->closid; u32 rmid =3D rdtgrp->mon.rmid; + struct rdt_mon_domain *d; struct mbm_state *m; =20 - m =3D get_mbm_state(rr->d, closid, rmid, rr->evtid); + if (!domain_header_is_valid(rr->hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) + return; + d =3D container_of(rr->hdr, struct rdt_mon_domain, hdr); + m =3D get_mbm_state(d, closid, rmid, rr->evtid); if (WARN_ON_ONCE(!m)) return; =20 @@ -698,7 +718,7 @@ static void mbm_update_one_event(struct rdt_resource *r= , struct rdt_mon_domain * struct rmid_read rr =3D {0}; =20 rr.r =3D r; - rr.d =3D d; + rr.hdr =3D &d->hdr; rr.evtid =3D evtid; if (resctrl_arch_mbm_cntr_assign_enabled(r)) { rr.is_mbm_cntr =3D true; --=20 2.51.1