From nobody Tue Dec 2 00:25:41 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 032CF1A285; Mon, 24 Nov 2025 16:32:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764001969; cv=none; b=DAN8nbDnYvdtoobJIwLfGz716nQgB/VRAwRcb6qkCZstQJkKrDfCAN70yL5l5nf/tIXaDaJwsTp2EwgHyVAdcEZyZGWh4flFsSIHsSzbvLVBpRPEYj2sT9xWeI6becVcgRPfVe/9HXAmtjIYed1/s5xMOS1aFbtQT59YA5adU5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764001969; c=relaxed/simple; bh=g7mlGe76mNaw/xOZJ6E1PI1pNY6kIC2FIUf9CvUkl0o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I1jZuMYEFR1jc2zhCQIK+cbObn/AAIDd2NtzgDXp0QcVPgFoZkEKqscaJ7BN+ltmPFGABXIX373Xlf1PLWuJXATF4fzzl1bWrNljjJOyt6ToHFcZ30nmAQTxA7kaRLeCqprLVoA9Q6NLe+Ly+c1tMq5PTffcf2qv19RUtCZmag8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=fc7uAUCe; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="fc7uAUCe" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id A19C925E88; Mon, 24 Nov 2025 17:32:44 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id ADK_3Zy4OxAN; Mon, 24 Nov 2025 17:32:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1764001963; bh=g7mlGe76mNaw/xOZJ6E1PI1pNY6kIC2FIUf9CvUkl0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fc7uAUCe/uFQ/AEcalCDLoOJJydOnry3z85zcw+NByVSYGLcyjmCerwjv41UBRXwM yjMdyDV3jvqwStlIwg5fkF5YZ6JR1q9fCf9C7YTgo/kuj2EiST5Pdil9O/R/kHAJyV 6WcGs7c3GFCeo/f7E7bwT9lTRHycJofC2Rits5WNWwn15s/fKwE9eV9178q975L7N+ WQcuJnhIqdYdvaqlUsv6I+gZ1DSeBkNtA68EDGhVvxhKtwRf5icWMFsDSIBD8VwsCs dTfu3V6W54VVtwX5MhfMPOkZuVpYLAgVlpBcedB/uBTRXQcVcT70X5j1YocvLkZq5s IvP306ryTE/9Q== From: Yao Zi To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Mingcong Bai , Kexy Biscuit Subject: [PATCH net-next v3 1/3] net: phy: motorcomm: Support YT8531S PHY in YT6801 Ethernet controller Date: Mon, 24 Nov 2025 16:32:09 +0000 Message-ID: <20251124163211.54994-2-ziyao@disroot.org> In-Reply-To: <20251124163211.54994-1-ziyao@disroot.org> References: <20251124163211.54994-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" YT6801's internal PHY is confirmed as a GMII-capable variant of YT8531S by a previous series[1] and reading PHY ID. Add support for PHY_INTERFACE_MODE_GMII for YT8531S to allow the Ethernet driver to reuse the PHY code for its internal PHY. Link: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@moto= r-comm.com/ # [1] Co-developed-by: Frank Sae Signed-off-by: Frank Sae Signed-off-by: Yao Zi --- drivers/net/phy/motorcomm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 89b5b19a9bd2..b751fbc6711a 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -910,6 +910,10 @@ static int ytphy_rgmii_clk_delay_config(struct phy_dev= ice *phydev) val |=3D FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); break; + case PHY_INTERFACE_MODE_GMII: + if (phydev->drv->phy_id !=3D PHY_ID_YT8531S) + return -EOPNOTSUPP; + break; default: /* do not support other modes */ return -EOPNOTSUPP; } --=20 2.51.2 From nobody Tue Dec 2 00:25:41 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EB16298987; Mon, 24 Nov 2025 16:32:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764001979; cv=none; b=jih7RiFxRhyeV2N4/3FX2J7qPpWV9QCYrO7H98OdGNs8Lg1wF3Abzqp8AwP8s/ojhJe2aEpDhgwTGzAb6W5OvYqLRhAHMc12YFqhDmthUNmFU0p4SKxxnRPKngkodc/L8gvLMXQM8aDruFV8ftsFrZxrB9vsmsGhUkOR8wLM9Js= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764001979; c=relaxed/simple; bh=OqtyhI4ye/Qmlk92ZBFLwMSfrEiO3Lq1YDIDpXMhqzo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A/cHwfA0wQydy0I6j893OC6P+VhVOGlY9gDd15Sx5+gZwQ78JeL+AXmNGXY9Nw2GaaGAdg1YJZytR6k28iTyedmCx1/d8veHUe/iCHAvrVrzMESPIpQiFhIGUaCd1cXEMudRJpYai3JZF0NXvroY9tsn6xOevgWNE9jVGr4/oDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Hcb964wv; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Hcb964wv" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B0E0825F8D; Mon, 24 Nov 2025 17:32:55 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id yDVRspZZvPm2; Mon, 24 Nov 2025 17:32:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1764001974; bh=OqtyhI4ye/Qmlk92ZBFLwMSfrEiO3Lq1YDIDpXMhqzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Hcb964wvwD/wpgxcQCTVvrlzHW6gJbnM6VaWJYdOhzDiPurwTndTCKDF/D4ODD+61 UAnNEreTKPxYOCDRTvssEgV38KxfNqEtos+ErNVGAHcs1H0fPjwoejBllnjxdBdD3x OYJAak91vfM6RTyKsduN8TMfF9PGfGiwxNeqRsG4lv9vqeMquCZDwEu4Kru+0rhz1b ojk+aAvzX7uaABYdnm06d9vf9yWx/wSOaUCl5fGczpqkcBeigY6L86jduZ8Zx2DaLm cloCEyqmYEe1BzpmEZU/CLC8NI4s7JIOW9cRYzltMhT9pzW4+9jhUX5hWHGzclFHFW gwxhXL3rcIyTg== From: Yao Zi To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Mingcong Bai , Kexy Biscuit , Runhua He , Xi Ruoyao Subject: [PATCH net-next v3 2/3] net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller Date: Mon, 24 Nov 2025 16:32:10 +0000 Message-ID: <20251124163211.54994-3-ziyao@disroot.org> In-Reply-To: <20251124163211.54994-1-ziyao@disroot.org> References: <20251124163211.54994-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Motorcomm YT6801 is a PCIe ethernet controller based on DWMAC4 IP. It integrates an GbE phy, supporting WOL, VLAN tagging and various types of offloading. It ships an on-chip eFuse for storing various vendor configuration, including MAC address. This patch adds basic glue code for the controller, allowing it to be set up and transmit data at a reasonable speed. Features like WOL could be implemented in the future. Signed-off-by: Yao Zi Tested-by: Mingcong Bai Tested-by: Runhua He Tested-by: Xi Ruoyao --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 9 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-motorcomm.c | 378 ++++++++++++++++++ 3 files changed, 388 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 907fe2e927f0..07088d03dbab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -374,6 +374,15 @@ config DWMAC_LOONGSON This selects the LOONGSON PCI bus support for the stmmac driver, Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bri= dge. =20 +config DWMAC_MOTORCOMM + tristate "Motorcomm PCI DWMAC support" + depends on PCI + select MOTORCOMM_PHY + select STMMAC_LIBPCI + help + This enables glue driver for Motorcomm DWMAC-based PCI Ethernet + controllers. Currently only YT6801 is supported. + config STMMAC_PCI tristate "STMMAC PCI bus support" depends on PCI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index 7bf528731034..c9263987ef8d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -48,4 +48,5 @@ obj-$(CONFIG_STMMAC_LIBPCI) +=3D stmmac_libpci.o obj-$(CONFIG_STMMAC_PCI) +=3D stmmac-pci.o obj-$(CONFIG_DWMAC_INTEL) +=3D dwmac-intel.o obj-$(CONFIG_DWMAC_LOONGSON) +=3D dwmac-loongson.o +obj-$(CONFIG_DWMAC_MOTORCOMM) +=3D dwmac-motorcomm.o stmmac-pci-objs:=3D stmmac_pci.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c b/driver= s/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c new file mode 100644 index 000000000000..fc87192af446 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DWMAC glue driver for Motorcomm PCI Ethernet controllers + * + * Copyright (c) 2025 Yao Zi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwmac4.h" +#include "stmmac.h" +#include "stmmac_libpci.h" + +#define DRIVER_NAME "dwmac-motorcomm" + +#define PCI_VENDOR_ID_MOTORCOMM 0x1f0a + +/* Register definition */ +#define EPHY_CTRL 0x1004 +/* Clearing this bit asserts resets for internal MDIO bus and PHY */ +#define EPHY_MDIO_PHY_RESET BIT(0) +#define OOB_WOL_CTRL 0x1010 +#define OOB_WOL_CTRL_DIS BIT(0) +#define MGMT_INT_CTRL0 0x1100 +#define MGMT_INT_CTRL0_MASK GENMASK(31, 16) +#define MGMT_INT_CTRL0_MASK_RXCH GENMASK(3, 0) +#define MGMT_INT_CTRL0_MASK_TXCH BIT(4) +#define MGMT_INT_CTRL0_MASK_MISC BIT(5) +#define INT_MODERATION 0x1108 +#define INT_MODERATION_RX GENMASK(11, 0) +#define INT_MODERATION_TX GENMASK(27, 16) +#define EFUSE_OP_CTRL_0 0x1500 +#define EFUSE_OP_MODE GENMASK(1, 0) +#define EFUSE_OP_ROW_READ 0x1 +#define EFUSE_OP_START BIT(2) +#define EFUSE_OP_ADDR GENMASK(15, 8) +#define EFUSE_OP_CTRL_1 0x1504 +#define EFUSE_OP_DONE BIT(1) +#define EFUSE_OP_RD_DATA GENMASK(31, 24) +#define SYS_RESET 0x152c +#define SYS_RESET_RESET BIT(31) +#define GMAC_OFFSET 0x2000 + +/* Constants */ +#define EFUSE_READ_TIMEOUT_US 20000 +#define EFUSE_PATCH_REGION_OFFSET 18 +#define EFUSE_PATCH_MAX_NUM 39 +#define EFUSE_ADDR_MACA0LR 0x1520 +#define EFUSE_ADDR_MACA0HR 0x1524 + +struct motorcomm_efuse_patch { + __le16 addr; + __le32 data; +} __packed; + +struct dwmac_motorcomm_priv { + void __iomem *base; + struct device *dev; +}; + +static int motorcomm_efuse_read_byte(struct dwmac_motorcomm_priv *priv, + u8 offset, u8 *byte) +{ + u32 reg; + int ret; + + writel(FIELD_PREP(EFUSE_OP_MODE, EFUSE_OP_ROW_READ) | + FIELD_PREP(EFUSE_OP_ADDR, offset) | + EFUSE_OP_START, priv->base + EFUSE_OP_CTRL_0); + + ret =3D readl_poll_timeout(priv->base + EFUSE_OP_CTRL_1, + reg, reg & EFUSE_OP_DONE, 2000, + EFUSE_READ_TIMEOUT_US); + + *byte =3D FIELD_GET(EFUSE_OP_RD_DATA, reg); + + return ret; +} + +static int motorcomm_efuse_read_patch(struct dwmac_motorcomm_priv *priv, + u8 index, + struct motorcomm_efuse_patch *patch) +{ + u8 buf[sizeof(*patch)], offset; + int i, ret; + + for (i =3D 0; i < sizeof(*patch); i++) { + offset =3D EFUSE_PATCH_REGION_OFFSET + sizeof(*patch) * index + i; + + ret =3D motorcomm_efuse_read_byte(priv, offset, &buf[i]); + if (ret) + return ret; + } + + memcpy(patch, buf, sizeof(*patch)); + + return 0; +} + +static int motorcomm_efuse_get_patch_value(struct dwmac_motorcomm_priv *pr= iv, + u16 addr, u32 *value) +{ + struct motorcomm_efuse_patch patch; + int i, ret; + + for (i =3D 0; i < EFUSE_PATCH_MAX_NUM; i++) { + ret =3D motorcomm_efuse_read_patch(priv, i, &patch); + if (ret) + return ret; + + if (patch.addr =3D=3D 0) { + return -ENOENT; + } else if (le16_to_cpu(patch.addr) =3D=3D addr) { + *value =3D le32_to_cpu(patch.data); + return 0; + } + } + + return -ENOENT; +} + +static int motorcomm_efuse_read_mac(struct dwmac_motorcomm_priv *priv, u8 = *mac) +{ + u32 maca0lr, maca0hr; + int ret; + + ret =3D motorcomm_efuse_get_patch_value(priv, EFUSE_ADDR_MACA0LR, + &maca0lr); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to read maca0lr from eFuse\n"); + + ret =3D motorcomm_efuse_get_patch_value(priv, EFUSE_ADDR_MACA0HR, + &maca0hr); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to read maca0hr from eFuse\n"); + + mac[0] =3D FIELD_GET(GENMASK(15, 8), maca0hr); + mac[1] =3D FIELD_GET(GENMASK(7, 0), maca0hr); + mac[2] =3D FIELD_GET(GENMASK(31, 24), maca0lr); + mac[3] =3D FIELD_GET(GENMASK(23, 16), maca0lr); + mac[4] =3D FIELD_GET(GENMASK(15, 8), maca0lr); + mac[5] =3D FIELD_GET(GENMASK(7, 0), maca0lr); + + return 0; +} + +static void motorcomm_deassert_mdio_phy_reset(struct dwmac_motorcomm_priv = *priv) +{ + u32 reg =3D readl(priv->base + EPHY_CTRL); + + reg |=3D EPHY_MDIO_PHY_RESET; + + writel(reg, priv->base + EPHY_CTRL); +} + +static void motorcomm_reset(struct dwmac_motorcomm_priv *priv) +{ + u32 reg =3D readl(priv->base + SYS_RESET); + + reg &=3D ~SYS_RESET_RESET; + writel(reg, priv->base + SYS_RESET); + + reg |=3D SYS_RESET_RESET; + writel(reg, priv->base + SYS_RESET); + + motorcomm_deassert_mdio_phy_reset(priv); +} + +static void motorcomm_init(struct dwmac_motorcomm_priv *priv) +{ + writel(0x0, priv->base + MGMT_INT_CTRL0); + + writel(FIELD_PREP(INT_MODERATION_RX, 200) | + FIELD_PREP(INT_MODERATION_TX, 200), + priv->base + INT_MODERATION); + + /* + * OOB WOL must be disabled during normal operation, or DMA interrupts + * cannot be delivered to the host. + */ + writel(OOB_WOL_CTRL_DIS, priv->base + OOB_WOL_CTRL); +} + +static int motorcomm_resume(struct device *dev, void *bsp_priv) +{ + struct dwmac_motorcomm_priv *priv =3D bsp_priv; + int ret; + + ret =3D stmmac_pci_plat_resume(dev, bsp_priv); + if (ret) + return ret; + + /* + * When recovering from D3hot, EPHY_MDIO_PHY_RESET is automatically + * asserted, and must be deasserted for normal operation. + */ + motorcomm_deassert_mdio_phy_reset(priv); + motorcomm_init(priv); + + return 0; +} + +static struct plat_stmmacenet_data * +motorcomm_default_plat_data(struct pci_dev *pdev) +{ + struct plat_stmmacenet_data *plat; + struct device *dev =3D &pdev->dev; + + plat =3D stmmac_plat_dat_alloc(dev); + if (!plat) + return NULL; + + plat->mdio_bus_data =3D devm_kzalloc(dev, sizeof(*plat->mdio_bus_data), + GFP_KERNEL); + if (!plat->mdio_bus_data) + return NULL; + + plat->dma_cfg =3D devm_kzalloc(dev, sizeof(*plat->dma_cfg), GFP_KERNEL); + if (!plat->dma_cfg) + return NULL; + + plat->axi =3D devm_kzalloc(dev, sizeof(*plat->axi), GFP_KERNEL); + if (!plat->axi) + return NULL; + + plat->dma_cfg->pbl =3D DEFAULT_DMA_PBL; + plat->dma_cfg->pblx8 =3D true; + plat->dma_cfg->txpbl =3D 32; + plat->dma_cfg->rxpbl =3D 32; + plat->dma_cfg->eame =3D true; + plat->dma_cfg->mixed_burst =3D true; + + plat->axi->axi_wr_osr_lmt =3D 1; + plat->axi->axi_rd_osr_lmt =3D 1; + plat->axi->axi_mb =3D true; + plat->axi->axi_blen_regval =3D DMA_AXI_BLEN4 | DMA_AXI_BLEN8 | + DMA_AXI_BLEN16 | DMA_AXI_BLEN32; + + plat->bus_id =3D pci_dev_id(pdev); + plat->phy_interface =3D PHY_INTERFACE_MODE_GMII; + /* + * YT6801 requires an 25MHz clock input/oscillator to function, which + * is likely the source of CSR clock. + */ + plat->clk_csr =3D STMMAC_CSR_20_35M; + plat->tx_coe =3D 1; + plat->rx_coe =3D 1; + plat->clk_ref_rate =3D 125000000; + plat->core_type =3D DWMAC_CORE_GMAC4; + plat->suspend =3D stmmac_pci_plat_suspend; + plat->resume =3D motorcomm_resume; + plat->flags =3D STMMAC_FLAG_TSO_EN | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP; + + return plat; +} + +static int motorcomm_setup_irq(struct pci_dev *pdev, + struct stmmac_resources *res, + struct plat_stmmacenet_data *plat) +{ + int ret; + + ret =3D pci_alloc_irq_vectors(pdev, 6, 6, PCI_IRQ_MSIX); + if (ret > 0) { + res->rx_irq[0] =3D pci_irq_vector(pdev, 0); + res->tx_irq[0] =3D pci_irq_vector(pdev, 4); + res->irq =3D pci_irq_vector(pdev, 5); + + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + + return 0; + } + + dev_info(&pdev->dev, "failed to allocate MSI-X vector: %d\n", ret); + dev_info(&pdev->dev, "try MSI instead\n"); + + ret =3D pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed to allocate MSI\n"); + + res->irq =3D pci_irq_vector(pdev, 0); + + return 0; +} + +static int motorcomm_probe(struct pci_dev *pdev, const struct pci_device_i= d *id) +{ + struct plat_stmmacenet_data *plat; + struct dwmac_motorcomm_priv *priv; + struct stmmac_resources res =3D {}; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + + plat =3D motorcomm_default_plat_data(pdev); + if (!plat) + return -ENOMEM; + + plat->bsp_priv =3D priv; + + ret =3D pcim_enable_device(pdev); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to enable device\n"); + + priv->base =3D pcim_iomap_region(pdev, 0, DRIVER_NAME); + if (IS_ERR(priv->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base), + "failed to map IO region\n"); + + pci_set_master(pdev); + + motorcomm_reset(priv); + + ret =3D motorcomm_efuse_read_mac(priv, res.mac); + if (ret =3D=3D -ENOENT) { + dev_warn(&pdev->dev, "eFuse contains no valid MAC address\n"); + dev_warn(&pdev->dev, "fallback to random MAC address\n"); + + memset(res.mac, 0, sizeof(res.mac)); + } else if (ret) { + return dev_err_probe(&pdev->dev, ret, + "failed to read MAC address from eFuse\n"); + } + + ret =3D motorcomm_setup_irq(pdev, &res, plat); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to setup IRQ\n"); + + motorcomm_init(priv); + + res.addr =3D priv->base + GMAC_OFFSET; + + return stmmac_dvr_probe(&pdev->dev, plat, &res); +} + +static void motorcomm_remove(struct pci_dev *pdev) +{ + stmmac_dvr_remove(&pdev->dev); + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id dwmac_motorcomm_pci_id_table[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_MOTORCOMM, 0x6801) }, + { }, +}; +MODULE_DEVICE_TABLE(pci, dwmac_motorcomm_pci_id_table); + +static struct pci_driver dwmac_motorcomm_pci_driver =3D { + .name =3D DRIVER_NAME, + .id_table =3D dwmac_motorcomm_pci_id_table, + .probe =3D motorcomm_probe, + .remove =3D motorcomm_remove, + .driver =3D { + .pm =3D &stmmac_simple_pm_ops, + }, +}; + +module_pci_driver(dwmac_motorcomm_pci_driver); + +MODULE_DESCRIPTION("DWMAC glue driver for Motorcomm PCI Ethernet controlle= rs"); +MODULE_AUTHOR("Yao Zi "); +MODULE_LICENSE("GPL"); --=20 2.51.2 From nobody Tue Dec 2 00:25:41 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEE2A27F72C; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Mingcong Bai , Kexy Biscuit Subject: [PATCH net-next v3 3/3] MAINTAINERS: Assign myself as maintainer of Motorcomm DWMAC glue driver Date: Mon, 24 Nov 2025 16:32:11 +0000 Message-ID: <20251124163211.54994-4-ziyao@disroot.org> In-Reply-To: <20251124163211.54994-1-ziyao@disroot.org> References: <20251124163211.54994-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" I volunteer to maintain the DWMAC glue driver for Motorcomm ethernet controllers. Signed-off-by: Yao Zi --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc0343b10489..b9bbf39e61ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17621,6 +17621,12 @@ F: drivers/most/ F: drivers/staging/most/ F: include/linux/most.h =20 +MOTORCOMM DWMAC GLUE DRIVER +M: Yao Zi +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c + MOTORCOMM PHY DRIVER M: Frank L: netdev@vger.kernel.org --=20 2.51.2