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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2025 11:59:43.2281 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be93d6d8-c89c-4abd-f6b7-08de2b50f47e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7575 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Speculative prefetches from CPU to GPU memory until the GPU is ready after reset can cause harmless corrected RAS events to be logged on Grace systems. It is thus preferred that the mapping not be re-established until the GPU is ready post reset. The GPU readiness can be checked through BAR0 registers similar to the checking at the time of device probe. It can take several seconds for the GPU to be ready. So it is desirable that the time overlaps as much of the VM startup as possible to reduce impact on the VM bootup time. The GPU readiness state is thus checked on the first fault/huge_fault request or read/write access which amortizes the GPU readiness time. The first fault and read/write checks the GPU state when the reset_done flag - which denotes whether the GPU has just been reset. The memory_lock is taken across map/access to avoid races with GPU reset. cc: Alex Williamson cc: Jason Gunthorpe cc: Vikram Sethi Suggested-by: Alex Williamson Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/nvgrace-gpu/main.c | 79 ++++++++++++++++++++++++++--- 1 file changed, 72 insertions(+), 7 deletions(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index bef9f25bf8f3..fbc19fe688ca 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -104,6 +104,17 @@ static int nvgrace_gpu_open_device(struct vfio_device = *core_vdev) mutex_init(&nvdev->remap_lock); } =20 + /* + * GPU readiness is checked by reading the BAR0 registers. + * + * ioremap BAR0 to ensure that the BAR0 mapping is present before + * register reads on first fault before establishing any GPU + * memory mapping. + */ + ret =3D vfio_pci_core_setup_barmap(vdev, 0); + if (ret) + return ret; + vfio_pci_core_finish_enable(vdev); =20 return 0; @@ -150,6 +161,26 @@ static int nvgrace_gpu_wait_device_ready(void __iomem = *io) return ret; } =20 +static int +nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev) +{ + struct vfio_pci_core_device *vdev =3D &nvdev->core_device; + int ret; + + lockdep_assert_held_read(&vdev->memory_lock); + + if (!nvdev->reset_done) + return 0; + + ret =3D nvgrace_gpu_wait_device_ready(vdev->barmap[0]); + if (ret) + return ret; + + nvdev->reset_done =3D false; + + return 0; +} + static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(struct vm_fault *vmf, unsigned int order) { @@ -173,8 +204,18 @@ static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(stru= ct vm_fault *vmf, pfn & ((1 << order) - 1))) return VM_FAULT_FALLBACK; =20 - scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) + scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) { + /* + * If the GPU memory is accessed by the CPU while the GPU is + * not ready after reset, it can cause harmless corrected RAS + * events to be logged. Make sure the GPU is ready before + * establishing the mappings. + */ + if (nvgrace_gpu_check_device_ready(nvdev)) + return ret; + ret =3D vfio_pci_vmf_insert_pfn(vmf, pfn, order); + } =20 return ret; } @@ -593,9 +634,21 @@ nvgrace_gpu_read_mem(struct nvgrace_gpu_pci_core_devic= e *nvdev, else mem_count =3D min(count, memregion->memlength - (size_t)offset); =20 - ret =3D nvgrace_gpu_map_and_read(nvdev, buf, mem_count, ppos); - if (ret) - return ret; + scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) { + /* + * If the GPU memory is accessed by the CPU while the GPU is + * not ready after reset, it can cause harmless corrected RAS + * events to be logged. Make sure the GPU is ready before + * establishing the mappings. + */ + ret =3D nvgrace_gpu_check_device_ready(nvdev); + if (ret) + return ret; + + ret =3D nvgrace_gpu_map_and_read(nvdev, buf, mem_count, ppos); + if (ret) + return ret; + } =20 /* * Only the device memory present on the hardware is mapped, which may @@ -713,9 +766,21 @@ nvgrace_gpu_write_mem(struct nvgrace_gpu_pci_core_devi= ce *nvdev, */ mem_count =3D min(count, memregion->memlength - (size_t)offset); =20 - ret =3D nvgrace_gpu_map_and_write(nvdev, buf, mem_count, ppos); - if (ret) - return ret; + scoped_guard(rwsem_read, &nvdev->core_device.memory_lock) { + /* + * If the GPU memory is accessed by the CPU while the GPU is + * not ready after reset, it can cause harmless corrected RAS + * events to be logged. Make sure the GPU is ready before + * establishing the mappings. + */ + ret =3D nvgrace_gpu_check_device_ready(nvdev); + if (ret) + return ret; + + ret =3D nvgrace_gpu_map_and_write(nvdev, buf, mem_count, ppos); + if (ret) + return ret; + } =20 exitfn: *ppos +=3D count; --=20 2.34.1