From nobody Tue Dec 2 00:46:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D5E478F2E; Mon, 24 Nov 2025 06:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763967469; cv=none; b=s3zK6MtSt65d9R3SsLMsjORA36yxBMciA8wHieKm0Beslza3m4m3jjVf792hJFOEaRW/ORWL4/VMdj2yPF96JmDSnPa4i0svGAikyfm2gZHqIpLmYOi6y01EX9L1RkIz+QND+EeRbCpcHZ+538JozWrimQUMylcXOTdQL5s1BOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763967469; c=relaxed/simple; bh=n2sfG3NsoWQ4+FdYe4rlPhtXRST35Vy7SKPnFJ1RVIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ftx6iia2nxWoa57dq8cRunrMczxlsDI+Qmtjr56Pg/JWpoYcJl4LXQeOaSPQeSrdqT0zwGiZ0ORZn5ad7EPBKTOM7wcIv3HcU5fnmq7/qIrgkBRYpbLGSZ9a55aqCiRME1bewy2cqNK2guHPHBrwhrzG3MdvcvM9huGgM//4HEk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C1doaHe0; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C1doaHe0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763967468; x=1795503468; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n2sfG3NsoWQ4+FdYe4rlPhtXRST35Vy7SKPnFJ1RVIY=; b=C1doaHe0jg9IRknh9lxOt3n5jFIBNfZPcCOKcQol/Zxtb2fWXgOFVxZv NoxnVGeeBuxWPsSBb1TUqYEsvKFgGe4p0jsQB4s3SLDab5rSBr86G6TMD qgnVkKYZS9iUhGiwfC6vkpE02u27FlO7sOxsYt6wuK2HyGxYJ/IMXd3JB d36QfS0piJl1zh1Q1VpmvDBHAxx8FDYiE8sjlI85J9LBRNh3hfuUkeBwa W2uFQxzwccI5rZ+WCaxA0kRxJs6fP0dgIoW1Fr/aHcBt2vmlRpMNy1G5S 2I31PCXAYJfCQTI9qUajjxgA5k2s6vhtjOsa5mrGYqQNu/INdG2njJOpg w==; X-CSE-ConnectionGUID: QCWotRnxRH6AlB4jmSgDlA== X-CSE-MsgGUID: e2wQ6iv5TAOFr8dS2ty1gA== X-IronPort-AV: E=McAfee;i="6800,10657,11622"; a="76286883" X-IronPort-AV: E=Sophos;i="6.20,222,1758610800"; d="scan'208";a="76286883" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2025 22:57:48 -0800 X-CSE-ConnectionGUID: PJVs6ygrTQK10VUjZ0ZX2g== X-CSE-MsgGUID: waoAaKkkTwGbQ2JSk/YT4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,222,1758610800"; d="scan'208";a="192272773" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2025 22:57:45 -0800 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , Jianfeng Gao , Yi Lai , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] EDAC/igen6: Add two Intel Amston Lake SoCs support Date: Mon, 24 Nov 2025 14:54:56 +0800 Message-ID: <20251124065457.3630949-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251124065457.3630949-1-qiuxu.zhuo@intel.com> References: <20251124065457.3630949-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Amston Lake SoCs with IBECC (In-Band ECC) capability share the same IBECC registers as Alder Lake-N SoCs. Add two new compute die IDs for Amston Lake SoC products to enable EDAC support. Tested-by: Jianfeng Gao Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 2fc59f9eed69..5d887a3115f0 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -246,6 +246,8 @@ static struct work_struct ecclog_work; =20 /* Compute did IDs for Amston Lake with IBECC */ #define DID_ASL_SKU1 0x464a +#define DID_ASL_SKU2 0x4646 +#define DID_ASL_SKU3 0x4652 =20 /* Compute die IDs for Raptor Lake-P with IBECC */ #define DID_RPL_P_SKU1 0xa706 @@ -618,6 +620,8 @@ static struct pci_device_id igen6_pci_tbl[] =3D { { PCI_VDEVICE(INTEL, DID_ADL_N_SKU12), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_AZB_SKU1), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_ASL_SKU1), (kernel_ulong_t)&adl_n_cfg }, + { PCI_VDEVICE(INTEL, DID_ASL_SKU2), (kernel_ulong_t)&adl_n_cfg }, + { PCI_VDEVICE(INTEL, DID_ASL_SKU3), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg }, --=20 2.43.0 From nobody Tue Dec 2 00:46:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB4F12DFA48; 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a="76286903" X-IronPort-AV: E=Sophos;i="6.20,222,1758610800"; d="scan'208";a="76286903" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2025 22:57:54 -0800 X-CSE-ConnectionGUID: uDLUk5UYTuibL4TWzgL7fg== X-CSE-MsgGUID: 9IEyQGG6TYiO3Vo3OFVvsw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,222,1758610800"; d="scan'208";a="192272779" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2025 22:57:52 -0800 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , Jianfeng Gao , Yi Lai , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] EDAC/igen6: Make masks of {MCHBAR, TOM, TOUUD, ECC_ERROR_LOG} configurable Date: Mon, 24 Nov 2025 14:54:57 +0800 Message-ID: <20251124065457.3630949-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251124065457.3630949-1-qiuxu.zhuo@intel.com> References: <20251124065457.3630949-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The masks used to retrieve base addresses from {MCHBAR, TOM, TOUUD, ECC_ERROR_LOG} registers can be CPU model-specific. Currently, igen6_edac hard-codes these masks with the most significant bit at 38, while some CPUs have extended the most significant bit to bit 41 or bit 45. Systems with more than 512GB (2^39) memory need this extension to get correct masks. But all CPUs currently supported by igen6_edac support max memory less than 512GB (e.g., max memory size for Raptor Lake systems is 192GB, for Alder Lake systems is 128GB, ...), which means the previous hard-coded most significant bit 38 still works properly. So backporting this patch to stable kernels is not necessary. To make these masks reflect the CPUs' real support and easily support future Intel client CPUs supported by igen6_edac that have more than 512GB memory, add four new fields to structure res_config to make these masks CPU model-specific and configure them properly. Tested-by: Jianfeng Gao Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 67 ++++++++++++++++++++++++++++++++------- 1 file changed, 55 insertions(+), 12 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 5d887a3115f0..db4aa9f581e3 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -79,15 +79,11 @@ #define ECC_ERROR_LOG_OFFSET (IBECC_BASE + res_cfg->ibecc_error_log_offse= t) #define ECC_ERROR_LOG_CE BIT_ULL(62) #define ECC_ERROR_LOG_UE BIT_ULL(63) -#define ECC_ERROR_LOG_ADDR_SHIFT 5 -#define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38) -#define ECC_ERROR_LOG_ADDR45(v) GET_BITFIELD(v, 5, 45) #define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61) =20 /* Host MMIO base address */ #define MCHBAR_OFFSET 0x48 #define MCHBAR_EN BIT_ULL(0) -#define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16) #define MCHBAR_SIZE 0x10000 =20 /* Parameters for the channel decode stage */ @@ -125,10 +121,21 @@ #define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6) #define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26) =20 +/* Non-constant mask variant of FIELD_GET() */ +#define field_get(mask, reg) (((reg) & (mask)) >> (ffs(mask) - 1)) + static struct res_config { bool machine_check; /* The number of present memory controllers. */ int num_imc; + /* Host MMIO configuration */ + u64 reg_mchbar_mask; + /* Top of memory */ + u64 reg_tom_mask; + /* Top of upper usable DRAM */ + u64 reg_touud_mask; + /* IBECC error log */ + u64 reg_eccerrlog_addr_mask; u32 imc_base; u32 cmf_base; u32 cmf_size; @@ -305,7 +312,8 @@ static int get_mchbar(struct pci_dev *pdev, u64 *mchbar) return -ENODEV; } =20 - *mchbar =3D MCHBAR_BASE(u.v); + *mchbar =3D u.v & res_cfg->reg_mchbar_mask; + edac_dbg(2, "MCHBAR 0x%llx (reg 0x%llx)\n", *mchbar, u.v); =20 return 0; } @@ -481,11 +489,15 @@ static u64 adl_err_addr_to_imc_addr(u64 eaddr, int mc) =20 static u64 rpl_p_err_addr(u64 ecclog) { - return ECC_ERROR_LOG_ADDR45(ecclog); + return field_get(res_cfg->reg_eccerrlog_addr_mask, ecclog); } =20 static struct res_config ehl_cfg =3D { .num_imc =3D 1, + .reg_mchbar_mask =3D GENMASK_ULL(38, 16), + .reg_tom_mask =3D GENMASK_ULL(38, 20), + .reg_touud_mask =3D GENMASK_ULL(38, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0x5000, .ibecc_base =3D 0xdc00, .ibecc_available =3D ehl_ibecc_available, @@ -496,6 +508,10 @@ static struct res_config ehl_cfg =3D { =20 static struct res_config icl_cfg =3D { .num_imc =3D 1, + .reg_mchbar_mask =3D GENMASK_ULL(38, 16), + .reg_tom_mask =3D GENMASK_ULL(38, 20), + .reg_touud_mask =3D GENMASK_ULL(38, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0x5000, .ibecc_base =3D 0xd800, .ibecc_error_log_offset =3D 0x170, @@ -507,6 +523,10 @@ static struct res_config icl_cfg =3D { static struct res_config tgl_cfg =3D { .machine_check =3D true, .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(38, 17), + .reg_tom_mask =3D GENMASK_ULL(38, 20), + .reg_touud_mask =3D GENMASK_ULL(38, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0x5000, .cmf_base =3D 0x11000, .cmf_size =3D 0x800, @@ -521,6 +541,10 @@ static struct res_config tgl_cfg =3D { static struct res_config adl_cfg =3D { .machine_check =3D true, .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(45, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x68, @@ -532,6 +556,10 @@ static struct res_config adl_cfg =3D { static struct res_config adl_n_cfg =3D { .machine_check =3D true, .num_imc =3D 1, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(45, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x68, @@ -543,6 +571,10 @@ static struct res_config adl_n_cfg =3D { static struct res_config rpl_p_cfg =3D { .machine_check =3D true, .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(45, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x68, @@ -555,6 +587,10 @@ static struct res_config rpl_p_cfg =3D { static struct res_config mtl_ps_cfg =3D { .machine_check =3D true, .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x170, @@ -566,6 +602,10 @@ static struct res_config mtl_ps_cfg =3D { static struct res_config mtl_p_cfg =3D { .machine_check =3D true, .num_imc =3D 2, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x170, @@ -577,6 +617,10 @@ static struct res_config mtl_p_cfg =3D { static struct res_config wcl_cfg =3D { .machine_check =3D true, .num_imc =3D 1, + .reg_mchbar_mask =3D GENMASK_ULL(41, 17), + .reg_tom_mask =3D GENMASK_ULL(41, 20), + .reg_touud_mask =3D GENMASK_ULL(41, 20), + .reg_eccerrlog_addr_mask =3D GENMASK_ULL(38, 5), .imc_base =3D 0xd800, .ibecc_base =3D 0xd400, .ibecc_error_log_offset =3D 0x170, @@ -908,8 +952,8 @@ static void ecclog_work_cb(struct work_struct *work) if (res_cfg->err_addr) eaddr =3D res_cfg->err_addr(node->ecclog); else - eaddr =3D ECC_ERROR_LOG_ADDR(node->ecclog) << - ECC_ERROR_LOG_ADDR_SHIFT; + eaddr =3D node->ecclog & res_cfg->reg_eccerrlog_addr_mask; + res.mc =3D node->mc; res.sys_addr =3D res_cfg->err_addr_to_sys_addr(eaddr, res.mc); res.imc_addr =3D res_cfg->err_addr_to_imc_addr(eaddr, res.mc); @@ -1129,8 +1173,7 @@ static int debugfs_u64_set(void *data, u64 val) =20 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); =20 - val >>=3D ECC_ERROR_LOG_ADDR_SHIFT; - ecclog =3D (val << ECC_ERROR_LOG_ADDR_SHIFT) | ECC_ERROR_LOG_CE; + ecclog =3D (val & res_cfg->reg_eccerrlog_addr_mask) | ECC_ERROR_LOG_CE; =20 if (!ecclog_gen_pool_add(0, ecclog)) irq_work_queue(&ecclog_irq_work); @@ -1196,7 +1239,7 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 = *mchbar) goto fail; } =20 - igen6_tom =3D u.v & GENMASK_ULL(38, 20); + igen6_tom =3D u.v & res_cfg->reg_tom_mask; =20 if (get_mchbar(pdev, mchbar)) goto fail; @@ -1207,7 +1250,7 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 = *mchbar) else if (pci_read_config_dword(pdev, TOUUD_OFFSET + 4, &u.v_hi)) edac_dbg(2, "Failed to read upper TOUUD\n"); else - igen6_touud =3D u.v & GENMASK_ULL(38, 20); + igen6_touud =3D u.v & res_cfg->reg_touud_mask; #endif =20 return 0; --=20 2.43.0