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However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly defined fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap --- drivers/firmware/qcom/qcom_scm.c | 62 ++++++++++++++++++++++++++++++++++++= +++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index e777b7cb9b127944fe112f453cae9cbc40c06cae..28979f95e51fbee94b84c1570a4= d88a76f72db4e 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -29,12 +29,18 @@ #include #include #include +#include =20 #include "qcom_scm.h" #include "qcom_tzmem.h" =20 static u32 download_mode; =20 +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2223,6 +2229,57 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); =20 +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 = virq) +{ + if (virq >=3D GIC_SPI_BASE && virq <=3D GIC_MAX_SPI) { + fwspec->param[0] =3D GIC_SPI; + fwspec->param[1] =3D virq - GIC_SPI_BASE; + } else if (virq >=3D GIC_ESPI_BASE && virq <=3D GIC_MAX_ESPI) { + fwspec->param[0] =3D GIC_ESPI; + fwspec->param[1] =3D virq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + fwspec->param[2] =3D IRQ_TYPE_EDGE_RISING; + fwspec->param_count =3D 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + struct device_node *parent_irq_node; + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq =3D res.result[1] & GENMASK(15, 0); + + ret =3D qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + parent_irq_node =3D of_irq_find_parent(scm->dev->of_node); + if (!parent_irq_node) + return -ENODEV; + + fwspec.fwnode =3D of_fwnode_handle(parent_irq_node); + + ret =3D irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2396,7 +2453,10 @@ static int qcom_scm_probe(struct platform_device *pd= ev) return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), "Failed to create the SCM memory pool\n"); =20 - irq =3D platform_get_irq_optional(pdev, 0); + irq =3D qcom_scm_get_waitq_irq(scm); + if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq !=3D -ENXIO) return irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index a56c8212cc0c41021e5a067d52b7d5dcc49107ea..8b1e2ea18a59ac143907a381b73= 236148bace189 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -152,6 +152,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 =20 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 --=20 2.34.1