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Sun, 23 Nov 2025 09:14:11 -0800 (PST) From: Guillaume La Roque Date: Sun, 23 Nov 2025 18:14:10 +0100 Subject: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251123-fixkhadas-v1-1-045348f0a4c2@baylibre.com> X-B4-Tracking: v=1; b=H4sIAOFAI2kC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDQyNj3bTMiuyMxJTEYt1kC5OURPMU82QT82QloPqColSgJNis6NjaWgB xAQqgWwAAAA== To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Anand Moon Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume La Roque X-Mailer: b4 0.14.1 The original addition of cache information for the Amlogic S922X SoC used the wrong next-level cache node for CPU cores 100 and 101, incorrectly referencing `l2_cache_l`. These cores actually belong to the big cluster and should reference `l2_cache_b`. Update the device tree accordingly. Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Aml= ogic S922X SoC") Signed-off-by: Guillaume La Roque Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/= dts/amlogic/meson-g12b.dtsi index f04efa828256..23358d94844c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -87,7 +87,7 @@ cpu100: cpu@100 { i-cache-line-size =3D <32>; i-cache-size =3D <0x8000>; i-cache-sets =3D <32>; - next-level-cache =3D <&l2_cache_l>; + next-level-cache =3D <&l2_cache_b>; #cooling-cells =3D <2>; }; =20 @@ -103,7 +103,7 @@ cpu101: cpu@101 { i-cache-line-size =3D <32>; i-cache-size =3D <0x8000>; i-cache-sets =3D <32>; - next-level-cache =3D <&l2_cache_l>; + next-level-cache =3D <&l2_cache_b>; #cooling-cells =3D <2>; }; =20 --- base-commit: 6a23ae0a96a600d1d12557add110e0bb6e32730c change-id: 20251123-fixkhadas-c84da7d7c47c Best regards, --=20 Guillaume La Roque