From nobody Tue Dec 2 01:26:24 2025 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44BC02E4254 for ; Fri, 21 Nov 2025 18:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763751344; cv=none; b=SxgXHRlGXs/rYCnx2WN4DsE6WOQn/IbGHFviGzjOmtAF+nmjOyKCuQl/Nz2lN6a/upb6ewFASEXW/xLvydEtoH2w6UqLEB/qpuBDx8DWnF+aBPtaixjgwo+CycPyaG9VaiHCI1pEY1Ddj6d+a6nE5LeQ6u6gTvbaX6jTn63dIz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763751344; c=relaxed/simple; bh=NCEIGYCRLDe5SO5QV/Sz8yL3ufMc+gjo3oK4TfY5XdU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GRBl2ECAIUDgLsZh8gmWox9fI1v/hGHtTNVkMy5YvIfhloI4ZLM1MjurExP6//zW/Lr71EmhfCuYn4qCJwhO8/Y3iGqVZhc6PrMUBGHxP2lW13djyWt0VXoU8X6ZCoPxo4ymELhXdFnmg+tFS5aL+6PW5Pkf5apR11NR/N2T5vo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=surriel.com; dkim=pass (2048-bit key) header.d=surriel.com header.i=@surriel.com header.b=VheqOwN6; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=surriel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=surriel.com header.i=@surriel.com header.b="VheqOwN6" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=surriel.com ; s=mail; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=A/tEc5tFrvTtBuLMXuLE+3Ir+qQmPEaILfulPI2BDOU=; b=VheqOwN6A2nhqQpeYKL3X+7bW4 oVtNF6AZIrS/xvOmeFyApFmstN2D+jPT8I5GrBf6IL6Rz0UH4BVH6zAc7qeqped0EUPzhe7CoyvVV NQQar/MYTER9IuKdSs3nAjWJhTZFQk21AXMc8N4+T1VmUkAfj1gG4uRFEiiTGOpWU3qV8OKywzvpg D8qT6uHRmzt07V2KuvF939mh1wXIDct2V+tldBrFe7gSTEkVGtD4hNTMfC98BbJ5+fEIjOj34Qz0e WRyo5RcMjfkA8AezN/s3fVFIo9I4TaRW/2Eg09a9LqZRhKu6zPuCq0KC0ODVPc7SsUxivt1USi7N/ vrIIiHJg==; Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1vMWI9-000000003i4-1QJt; Fri, 21 Nov 2025 13:55:34 -0500 From: Rik van Riel To: linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org, x86@kernel.org, dave.hansen@linux.intel.com, peterz@infradead.org, kernel-team@meta.com, bp@alien8.de, Yu-cheng Yu , Rik van Riel Subject: [RFC v5 3/8] x86/mm: Introduce X86_FEATURE_RAR Date: Fri, 21 Nov 2025 13:54:24 -0500 Message-ID: <20251121185530.21876-4-riel@surriel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251121185530.21876-1-riel@surriel.com> References: <20251121185530.21876-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yu-cheng Yu Introduce X86_FEATURE_RAR and enumeration of the feature. [riel: moved initialization to intel.c and disabling to Kconfig.cpufeatures] Signed-off-by: Yu-cheng Yu Signed-off-by: Rik van Riel --- arch/x86/Kconfig.cpufeatures | 4 ++++ arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/intel.c | 9 +++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures index 733d5aff2456..6389f0a617c8 100644 --- a/arch/x86/Kconfig.cpufeatures +++ b/arch/x86/Kconfig.cpufeatures @@ -199,3 +199,7 @@ config X86_DISABLED_FEATURE_SEV_SNP config X86_DISABLED_FEATURE_INVLPGB def_bool y depends on !BROADCAST_TLB_FLUSH + +config X86_DISABLED_FEATURE_RAR + def_bool y + depends on !BROADCAST_TLB_FLUSH diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b6472e252491..5cb57a820198 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -76,7 +76,7 @@ #define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */ #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitectur= e */ #define X86_FEATURE_ZEN6 ( 3*32+ 6) /* CPU based on Zen6 microarchitectur= e */ -/* Free ( 3*32+ 7) */ +#define X86_FEATURE_RAR ( 3*32+ 7) /* Intel Remote Action Request */ #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at= a constant rate */ #define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */ #define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 98ae4c37c93e..b53bf3452d6a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -719,6 +719,15 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) cpuid_leaf_0x2(®s); for_each_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); + + if (cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) { + u64 msr; + + rdmsrl(MSR_IA32_CORE_CAPS, msr); + + if (msr & MSR_IA32_CORE_CAPS_RAR) + setup_force_cpu_cap(X86_FEATURE_RAR); + } } =20 static const struct cpu_dev intel_cpu_dev =3D { --=20 2.51.1