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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:47 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 03/15] dt-bindings: pinctrl: rzg2l-poeg: Document renesas,poeg-config property Date: Fri, 21 Nov 2025 16:08:10 +0000 Message-ID: <20251121160842.371922-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document renesas,poeg-config optional property. The output pins of the general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). The HW supports following ways to disable the output pins. 1) Pin output disable by input level detection of the GTETRG{A..D} pins 2) Output disable request from the GPT 3) Pin output disable by user control Acked-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Biju Das --- v7->v8: * Add ack from Rob and Linus Walleij. v7: * New patch --- .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.y= aml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml index ab2d456c93e4..ae027a490206 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -57,6 +57,21 @@ properties: <2> : POEG group C <3> : POEG group D =20 + renesas,poeg-config: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4, 6, 8, 10, 12, 14, 16 ] + description: | + POEG Configuration. Valid values are: + <1> : User control + <2> : GPT both output high + <4> : GPT both output low + <6> : GPT both output high + GPT both output low + <8> : GPT dead time error + <10> : GPT both output high + GPT dead time error + <12> : GPT both output low + GPT dead time error + <14> : GPT both output {high, low} + GPT dead time error + <16> : External pin control + required: - compatible - reg @@ -83,4 +98,5 @@ examples: resets =3D <&cpg R9A07G044_POEG_D_RST>; renesas,poeg-id =3D <3>; renesas,gpt =3D <&gpt>; + renesas,poeg-config =3D <1>; }; --=20 2.43.0