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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:45 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 01/15] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Date: Fri, 21 Nov 2025 16:08:08 +0000 Message-ID: <20251121160842.371922-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G2L GPT IP supports output pin disable function by dead time error and detecting short-circuits between output pins. Add documentation for the optional property renesas,poegs to link a pair of GPT IOs with POEG. Reviewed-by: Rob Herring Signed-off-by: Biju Das --- V24 from [1] -> v8: * No change [1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.rene= sas.com/ --- .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b= /Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml index 13b807765a30..98bcde755fb9 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -245,6 +245,28 @@ properties: resets: maxItems: 1 =20 + renesas,poegs: + minItems: 1 + maxItems: 8 + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to POEG instance that serves the output dis= able + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] + description: | + An index identifying pair of GPT channels. + <0> : GPT channels 0 and 1 + <1> : GPT channels 2 and 3 + <2> : GPT channels 4 and 5 + <3> : GPT channels 6 and 7 + <4> : GPT channels 8 and 9 + <5> : GPT channels 10 and 11 + <6> : GPT channels 12 and 13 + <7> : GPT channels 14 and 15 + description: + A list of phandle and channel index pair tuples to the POEGs that ha= ndle the + output disable for the GPT channels. + required: - compatible - reg @@ -375,4 +397,5 @@ examples: power-domains =3D <&cpg>; resets =3D <&cpg R9A07G044_GPT_RST_C>; #pwm-cells =3D <3>; + renesas,poegs =3D <&poeggd 4>; }; --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4836A31158A for ; Fri, 21 Nov 2025 16:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763741331; cv=none; b=t0EAf77ujO5H1wrFWVyQhM38M8ig9WubG+gHWbl6FrbfOyViKxsiPPaumrsgPGLIbQQwdfvtpdrqV0monYP8DFsaRtrvHpJySum4KhKHeCYQdfKHbmg8V/a7gUvA+TBM2wPrd/AiNDq1KIzwuZ0VOM3oFDBe6nex9dlIl5fcTd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763741331; c=relaxed/simple; bh=UceBvl9mvJOOEGtnw5s3Ldt6TQ9x8yChblPWkYoFcFI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:46 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 02/15] pwm: rzg2l-gpt: Add support for gpt linking with poeg Date: Fri, 21 Nov 2025 16:08:09 +0000 Message-ID: <20251121160842.371922-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The General PWM Timer (GPT) is capable of detecting "dead time error and short-circuits between output pins" and send Output disable request to poeg(Port Output Enable for GPT). Add support for linking poeg group with gpt, so that gpt can control the output disable function. Signed-off-by: Biju Das --- V24 from [1] -> v8: * Replaced return type of rzg2l_gpt_poeg_init() from void->int and probe() checks this return value. * Added more error checks in rzg2l_gpt_poeg_init()=20 [1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.rene= sas.com/ --- drivers/pwm/pwm-rzg2l-gpt.c | 95 +++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 38ad03ded9ce..aabd2d576231 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -39,6 +39,7 @@ #define RZG2L_GTCR(ch) (0x2c + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch)) +#define RZG2L_GTINTAD(ch) (0x38 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_c= h)) @@ -55,12 +56,21 @@ #define RZG2L_GTUDDTYC_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF) =20 #define RZG2L_GTIOR_GTIOA GENMASK(4, 0) +#define RZG2L_GTIOR_OADF GENMASK(10, 9) #define RZG2L_GTIOR_GTIOB GENMASK(20, 16) +#define RZG2L_GTIOR_OBDF GENMASK(26, 25) + #define RZG2L_GTIOR_GTIOx(sub_ch) ((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GT= IOR_GTIOA) + #define RZG2L_GTIOR_OAE BIT(8) #define RZG2L_GTIOR_OBE BIT(24) #define RZG2L_GTIOR_OxE(sub_ch) ((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR= _OAE) =20 +#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9) +#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25) +#define RZG2L_GTIOR_PIN_DISABLE_SETTING \ + (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_= OUT_DISABLE) + #define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b #define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \ (RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE) @@ -71,12 +81,17 @@ ((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \ RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH) =20 +#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) + #define RZG2L_MAX_HW_CHANNELS 8 #define RZG2L_CHANNELS_PER_IO 2 #define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER= _IO) #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +#define RZG2L_MAX_POEG_GROUPS 4 +#define RZG2L_LAST_POEG_GROUP 3 + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ @@ -84,6 +99,7 @@ struct rzg2l_gpt_chip { u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNE= LS); }; =20 static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *ch= ip) @@ -379,6 +395,81 @@ static const struct pwm_ops rzg2l_gpt_ops =3D { .apply =3D rzg2l_gpt_apply, }; =20 +/* + * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and + * configure the pin for output disable. + */ +static int rzg2l_gpt_poeg_init(struct platform_device *pdev, + struct rzg2l_gpt_chip *rzg2l_gpt) +{ + const char *poeg_name =3D "renesas,poegs"; + struct of_phandle_args of_args; + struct property *poegs; + unsigned int i; + u32 poeg_grp; + u32 bitpos; + int cells; + int ret; + + poegs =3D of_find_property(pdev->dev.of_node, poeg_name, NULL); + if (!poegs) + return 0; + + cells =3D of_property_count_u32_elems(pdev->dev.of_node, poeg_name); + if (cells < 0) + return cells; + + if (cells & 1) + return -EINVAL; + + cells >>=3D 1; + for (i =3D 0; i < cells; i++) { + ret =3D of_parse_phandle_with_fixed_args(pdev->dev.of_node, + poeg_name, 1, i, + &of_args); + if (ret) + return ret; + + if (of_args.args[0] >=3D RZG2L_MAX_HW_CHANNELS) { + dev_err(&pdev->dev, "Invalid channel %d >=3D %d\n", + of_args.args[0], RZG2L_MAX_HW_CHANNELS); + goto err_of_node; + } + + if (!of_device_is_available(of_args.np)) { + /* It's fine to have a phandle to a non-enabled poeg. */ + of_node_put(of_args.np); + continue; + } + + if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) { + if (poeg_grp > RZG2L_LAST_POEG_GROUP) { + dev_err(&pdev->dev, "Invalid poeg group %d > %d\n", + poeg_grp, RZG2L_LAST_POEG_GROUP); + goto err_of_node; + } + + bitpos =3D of_args.args[0] + poeg_grp * RZG2L_MAX_HW_CHANNELS; + set_bit(bitpos, rzg2l_gpt->poeg_gpt_link); + + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(of_args.args[0]), + RZG2L_GTINTAD_GRP_MASK, poeg_grp << 24); + + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(of_args.args[0]), + RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF, + RZG2L_GTIOR_PIN_DISABLE_SETTING); + } + + of_node_put(of_args.np); + } + + return 0; + +err_of_node: + of_node_put(of_args.np); + return -EINVAL; +} + static int rzg2l_gpt_probe(struct platform_device *pdev) { struct rzg2l_gpt_chip *rzg2l_gpt; @@ -430,6 +521,10 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (rzg2l_gpt->rate_khz * KILO !=3D rate) return dev_err_probe(dev, -EINVAL, "Rate is not multiple of 1000"); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:47 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 03/15] dt-bindings: pinctrl: rzg2l-poeg: Document renesas,poeg-config property Date: Fri, 21 Nov 2025 16:08:10 +0000 Message-ID: <20251121160842.371922-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document renesas,poeg-config optional property. The output pins of the general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). The HW supports following ways to disable the output pins. 1) Pin output disable by input level detection of the GTETRG{A..D} pins 2) Output disable request from the GPT 3) Pin output disable by user control Acked-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Biju Das --- v7->v8: * Add ack from Rob and Linus Walleij. v7: * New patch --- .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.y= aml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml index ab2d456c93e4..ae027a490206 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -57,6 +57,21 @@ properties: <2> : POEG group C <3> : POEG group D =20 + renesas,poeg-config: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4, 6, 8, 10, 12, 14, 16 ] + description: | + POEG Configuration. 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:47 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Philipp Zabel , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 04/15] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support Date: Fri, 21 Nov 2025 16:08:11 +0000 Message-ID: <20251121160842.371922-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The output pins of the RZ/G2L general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). Add basic support for user control and output-disable requests from the GTETRGn pins by using poeg char device. Signed-off-by: Biju Das --- v7->v8: * Replaced config name from POEG_RZG2L->RENESAS_RZG2L_POEG. * Updated POEG Kconfig dependency with PWM * Dropped static variable minor_n and instead using the value of "renesas,poeg-id". * Replaced devm_reset_*_exclusive()->devm_reset_*_exclusive_deasserted() * Replaced pm_runtime_enable() with devm variant. * Added support for handling output-disable requests from the GTETRGn pins. * Replaced the macros RZG2L_POEG_USR_CTRL_{EN,DiS}ABLE_CMD to=20 RZG2L_POEG_OUTPUT_DISABLE_USR_{EN,DIS}ABLE_CMD. * Replaced '&pdev->dev' by 'dev' in probe(). v6->v7: * Used DT to handle the system configuration * Added poeg char device for user control support to enable/disable output from GPT * Replaced iowrite32/ioread32-> writel/readl * Dropped of_match_ptr from .of_match_table v5->v6: * Dropped sysfs and is handled in generic driver. v4->v5: * Updated kernel version in sysfs doc. v3->v4: * Updated commit description. v2->v3: * Added sysfs documentation for output_disable * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency * Used dev_get_drvdata to get device data * Replaced sprintf->sysfs_emit in show(). v1->v2: * Renamed the file poeg-rzg2l->rzg2l-poeg * Removed the macro POEGG as there is only single register and updated rzg2l_poeg_write() and rzg2l_poeg_read() * Updated error handling in probe() Ref->v1: * Moved driver files from soc to pincontrol directory * Updated KConfig --- drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/poeg/Kconfig | 11 + drivers/pinctrl/renesas/poeg/Makefile | 2 + drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 368 ++++++++++++++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 15 + 6 files changed, 400 insertions(+) create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig create mode 100644 drivers/pinctrl/renesas/poeg/Makefile create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c create mode 100644 include/linux/pinctrl/rzg2l-poeg.h diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kcon= fig index 8cbd79a13414..dc95b7020d30 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -326,4 +326,6 @@ config PINCTRL_RZV2M This selects GPIO and pinctrl driver for Renesas RZ/V2M platforms. =20 +source "drivers/pinctrl/renesas/poeg/Kconfig" + endmenu diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Mak= efile index 1c5144a1c4b8..8dc5da978a45 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -53,6 +53,8 @@ obj-$(CONFIG_PINCTRL_RZN1) +=3D pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_RZT2H) +=3D pinctrl-rzt2h.o obj-$(CONFIG_PINCTRL_RZV2M) +=3D pinctrl-rzv2m.o =20 +obj-$(CONFIG_RENESAS_RZG2L_POEG) +=3D poeg/ + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o +=3D -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o +=3D -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas= /poeg/Kconfig new file mode 100644 index 000000000000..621a4ce72c72 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +config RENESAS_RZG2L_POEG + tristate "Renesas RZ/G2L poeg support" + depends on PWM_RENESAS_RZG2L_GPT || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the Port Output Enable for GPT(POEG) found + in Renesas RZ/G2L alike SoCs. + + To compile this driver as a module, choose M here: the module + will be called rzg2l-poeg. diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesa= s/poeg/Makefile new file mode 100644 index 000000000000..b0ed1e9a467a --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RENESAS_RZG2L_POEG) +=3D rzg2l-poeg.o diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/re= nesas/poeg/rzg2l-poeg.c new file mode 100644 index 000000000000..2a09888407d0 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver + * + * Copyright (C) 2023 Renesas Electronics Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define POEGG_IOCE BIT(5) +#define POEGG_PIDE BIT(4) +#define POEGG_SSF BIT(3) +#define POEGG_IOCF BIT(1) +#define POEGG_PIDF BIT(0) + +#define RZG2L_POEG_MAX_INDEX 3 + +#define RZG2L_GPT_MAX_HW_CHANNELS 8 +#define RZG2L_GPT_INVALID_CHANNEL 0xff + +enum poeg_conf { + POEG_USER_CTRL =3D BIT(0), + POEG_GPT_BOTH_HIGH =3D BIT(1), + POEG_GPT_BOTH_LOW =3D BIT(2), + POEG_GPT_DEAD_TIME =3D BIT(3), + POEG_EXT_PIN_CTRL =3D BIT(4), + POEG_GPT_BOTH_HIGH_LOW =3D BIT(1) | BIT(2), + POEG_GPT_BOTH_HIGH_DEAD_TIME =3D BIT(1) | BIT(3), + POEG_GPT_BOTH_LOW_DEAD_TIME =3D BIT(2) | BIT(3), + POEG_GPT_ALL =3D BIT(1) | BIT(2) | BIT(3) +}; + +static struct class *poeg_class; +static dev_t g_poeg_dev; + +struct rzg2l_poeg_chip { + struct device *gpt_dev; + struct reset_control *rstc; + void __iomem *mmio; + struct cdev poeg_cdev; + u32 cfg; + int minor_n; + u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; + u8 index; +}; + +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) +{ + writel(data, chip->mmio); +} + +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) +{ + return readl(chip->mmio); +} + +static int rzg2l_poeg_output_disable_user(struct rzg2l_poeg_chip *chip, bo= ol enable) +{ + u32 reg_val; + + reg_val =3D rzg2l_poeg_read(chip); + if (enable) + reg_val |=3D POEGG_SSF; + else + reg_val &=3D ~POEGG_SSF; + + rzg2l_poeg_write(chip, reg_val); + + return 0; +} + +static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) +{ + struct rzg2l_poeg_chip *chip =3D ptr; + u32 val; + + val =3D rzg2l_poeg_read(chip); + if (val & POEGG_PIDF) + val &=3D ~POEGG_PIDF; + + rzg2l_poeg_write(chip, val); + + return IRQ_HANDLED; +} + +static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, const char __use= r *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip =3D filp->private_data; + struct poeg_cmd cmd; + + if (copy_from_user(&cmd, buf, sizeof(cmd))) + return -EFAULT; + + switch (cmd.val) { + case RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD: + rzg2l_poeg_output_disable_user(chip, true); + break; + case RZG2L_POEG_OUTPUT_DISABLE_USR_DISABLE_CMD: + rzg2l_poeg_output_disable_user(chip, false); + break; + default: + return -EINVAL; + } + + return len; +} + +static int rzg2l_poeg_chrdev_open(struct inode *inode, struct file *filp) +{ + struct rzg2l_poeg_chip *const chip =3D container_of(inode->i_cdev, typeof= (*chip), + poeg_cdev); + + filp->private_data =3D chip; + + return nonseekable_open(inode, filp); +} + +static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *fil= p) +{ + filp->private_data =3D NULL; + + return 0; +} + +static const struct file_operations poeg_fops =3D { + .owner =3D THIS_MODULE, + .write =3D rzg2l_poeg_chrdev_write, + .open =3D rzg2l_poeg_chrdev_open, + .release =3D rzg2l_poeg_chrdev_release, +}; + +static bool rzg2l_poeg_get_linked_gpt_channels(struct platform_device *pde= v, + struct rzg2l_poeg_chip *chip, + struct device_node *gpt_np, + u8 poeg_id) +{ + struct of_phandle_args of_args; + bool ret =3D false; + unsigned int i; + u32 poeg_grp; + int cells; + int err; + + cells =3D of_property_count_u32_elems(gpt_np, "renesas,poegs"); + if (cells =3D=3D -EINVAL) + return ret; + + for (i =3D 0 ; i < RZG2L_GPT_MAX_HW_CHANNELS; i++) + chip->gpt_channels[i] =3D RZG2L_GPT_INVALID_CHANNEL; + + cells >>=3D 1; + for (i =3D 0; i < cells; i++) { + err =3D of_parse_phandle_with_fixed_args(gpt_np, "renesas,poegs", + 1, i, &of_args); + if (err) { + dev_err_probe(&pdev->dev, err, + "Failed to parse 'renesas,poegs' property\n"); + break; + } + + if (of_args.args[0] >=3D RZG2L_GPT_MAX_HW_CHANNELS) { + dev_err(&pdev->dev, "Invalid channel %d >=3D %d\n", + of_args.args[0], RZG2L_GPT_MAX_HW_CHANNELS); + of_node_put(of_args.np); + break; + } + + if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) { + if (poeg_grp =3D=3D poeg_id) { + chip->gpt_channels[of_args.args[0]] =3D poeg_id; + ret =3D true; + } + } + + of_node_put(of_args.np); + } + + return ret; +} + +static const struct of_device_id rzg2l_poeg_of_table[] =3D { + { .compatible =3D "renesas,rzg2l-poeg", }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table); + +static void rzg2l_poeg_cleanup(void *data) +{ + struct rzg2l_poeg_chip *chip =3D data; + + put_device(chip->gpt_dev); +} + +static int rzg2l_poeg_probe(struct platform_device *pdev) +{ + struct platform_device *gpt_pdev =3D NULL; + struct device *dev =3D &pdev->dev; + struct rzg2l_poeg_chip *chip; + bool gpt_linked =3D false; + struct device_node *np; + struct device *cdev; + u32 cfg, val; + int ret, irq; + + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + if (!of_property_read_u32(dev->of_node, "renesas,poeg-id", &val)) + chip->index =3D val; + + if (chip->index > RZG2L_POEG_MAX_INDEX) + return -EINVAL; + + np =3D of_parse_phandle(dev->of_node, "renesas,gpt", 0); + if (np) + gpt_pdev =3D of_find_device_by_node(np); + + gpt_linked =3D rzg2l_poeg_get_linked_gpt_channels(pdev, chip, np, chip->i= ndex); + of_node_put(np); + if (!gpt_pdev || !gpt_linked) + return -ENODEV; + + chip->gpt_dev =3D &gpt_pdev->dev; + ret =3D devm_add_action_or_reset(dev, rzg2l_poeg_cleanup, chip); + if (ret < 0) + return ret; + + chip->mmio =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->mmio)) + return PTR_ERR(chip->mmio); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, rzg2l_poeg_irq, 0, dev_name(dev), chip= ); + if (ret < 0) + return dev_err_probe(dev, ret, "cannot get irq\n"); + + chip->rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(chip->rstc)) + return dev_err_probe(dev, PTR_ERR(chip->rstc), "get deasserted reset fai= led\n"); + + platform_set_drvdata(pdev, chip); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "pm_runtime_resume_get failed\n"); + + ret =3D of_property_read_u32(dev->of_node, "renesas,poeg-config", &cfg); + if (ret) + goto err_pm; + + switch (cfg) { + case POEG_USER_CTRL: + rzg2l_poeg_write(chip, 0); + break; + case POEG_EXT_PIN_CTRL: + rzg2l_poeg_write(chip, POEGG_PIDE); + break; + default: + ret =3D -EINVAL; + goto err_pm; + } + + chip->cfg =3D cfg; + + cdev_init(&chip->poeg_cdev, &poeg_fops); + chip->poeg_cdev.owner =3D THIS_MODULE; + ret =3D cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), chip->index),= 1); + if (ret) + goto err_pm; + + cdev =3D device_create(poeg_class, NULL, MKDEV(MAJOR(g_poeg_dev), chip->i= ndex), + NULL, "poeg%d", chip->index); + if (IS_ERR(cdev)) { + ret =3D PTR_ERR(cdev); + dev_err_probe(dev, ret, "Error %d creating device for port\n", chip->ind= ex); + goto free_cdev; + } + + chip->minor_n =3D chip->index; + + return ret; + +free_cdev: + cdev_del(&chip->poeg_cdev); +err_pm: + pm_runtime_put(&pdev->dev); + return ret; +} + +static void rzg2l_poeg_remove(struct platform_device *pdev) +{ + struct rzg2l_poeg_chip *chip =3D platform_get_drvdata(pdev); + + device_destroy(poeg_class, MKDEV(MAJOR(g_poeg_dev), chip->minor_n)); + cdev_del(&chip->poeg_cdev); + pm_runtime_put(&pdev->dev); +} + +static struct platform_driver rzg2l_poeg_driver =3D { + .driver =3D { + .name =3D "rzg2l-poeg", + .of_match_table =3D rzg2l_poeg_of_table + }, + .probe =3D rzg2l_poeg_probe, + .remove =3D rzg2l_poeg_remove +}; + +static int rzg2l_poeg_device_init(void) +{ + int err; + + err =3D alloc_chrdev_region(&g_poeg_dev, 0, 1, "poeg"); + if (err) + goto out; + + poeg_class =3D class_create("poeg"); + if (IS_ERR(poeg_class)) { + err =3D PTR_ERR(poeg_class); + goto err_free_chrdev; + } + + err =3D platform_driver_register(&rzg2l_poeg_driver); + if (err) + goto err_class_destroy; + + return 0; + +err_class_destroy: + class_destroy(poeg_class); +err_free_chrdev: + unregister_chrdev_region(g_poeg_dev, 1); +out: + return err; +} + +static void rzg2l_poeg_device_exit(void) +{ + platform_driver_unregister(&rzg2l_poeg_driver); + class_destroy(poeg_class); + unregister_chrdev_region(g_poeg_dev, 1); +} + +module_init(rzg2l_poeg_device_init); +module_exit(rzg2l_poeg_device_exit); + +MODULE_AUTHOR("Biju Das "); +MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg= 2l-poeg.h new file mode 100644 index 000000000000..a5392f956700 --- /dev/null +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_RENESAS_RZG2L_POEG_H__ +#define __LINUX_RENESAS_RZG2L_POEG_H__ + +#include + +#define RZG2L_POEG_OUTPUT_DISABLE_USR_DISABLE_CMD 0 +#define RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD 1 + +struct poeg_cmd { + __u32 val; + __u8 channel; +}; + +#endif /* __LINUX_RENESAS_RZG2L_POEG_H__ */ --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D143A34A77E for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:48 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 05/15] arm64: dts: renesas: r9a07g0{4,5}4: Add POEG nodes Date: Fri, 21 Nov 2025 16:08:12 +0000 Message-ID: <20251121160842.371922-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add POEGG{A,B,C,D} nodes to RZ/{G2L,V2L} SoC DTSI. Signed-off-by: Biju Das --- v8: * New patch --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 52 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 52 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g044.dtsi index bd52d60bafb9..28ef5ac98712 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -359,6 +359,58 @@ gpt: pwm@10048000 { status =3D "disabled"; }; =20 + poegga: poeg@10048800 { + compatible =3D "renesas,r9a07g044-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10048800 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G044_POEG_A_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_POEG_A_RST>; + renesas,poeg-id =3D <0>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggb: poeg@10048c00 { + compatible =3D "renesas,r9a07g044-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10048c00 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G044_POEG_B_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_POEG_B_RST>; + renesas,poeg-id =3D <1>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggc: poeg@10049000 { + compatible =3D "renesas,r9a07g044-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10049000 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G044_POEG_C_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_POEG_C_RST>; + renesas,poeg-id =3D <2>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggd: poeg@10049400 { + compatible =3D "renesas,r9a07g044-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10049400 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_POEG_D_RST>; + renesas,poeg-id =3D <3>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + ssi0: ssi@10049c00 { compatible =3D "renesas,r9a07g044-ssi", "renesas,rz-ssi"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g054.dtsi index 4e0256d3201d..14ea99d2cfd0 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -359,6 +359,58 @@ gpt: pwm@10048000 { status =3D "disabled"; }; =20 + poegga: poeg@10048800 { + compatible =3D "renesas,r9a07g054-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10048800 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G054_POEG_A_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G054_POEG_A_RST>; + renesas,poeg-id =3D <0>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggb: poeg@10048c00 { + compatible =3D "renesas,r9a07g054-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10048c00 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G054_POEG_B_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G054_POEG_B_RST>; + renesas,poeg-id =3D <1>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggc: poeg@10049000 { + compatible =3D "renesas,r9a07g054-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10049000 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G054_POEG_C_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G054_POEG_C_RST>; + renesas,poeg-id =3D <2>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + + poeggd: poeg@10049400 { + compatible =3D "renesas,r9a07g054-poeg", + "renesas,rzg2l-poeg"; + reg =3D <0 0x10049400 0 0x400>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A07G054_POEG_D_CLKP>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G054_POEG_D_RST>; + renesas,poeg-id =3D <3>; + renesas,gpt =3D <&gpt>; + status =3D "disabled"; + }; + ssi0: ssi@10049c00 { compatible =3D "renesas,r9a07g054-ssi", "renesas,rz-ssi"; --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE6D334C81D for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:49 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 06/15] arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier board Date: Fri, 21 Nov 2025 16:08:13 +0000 Message-ID: <20251121160842.371922-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable POEGG{A,B,C,D} on RZ/{G2,V2}L SMARC EVK. Signed-off-by: Biju Das --- v8: * New patch. --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg2l-smarc.dtsi index b76b55e7f09d..7648f0e96668 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -109,6 +109,7 @@ &gpt { pinctrl-0 =3D <&gpt_pins>; pinctrl-names =3D "default"; status =3D "okay"; + renesas,poegs =3D <&poeggd 4>; }; #endif /* PMOD0_GPT */ =20 @@ -166,6 +167,11 @@ &spi1 { }; #endif /* PMOD_MTU3 */ =20 +&poeggd { + status =3D "okay"; + renesas,poeg-config =3D <1>; +}; + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C92EB34D4D5 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:50 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven Cc: Biju Das , Krzysztof Kozlowski , Bjorn Andersson , Arnd Bergmann , Dmitry Baryshkov , Eric Biggers , Michal Simek , Luca Weiss , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Lad Prabhakar , Kuninori Morimoto , linux-kernel@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v8 07/15] arm64: defconfig: Enable Renesas RZ/G2L POEG interface Date: Fri, 21 Nov 2025 16:08:14 +0000 Message-ID: <20251121160842.371922-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The Renesas RZ/G2L POEG interface is used in SMARC RZ/G2L EVK. Enable the driver for it in the default configuration. Signed-off-by: Biju Das --- v8: * New patch. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dcdd4fcdc2a7..f2c28deb2283 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -688,6 +688,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=3Dm CONFIG_PINCTRL_SC8280XP_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8550_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8650_LPASS_LPI=3Dm +CONFIG_RENESAS_RZG2L_POEG=3Dm CONFIG_PINCTRL_SOPHGO_SG2000=3Dy CONFIG_GPIO_ALTERA=3Dm CONFIG_GPIO_DAVINCI=3Dy --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7D3C34D906 for ; Fri, 21 Nov 2025 16:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763741335; cv=none; b=rurzraRxq3vsETdb7/7CmQESLWEY5IKv8sqt0GV472MHfzi9w1UnDKJklIy2L+ztgkkeYt30EEdnb6nds4zJLNO5vr+dK7iqCRcbtGj1JqJrX127n6UWJw7mC1rhtF0JA8D55Kj6rPZ2xvCdu1dpTFgyC6wtXVCdA6zzA7OGurc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763741335; c=relaxed/simple; bh=+t6QRXttRpX5nce6uZuXOYAkO7xTEcrDg1qTPVsuBuk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TAVnf6es8eleVidBnYJ4lDwTG1pqotVDAqG4vU/8oU2nDvHO5+bBnuXRtgqwhfjhXeY9ZrCP8+m7+gGMFcZeRqKMrZRrhsXsX3SVFI7m0vtff1pj17SnDfM3pthpi2RYo9zVzEMJuMd3OMueHCOut7mbAQpnlO9d9jXyDS4Okjw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IJp0x6Oc; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IJp0x6Oc" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4779cc419b2so23647215e9.3 for ; Fri, 21 Nov 2025 08:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763741331; x=1764346131; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8o2eYAk4+T2MvJcophYUy9RZhVssXZ1GeiS/j2h3xk8=; b=IJp0x6Oc2nW+PGonCRDevst2Z7j9C/SyOawKu2FLVDmPzGB7Etga9VuaUHR/haegKf xk/6KPNA9aWEknSLoOPxgMiP6eYrV2FBjBfJ2baJYG0kC9sGmw289C9k24N1roL+t2kQ d/aKB3yoEo86TKptUUoWzCSv1z8t5hnu8cZWXd0mln+F/9GtDxd0ciIECxJuOgtIch2S KG+1LYIJneal4YxKikQJ7jiD7PHIl9bkrBEyUsZ0Yos+YuRYf1WBmfCji+FAH+sn8bC2 g4k1rrH5DEBTT1TQ/pfznyigL5NqOR6qM3mF4cHB+puGggqoQC+hvCYIC+H4KFMkKvgQ 3a8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763741331; x=1764346131; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8o2eYAk4+T2MvJcophYUy9RZhVssXZ1GeiS/j2h3xk8=; b=f6D0rSjoMM1g42kBeFCweSWNxKRrTQzc58SH8Iu7u2ZjrqIYj5XagY6MGmRtyBIEZ8 15Tr2bgWaA3E/48svclVnpeq/07NEmRbqXFfoxCLBauOsIwXAZhKsTLAZPzthuzK4Aqy Uyl/wYPFN9jtt45M6Sg/6VY87L8BRiK3He90Tt24v8YD67i6OnV7no2Gsd7fmLmw4YCd kQWoG9DcKvZhMePAfFtgo5Xbl6+248SpnxlGaGHqw/XGIJUK4L2OB2XUIMO/Nhf8bVDU xjaj4ba1nqteKlKWG96KsrDvBU2Ai51+iosujhcZNuvabQJ24sPk2EVqnAF1W5KEGl95 ez8A== X-Forwarded-Encrypted: i=1; AJvYcCVcUu42Plw9Oub+euezepARiXOAWc+s3pE6ySDXO1mvqAaYuu58i6wdXHm4YdqLQOXoGRg2RlY83Rvvi3E=@vger.kernel.org X-Gm-Message-State: AOJu0YzTFqJy26Vq4HFht0CoRIlRiopDm8vUVYJer7jAiIHPI+YM3SPu yUUnvZAUar62hFqzO6Z+o6yxkxJVVhDhclCpvpBdxrrzI9Ei18MdSyhl X-Gm-Gg: ASbGncs4SvvO1wQtldXSKPxjUtZ1O2vtKE+V48oeNOW7TD3Wq1p+jLfF56KMdwLbOA7 g8+G6rNXSbnRy7rOm4TpGYITlZZy9Y1kHqCy0qo7rWcqstSA5ibtqmxYv0IPk9o8v8B0YgHHnhv CjxSoY6FLjQORSOCkJoBUeYqpYM4HQLXDF2VQAMg/9pNSz7ajNi1RlaNisTo4OugIiOkGO+MGo8 rEki0LWhH927m+EeVP0NWs6ox1TECfBh7FQVt/fUTIipvNMsSMHNFIpgMnw5wNmlOs8u/hGYfSr Xhs2I2BDS7IleLu2SXA858nkFomryt/2ARpAn3jZsqwCQC4639uo7AKvymQSSrdu0ivfPY17aRQ Lhlq5UMCPr+mYxBgGZccyZVZMzcHXXCoWc87dCbC5ISIGfe/tjBwAGwkDX/N/g7PiraX68UKuRa pT2R6TLU5Ro8DtEkMR9cIhspxkj08topkeBHbT0Vpka+5YSvZzy81h4ZTl7VoweJj3SpejPYEPL BosucH6ww== X-Google-Smtp-Source: AGHT+IEJXgXSUSmmo2SsXVmfT6DnwKWByn13rXM7axdiuHfSioFwEpENFf28kMwD6HAfy6nncBRDDA== X-Received: by 2002:a05:600c:3b01:b0:477:54cd:200a with SMTP id 5b1f17b1804b1-477c110325dmr23471945e9.6.1763741330953; Fri, 21 Nov 2025 08:08:50 -0800 (PST) Received: from biju.lan (host86-162-200-138.range86-162.btcentralplus.com. [86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:50 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 08/15] tools/poeg: Add test app for poeg Date: Fri, 21 Nov 2025 16:08:15 +0000 Message-ID: <20251121160842.371922-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add test app for poeg for controlling output disable through user space. Signed-off-by: Biju Das --- tools/poeg/Build | 1 + tools/poeg/Makefile | 53 +++++++++++++++++++++++++++++++++++++++ tools/poeg/poeg_app.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 tools/poeg/Build create mode 100644 tools/poeg/Makefile create mode 100644 tools/poeg/poeg_app.c diff --git a/tools/poeg/Build b/tools/poeg/Build new file mode 100644 index 000000000000..f960920a4afb --- /dev/null +++ b/tools/poeg/Build @@ -0,0 +1 @@ +poeg_app-y +=3D poeg_app.o diff --git a/tools/poeg/Makefile b/tools/poeg/Makefile new file mode 100644 index 000000000000..669c914d9c98 --- /dev/null +++ b/tools/poeg/Makefile @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +include ../scripts/Makefile.include + +bindir ?=3D /usr/bin + +ifeq ($(srctree),) +srctree :=3D $(patsubst %/,%,$(dir $(CURDIR))) +srctree :=3D $(patsubst %/,%,$(dir $(srctree))) +endif + +# Do not use make's built-in rules +# (this improves performance and avoids hard-to-debug behaviour); +MAKEFLAGS +=3D -r + +override CFLAGS +=3D -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include + +ALL_TARGETS :=3D poeg_app +ALL_PROGRAMS :=3D $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS)) + +all: $(ALL_PROGRAMS) + +export srctree OUTPUT CC LD CFLAGS +include $(srctree)/tools/build/Makefile.include + +# +# We need the following to be outside of kernel tree +# +$(OUTPUT)include/linux/poeg.h: ../../include/linux/pinctrl/rzg2l-poeg.h + mkdir -p $(OUTPUT)include/linux 2>&1 || true + ln -sf $(CURDIR)/../../include/linux/pinctrl/rzg2l-poeg.h $@ + +prepare: $(OUTPUT)include/linux/poeg.h + +POEG_EXAMPLE :=3D $(OUTPUT)poeg_app.o +$(POEG_EXAMPLE): prepare FORCE + $(Q)$(MAKE) $(build)=3Dpoeg_app +$(OUTPUT)poeg_app: $(POEG_EXAMPLE) + $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ + +clean: + rm -f $(ALL_PROGRAMS) + rm -rf $(OUTPUT)include/linux/poeg.h + find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete + +install: $(ALL_PROGRAMS) + install -d -m 755 $(DESTDIR)$(bindir); \ + for program in $(ALL_PROGRAMS); do \ + install $$program $(DESTDIR)$(bindir); \ + done + +FORCE: + +.PHONY: all install clean FORCE prepare diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c new file mode 100644 index 000000000000..4ff8e5c007dc --- /dev/null +++ b/tools/poeg/poeg_app.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * POEG - example userspace application + * Copyright (C) 2023 Biju Das + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int main(int argc, char *argv[]) +{ + struct poeg_cmd cmd; + unsigned int val; + long cmd_val; + char *p; + int i; + + cmd_val =3D strtol(argv[1], &p, 10); + if (*p !=3D '\0' || errno !=3D 0) + return 1; // In main(), returning non-zero means failure + + fd =3D open("/dev/poeg3", O_RDWR); + if (fd < 0) + perror("open"); + else + printf("[POEG]open\n"); + + cmd.val =3D cmd_val; + cmd.channel =3D 4; + if (cmd.val =3D=3D RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD) + printf("[POEG] user control pin output disable enabled\n"); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:51 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY v8 09/15] pwm: rzg2l-gpt: Add support for output disable request from gpt Date: Fri, 21 Nov 2025 16:08:16 +0000 Message-ID: <20251121160842.371922-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das When dead time error occurs or the GTIOCA pin output value is the same as the GTIOCB pin output value, output protection is required. GPT detects this condition and generates output disable requests to POEG based on the settings in the output disable request permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH, GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and calculates external input using an OR operation, the POEG generates output disable requests to GPT. Add support for output disable request from gpt, when output level is high for both IOs at the same time. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 99 +++++++++++++++++++++++++++++++++++ include/linux/pwm/rzg2l-gpt.h | 33 ++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 include/linux/pwm/rzg2l-gpt.h diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index aabd2d576231..8006c62068b6 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ #define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTINTAD(ch) (0x38 + RZG2L_GET_CH_OFFS(ch)) +#define RZG2L_GTST(ch) (0x3c + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_c= h)) @@ -82,6 +84,12 @@ RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH) =20 #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) + +#define RZG2L_GTST_OABHF BIT(29) +#define RZG2L_GTST_OABLF BIT(30) + +#define RZG2L_GTST_POEG_IRQ_MASK GENMASK(30, 28) =20 #define RZG2L_MAX_HW_CHANNELS 8 #define RZG2L_CHANNELS_PER_IO 2 @@ -395,6 +403,96 @@ static const struct pwm_ops rzg2l_gpt_ops =3D { .apply =3D rzg2l_gpt_apply, }; =20 +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D dev_get_drvdata(dev); + u8 bitpos =3D grp * RZG2L_MAX_HW_CHANNELS; + unsigned int i; + u8 irq_bitpos; + u32 irq_bits; + u32 val =3D 0; + u32 reg; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + else + irq_bitpos =3D (3 * i); + + reg =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTST(i)); + irq_bits =3D FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg); + val |=3D (irq_bits << irq_bitpos); + } + + return val; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status); + +int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D dev_get_drvdata(dev); + u8 bitpos =3D grp * RZG2L_MAX_HW_CHANNELS; + unsigned int i; + u32 reg; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + reg =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTST(i)); + if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF)) + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(i), + RZG2L_GTIOR_OBE, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr); + +int rzg2l_gpt_pin_reenable(void *dev, u8 grp) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D dev_get_drvdata(dev); + u8 bitpos =3D grp * RZG2L_MAX_HW_CHANNELS; + unsigned int i; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(i), + RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE); + } + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable); + +static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op,= bool on) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D dev_get_drvdata(dev); + u8 bitpos =3D grp * RZG2L_MAX_HW_CHANNELS; + unsigned int i; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + if (on) + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(i), op, op); + else + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(i), op, 0); + } + + return 0; +} + +int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) +{ + int id =3D RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); + /* * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and * configure the pin for output disable. @@ -526,6 +624,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) return dev_err_probe(dev, ret, "Failed to link gpt with poeg\n"); =20 mutex_init(&rzg2l_gpt->lock); + platform_set_drvdata(pdev, rzg2l_gpt); =20 chip->ops =3D &rzg2l_gpt_ops; ret =3D devm_pwmchip_add(dev, chip); diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h new file mode 100644 index 000000000000..718aaeca39f2 --- /dev/null +++ b/include/linux/pwm/rzg2l-gpt.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PWM_RENESAS_RZG2L_GPT_H__ +#define __LINUX_PWM_RENESAS_RZG2L_GPT_H__ + +#if IS_ENABLED(CONFIG_PWM_RENESAS_RZG2L_GPT) +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:52 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 10/15] pwm: rzg2l-gpt: Add support for output disable when both output low Date: Fri, 21 Nov 2025 16:08:17 +0000 Message-ID: <20251121160842.371922-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das This patch adds support for output disable request from gpt, when same time output level is low. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 8006c62068b6..a0100e1b948d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -85,6 +85,7 @@ =20 #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) =20 #define RZG2L_GTST_OABHF BIT(29) #define RZG2L_GTST_OABLF BIT(30) @@ -493,6 +494,14 @@ int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8= grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); =20 +int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) +{ + int id =3D RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); + /* * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and * configure the pin for output disable. diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index 718aaeca39f2..adb5b9cfc8b3 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -7,6 +7,7 @@ u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp= ); int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on= ); +int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -28,6 +29,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_high(v= oid *gpt_device, u8 grp, return -ENODEV; } =20 +static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8= grp, bool on) +{ + return -ENODEV; +} + #endif =20 #endif /* __LINUX_PWM_RENESAS_RZG2L_GPT_H__ */ --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 807EA34EF14 for ; Fri, 21 Nov 2025 16:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:52 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 11/15] pwm: rzg2l-gpt: Add support for output disable on dead time error Date: Fri, 21 Nov 2025 16:08:18 +0000 Message-ID: <20251121160842.371922-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das This patch adds support for output disable request from gpt, when dead time error occurred. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index a0100e1b948d..0e158f677f01 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -84,6 +84,7 @@ RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH) =20 #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR BIT(28) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) =20 @@ -502,6 +503,14 @@ int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 = grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); =20 +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *dev, u8 grp, bool on) +{ + int id =3D RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_deadtime_error); + /* * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and * configure the pin for output disable. diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index adb5b9cfc8b3..f9365bbca57c 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -8,6 +8,7 @@ int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp= ); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on= ); int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *gpt_device, u8 grp, bo= ol on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -34,6 +35,10 @@ static inline int rzg2l_gpt_poeg_disable_req_both_low(vo= id *gpt_device, u8 grp, return -ENODEV; } =20 +static inline int rzg2l_gpt_poeg_disable_req_deadtime_err(void *gpt_device= , u8 grp, bool on) +{ + return -ENODEV; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 12/15] pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable Request Date: Fri, 21 Nov 2025 16:08:19 +0000 Message-ID: <20251121160842.371922-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for output-disable requests from GPT. When both outputs are high, gpt detects the condition and triggers an interrupt to POEG. POEG handles the interrupt and send notification to userspace. userspace handles the fault and issue a write call to cancel the disable output request. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 86 ++++++++++++++++++++++- include/linux/pinctrl/rzg2l-poeg.h | 9 +++ 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/re= nesas/poeg/rzg2l-poeg.c index 2a09888407d0..3dd8bc3465b1 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -49,7 +50,10 @@ struct rzg2l_poeg_chip { struct device *gpt_dev; struct reset_control *rstc; void __iomem *mmio; + DECLARE_BITMAP(gpt_irq, 3); struct cdev poeg_cdev; + wait_queue_head_t events_wait; + DECLARE_KFIFO_PTR(events, struct poeg_event); u32 cfg; int minor_n; u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; @@ -81,12 +85,29 @@ static int rzg2l_poeg_output_disable_user(struct rzg2l_= poeg_chip *chip, bool ena return 0; } =20 +static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip *chip) +{ + if (test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, true); +} + static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) { struct rzg2l_poeg_chip *chip =3D ptr; + struct poeg_event ev; u32 val; =20 + val =3D rzg2l_gpt_poeg_disable_req_irq_status(chip->gpt_dev, chip->index); + ev.channel =3D chip->index; + ev.gpt_disable_irq_status =3D val; + kfifo_in(&chip->events, &ev, 1); + wake_up_poll(&chip->events_wait, EPOLLIN); + + rzg2l_gpt_poeg_disable_req_clr(chip->gpt_dev, chip->index); val =3D rzg2l_poeg_read(chip); + if (val & POEGG_IOCF) + val &=3D ~POEGG_IOCF; + if (val & POEGG_PIDF) val &=3D ~POEGG_PIDF; =20 @@ -95,7 +116,50 @@ static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) return IRQ_HANDLED; } =20 -static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, const char __use= r *buf, +static __poll_t rzg2l_poeg_chrdev_poll(struct file *filp, + struct poll_table_struct *pollt) +{ + struct rzg2l_poeg_chip *const chip =3D filp->private_data; + __poll_t events =3D 0; + + poll_wait(filp, &chip->events_wait, pollt); + if (!kfifo_is_empty(&chip->events)) + events =3D EPOLLIN | EPOLLRDNORM; + + return events; +} + +static ssize_t rzg2l_poeg_chrdev_read(struct file *filp, char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip =3D filp->private_data; + unsigned int copied; + int err; + + if (len < sizeof(struct poeg_event)) + return -EINVAL; + + do { + if (kfifo_is_empty(&chip->events)) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + err =3D wait_event_interruptible(chip->events_wait, + !kfifo_is_empty(&chip->events)); + if (err < 0) + return err; + } + + err =3D kfifo_to_user(&chip->events, buf, len, &copied); + if (err < 0) + return err; + } while (!copied); + + return copied; +} + +static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, + const char __user *buf, size_t len, loff_t *f_ps) { struct rzg2l_poeg_chip *const chip =3D filp->private_data; @@ -111,6 +175,12 @@ static ssize_t rzg2l_poeg_chrdev_write(struct file *fi= lp, const char __user *buf case RZG2L_POEG_OUTPUT_DISABLE_USR_DISABLE_CMD: rzg2l_poeg_output_disable_user(chip, false); break; + case RZG2L_POEG_GPT_CFG_IRQ_CMD: + rzg2l_poeg_config_irq(chip); + break; + case RZG2L_POEG_GPT_FAULT_CLR_CMD: + rzg2l_gpt_pin_reenable(chip->gpt_dev, chip->index); + break; default: return -EINVAL; } @@ -137,7 +207,9 @@ static int rzg2l_poeg_chrdev_release(struct inode *inod= e, struct file *filp) =20 static const struct file_operations poeg_fops =3D { .owner =3D THIS_MODULE, + .read =3D rzg2l_poeg_chrdev_read, .write =3D rzg2l_poeg_chrdev_write, + .poll =3D rzg2l_poeg_chrdev_poll, .open =3D rzg2l_poeg_chrdev_open, .release =3D rzg2l_poeg_chrdev_release, }; @@ -272,6 +344,9 @@ static int rzg2l_poeg_probe(struct platform_device *pde= v) case POEG_USER_CTRL: rzg2l_poeg_write(chip, 0); break; + case POEG_GPT_BOTH_HIGH: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + break; case POEG_EXT_PIN_CTRL: rzg2l_poeg_write(chip, POEGG_PIDE); break; @@ -280,8 +355,12 @@ static int rzg2l_poeg_probe(struct platform_device *pd= ev) goto err_pm; } =20 + if (cfg & POEG_GPT_ALL) + rzg2l_poeg_write(chip, POEGG_IOCE); + chip->cfg =3D cfg; =20 + init_waitqueue_head(&chip->events_wait); cdev_init(&chip->poeg_cdev, &poeg_fops); chip->poeg_cdev.owner =3D THIS_MODULE; ret =3D cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), chip->index),= 1); @@ -296,6 +375,10 @@ static int rzg2l_poeg_probe(struct platform_device *pd= ev) goto free_cdev; } =20 + ret =3D kfifo_alloc(&chip->events, 64, GFP_KERNEL); + if (ret) + goto free_cdev; + chip->minor_n =3D chip->index; =20 return ret; @@ -311,6 +394,7 @@ static void rzg2l_poeg_remove(struct platform_device *p= dev) { struct rzg2l_poeg_chip *chip =3D platform_get_drvdata(pdev); =20 + kfifo_free(&chip->events); device_destroy(poeg_class, MKDEV(MAJOR(g_poeg_dev), chip->minor_n)); cdev_del(&chip->poeg_cdev); pm_runtime_put(&pdev->dev); diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg= 2l-poeg.h index a5392f956700..311405b0137e 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -6,6 +6,15 @@ =20 #define RZG2L_POEG_OUTPUT_DISABLE_USR_DISABLE_CMD 0 #define RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD 1 +#define RZG2L_POEG_GPT_CFG_IRQ_CMD 2 +#define RZG2L_POEG_GPT_FAULT_CLR_CMD 3 + +#define RZG2L_GPT_OABHF 1 + +struct poeg_event { + __u32 gpt_disable_irq_status; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 13/15] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when both outputs are low Date: Fri, 21 Nov 2025 16:08:20 +0000 Message-ID: <20251121160842.371922-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das This patch adds support for output-disable requests from GPT, when both outputs are low. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 10 ++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/re= nesas/poeg/rzg2l-poeg.c index 3dd8bc3465b1..f66f69c5b1f7 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -89,6 +89,9 @@ static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip = *chip) { if (test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)) rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, true); + + if (test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, true); } =20 static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) @@ -347,9 +350,16 @@ static int rzg2l_poeg_probe(struct platform_device *pd= ev) case POEG_GPT_BOTH_HIGH: assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); break; + case POEG_GPT_BOTH_LOW: + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + break; case POEG_EXT_PIN_CTRL: rzg2l_poeg_write(chip, POEGG_PIDE); break; + case POEG_GPT_BOTH_HIGH_LOW: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + break; default: ret =3D -EINVAL; goto err_pm; diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg= 2l-poeg.h index 311405b0137e..ed3e08f10834 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -10,6 +10,7 @@ #define RZG2L_POEG_GPT_FAULT_CLR_CMD 3 =20 #define RZG2L_GPT_OABHF 1 +#define RZG2L_GPT_OABLF 2 =20 struct poeg_event { __u32 gpt_disable_irq_status; --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C39E534251A for ; Fri, 21 Nov 2025 16:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 14/15] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error Date: Fri, 21 Nov 2025 16:08:21 +0000 Message-ID: <20251121160842.371922-15-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for output disable request from gpt, when dead time error occurred. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 19 +++++++++++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/re= nesas/poeg/rzg2l-poeg.c index f66f69c5b1f7..d59e18832adf 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -92,6 +92,9 @@ static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip = *chip) =20 if (test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)) rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, true); + + if (test_bit(RZG2L_GPT_DTEF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index, tr= ue); } =20 static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) @@ -353,6 +356,9 @@ static int rzg2l_poeg_probe(struct platform_device *pde= v) case POEG_GPT_BOTH_LOW: assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); break; + case POEG_GPT_DEAD_TIME: + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; case POEG_EXT_PIN_CTRL: rzg2l_poeg_write(chip, POEGG_PIDE); break; @@ -360,6 +366,19 @@ static int rzg2l_poeg_probe(struct platform_device *pd= ev) assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); break; + case POEG_GPT_BOTH_HIGH_DEAD_TIME: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; + case POEG_GPT_BOTH_LOW_DEAD_TIME: + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; + case POEG_GPT_ALL: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; default: ret =3D -EINVAL; goto err_pm; diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg= 2l-poeg.h index ed3e08f10834..5edf719c155d 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -9,6 +9,7 @@ #define RZG2L_POEG_GPT_CFG_IRQ_CMD 2 #define RZG2L_POEG_GPT_FAULT_CLR_CMD 3 =20 +#define RZG2L_GPT_DTEF 0 #define RZG2L_GPT_OABHF 1 #define RZG2L_GPT_OABLF 2 =20 --=20 2.43.0 From nobody Tue Dec 2 01:05:41 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B95AB350D47 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm89496195e9.8.2025.11.21.08.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 08:08:55 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [DO NOT APPLY PATCH v8 15/15] tools: poeg: Add support for handling GPT output request disable Date: Fri, 21 Nov 2025 16:08:22 +0000 Message-ID: <20251121160842.371922-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> References: <20251121160842.371922-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for handling GPT output request disable. When GPT detects output disable condition, it request POEG and POEG triggers an interrupt after disabling the output. the clearing of interrupt happens in GPT. Add support for handling this in userspace, when POEG triggers interrupt, it sends an event to user space and user space send clear command to clear the gpt request for output disable. Signed-off-by: Biju Das --- tools/poeg/poeg_app.c | 57 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c index 4ff8e5c007dc..71f130d5aad2 100644 --- a/tools/poeg/poeg_app.c +++ b/tools/poeg/poeg_app.c @@ -20,9 +20,11 @@ =20 int main(int argc, char *argv[]) { + struct poeg_event event_data; struct poeg_cmd cmd; unsigned int val; long cmd_val; + int ret, fd; char *p; int i; =20 @@ -36,17 +38,52 @@ int main(int argc, char *argv[]) else printf("[POEG]open\n"); =20 - cmd.val =3D cmd_val; - cmd.channel =3D 4; - if (cmd.val =3D=3D RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD) - printf("[POEG] user control pin output disable enabled\n"); - else - printf("[POEG] user control pin output disable disabled\n"); + if (cmd_val =3D=3D RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD || + cmd_val =3D=3D RZG2L_POEG_OUTPUT_DISABLE_USR_DISABLE_CMD) { + if (cmd_val =3D=3D RZG2L_POEG_OUTPUT_DISABLE_USR_ENABLE_CMD) + printf("[POEG] user control pin output disable enabled\n"); + else + printf("[POEG] user control pin output disable disabled\n"); + + cmd.val =3D cmd_val; + cmd.channel =3D 4; + ret =3D write(fd, &cmd, sizeof(cmd)); + if (ret =3D=3D -1) { + perror("Failed to write cmd data"); + return 1; + } + } else { + printf("[POEG] GPT control configure IRQ\n"); + cmd.val =3D RZG2L_POEG_GPT_CFG_IRQ_CMD; + cmd.channel =3D 4; + ret =3D write(fd, &cmd, sizeof(cmd)); + if (ret =3D=3D -1) { + perror("Failed to write cmd data"); + return 1; + } + + for (;;) { + ret =3D read(fd, &event_data, sizeof(event_data)); + if (ret =3D=3D -1) { + perror("Failed to read event data"); + return 1; + } =20 - ret =3D write(fd, &cmd, sizeof(cmd)); - if (ret =3D=3D -1) { - perror("Failed to write cmd data"); - return 1; + val =3D event_data.gpt_disable_irq_status; + if (val) { + /* emulate fault clearing condition by adding delay */ + sleep(2); + for (i =3D 0; i < 8; i++) { + if (val & 7) { + printf("gpt ch:%u, irq=3D%x\n", i, val & 7); + cmd.val =3D RZG2L_POEG_GPT_FAULT_CLR_CMD; + cmd.channel =3D 4; + ret =3D write(fd, &cmd, sizeof(cmd)); + } + val >>=3D 3; + } + } + } } =20 if (close(fd) !=3D 0) --=20 2.43.0