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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Philipp Zabel , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 04/11] dt-bindings: net: dsa: renesas,rzn1-a5psw: Add RZ/T2H and RZ/N2H ETHSW support Date: Fri, 21 Nov 2025 11:35:30 +0000 Message-ID: <20251121113553.2955854-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251121113553.2955854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251121113553.2955854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar Extend the A5PSW DSA binding to cover the ETHSW variant used on newer Renesas RZ/T2H and RZ/N2H SoCs. ETHSW is derived from the A5PSW switch found on RZ/N1 but differs in register layout, clocking and interrupt topology, and exposes four ports in total (including the CPU/management port) instead of five. Update the schema to describe these differences by adding dedicated compatible strings for RZ/T2H and RZ/N2H, tightening requirements on clocks, resets and interrupts, and documenting the expanded 24-interrupt set used by ETHSW for timestamping and timer functions. Conditional validation ensures that RZ/T2H/RZ/N2H instances provide the correct resources while keeping the original A5PSW constraints intact. Use the RZ/T2H compatible string as the fallback for RZ/N2H, reflecting that both SoCs integrate the same ETHSW IP. Add myself as a co-maintainer of the binding to support ongoing work on the ETHSW family across RZ/T2H and RZ/N2H devices. Signed-off-by: Lad Prabhakar --- .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 154 +++++++++++++++--- 1 file changed, 130 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.y= aml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml index ea285ef3e64f..ec15ea4deeb0 100644 --- a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -4,43 +4,108 @@ $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Renesas RZ/N1 Advanced 5 ports ethernet switch +title: Renesas RZ/N1 A5PSW and RZ/T2H, RZ/N2H ETHSW Ethernet Switch =20 maintainers: - Cl=C3=A9ment L=C3=A9ger + - Lad Prabhakar =20 -description: | - The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family a= nd - handles 4 ports + 1 CPU management port. +description: > + This binding describes the Ethernet switch IPs used on Renesas SoCs: =20 -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports + - The A5PSW (Advanced 5-Port Switch) found on the RZ/N1 family, which + provides 4 external ports and 1 CPU/management port. + - The ETHSW (Ethernet Switch) found on the RZ/T2H and RZ/N2H families, + which is derived from the A5PSW IP with some register layout + differences, additional timestamping support, and a total of 4 ports + including the CPU/management port. =20 properties: compatible: - items: - - enum: - - renesas,r9a06g032-a5psw - - const: renesas,rzn1-a5psw + oneOf: + - items: + - enum: + - renesas,r9a06g032-a5psw + - const: renesas,rzn1-a5psw + + - const: renesas,r9a09g077-ethsw + + - items: + - const: renesas,r9a09g087-ethsw + - const: renesas,r9a09g077-ethsw =20 reg: maxItems: 1 =20 interrupts: - items: - - description: Device Level Ring (DLR) interrupt - - description: Switch interrupt - - description: Parallel Redundancy Protocol (PRP) interrupt - - description: Integrated HUB module interrupt - - description: Receive Pattern Match interrupt + oneOf: + - items: + - description: Device Level Ring (DLR) interrupt + - description: Switch interrupt + - description: Parallel Redundancy Protocol (PRP) interrupt + - description: Integrated HUB module interrupt + - description: Receive Pattern Match interrupt + + - items: + - description: Switch interrupt + - description: Device Level Ring (DLR) interrupt + - description: Parallel Redundancy Protocol (PRP) interrupt + - description: Integrated HUB module interrupt + - description: Receive Pattern Match interrupt 0 + - description: Receive Pattern Match interrupt 1 + - description: Receive Pattern Match interrupt 2 + - description: Receive Pattern Match interrupt 3 + - description: Receive Pattern Match interrupt 4 + - description: Receive Pattern Match interrupt 5 + - description: Receive Pattern Match interrupt 6 + - description: Receive Pattern Match interrupt 7 + - description: Receive Pattern Match interrupt 8 + - description: Receive Pattern Match interrupt 9 + - description: Receive Pattern Match interrupt 10 + - description: Receive Pattern Match interrupt 11 + - description: Switch timer pulse output interrupt 0 + - description: Switch timer pulse output interrupt 1 + - description: Switch timer pulse output interrupt 2 + - description: Switch timer pulse output interrupt 3 + - description: Switch TDMA timer output interrupt 0 + - description: Switch TDMA timer output interrupt 1 + - description: Switch TDMA timer output interrupt 2 + - description: Switch TDMA timer output interrupt 3 =20 interrupt-names: - items: - - const: dlr - - const: switch - - const: prp - - const: hub - - const: ptrn + oneOf: + - items: + - const: dlr + - const: switch + - const: prp + - const: hub + - const: ptrn + + - items: + - const: switch + - const: dlr + - const: prp + - const: hub + - const: ptrn0 + - const: ptrn1 + - const: ptrn2 + - const: ptrn3 + - const: ptrn4 + - const: ptrn5 + - const: ptrn6 + - const: ptrn7 + - const: ptrn8 + - const: ptrn9 + - const: ptrn10 + - const: ptrn11 + - const: tp0 + - const: tp1 + - const: tp2 + - const: tp3 + - const: tdma0 + - const: tdma1 + - const: tdma2 + - const: tdma3 =20 power-domains: maxItems: 1 @@ -50,14 +115,21 @@ properties: unevaluatedProperties: false =20 clocks: + minItems: 2 items: - description: AHB clock used for the switch register interface - description: Switch system clock + - description: Timestamp clock =20 clock-names: + minItems: 2 items: - const: hclk - const: clk + - const: ts + + resets: + maxItems: 1 =20 ethernet-ports: type: object @@ -73,14 +145,48 @@ properties: phandle pointing to a PCS sub-node compatible with renesas,rzn1-miic.yaml# =20 -unevaluatedProperties: false - required: - compatible - reg - clocks - clock-names - power-domains + - interrupts + - interrupt-names + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-ethsw + then: + properties: + interrupts: + minItems: 24 + interrupt-names: + minItems: 24 + clocks: + minItems: 3 + clock-names: + minItems: 3 + required: + - resets + else: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + resets: false + +unevaluatedProperties: false =20 examples: - | --=20 2.52.0