From nobody Tue Dec 2 02:04:15 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDF5C28750C; Fri, 21 Nov 2025 11:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722858; cv=none; b=jOw/S42rbvou7kUcszAAfvaOhshe668lzpm07kaIfLjq6Rhya4mHJIRD8PkV7ZBfStrIfbU7EXBcgM1KVek6t/I9okhcxx0h88AFfk/7aGIQUl6sXz8sPfNSSJ/N2JZq6Wxsy948N/w0ZLe5tSYFihpcoxoWXvpph48WfK28Q9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722858; c=relaxed/simple; bh=EjhpLxH1FgC0yuD9QJzF7H0xGchpQzLH+XxASmKO/Q8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rv5twT/4Y4UvBYsCRifKEPsVtRqAv2r7ytnVwN0x1sKriqV9MkvwlV2v9hClrLAIVkqFyFBFlC2wfAK012yHgPYSNKUQpn9atvxbjUeaC/f0jjkdK+z3pbzTQ2ofjDmTN4guH8wsM9gkw+bmx2qbtz8J+DUUpZIbK5PSd2C7gCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:42 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Date: Fri, 21 Nov 2025 18:59:33 +0800 Message-ID: <20251121105934.1759745-5-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-pll.c | 1068 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1083 insertions(+) create mode 100644 drivers/clk/meson/t7-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 71481607a6d5..6cdc6a96e105 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS help Support for the peripherals clock controller on Amlogic S805X2 and S905= Y4 devices, AKA S4. Say Y if you want S4 peripherals clock controller to w= ork. + +config COMMON_CLK_T7_PLL + tristate "Amlogic T7 SoC PLL controller support" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_PLL + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A311D2 based + device, AKA T7. PLLs are required by most peripheral to operate + Say Y if you are a T7 based device. + endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6998e752c68..8e3f7f94c639 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) +=3D s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) +=3D s4-peripherals.o +obj-$(CONFIG_COMMON_CLK_T7_PLL) +=3D t7-pll.o diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c new file mode 100644 index 000000000000..bee8a7489371 --- /dev/null +++ b/drivers/clk/meson/t7-pll.c @@ -0,0 +1,1068 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x00 +#define GP0PLL_CTRL1 0x04 +#define GP0PLL_CTRL2 0x08 +#define GP0PLL_CTRL3 0x0c +#define GP0PLL_CTRL4 0x10 +#define GP0PLL_CTRL5 0x14 +#define GP0PLL_CTRL6 0x18 +#define GP0PLL_STS 0x1c +#define GP1PLL_CTRL0 0x00 +#define GP1PLL_CTRL1 0x04 +#define GP1PLL_CTRL2 0x08 +#define GP1PLL_CTRL3 0x0c +#define GP1PLL_STS 0x1c +#define HIFIPLL_CTRL0 0x00 +#define HIFIPLL_CTRL1 0x04 +#define HIFIPLL_CTRL2 0x08 +#define HIFIPLL_CTRL3 0x0c +#define HIFIPLL_CTRL4 0x10 +#define HIFIPLL_CTRL5 0x14 +#define HIFIPLL_CTRL6 0x18 +#define HIFIPLL_STS 0x1c +#define PCIEPLL_CTRL0 0x00 +#define PCIEPLL_CTRL1 0x04 +#define PCIEPLL_CTRL2 0x08 +#define PCIEPLL_CTRL3 0x0c +#define PCIEPLL_CTRL4 0x10 +#define PCIEPLL_CTRL5 0x14 +#define PCIEPLL_STS 0x18 +#define MPLL_CTRL0 0x00 +#define MPLL_CTRL1 0x04 +#define MPLL_CTRL2 0x08 +#define MPLL_CTRL3 0x0c +#define MPLL_CTRL4 0x10 +#define MPLL_CTRL5 0x14 +#define MPLL_CTRL6 0x18 +#define MPLL_CTRL7 0x1c +#define MPLL_CTRL8 0x20 +#define MPLL_STS 0x24 +#define HDMIPLL_CTRL0 0x00 +#define HDMIPLL_CTRL1 0x04 +#define HDMIPLL_CTRL2 0x08 +#define HDMIPLL_CTRL3 0x0c +#define HDMIPLL_CTRL4 0x10 +#define HDMIPLL_CTRL5 0x14 +#define HDMIPLL_CTRL6 0x18 +#define HDMIPLL_STS 0x1c +#define MCLK_PLL_CNTL0 0x00 +#define MCLK_PLL_CNTL1 0x04 +#define MCLK_PLL_CNTL2 0x08 +#define MCLK_PLL_CNTL3 0x0c +#define MCLK_PLL_CNTL4 0x10 +#define MCLK_PLL_STS 0x14 + +static const struct pll_mult_range t7_media_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static const struct reg_sequence t7_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D GP0PLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D GP0PLL_CTRL3, .def =3D 0x48681c00 }, + { .reg =3D GP0PLL_CTRL4, .def =3D 0x88770290 }, + { .reg =3D GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D GP0PLL_CTRL6, .def =3D 0x56540000 }, +}; + +static struct clk_regmap t7_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_gp0_init_regs, + .init_count =3D ARRAY_SIZE(t7_gp0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short + */ +static const struct pll_mult_range t7_gp1_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static const struct reg_sequence t7_gp1_init_regs[] =3D { + { .reg =3D GP1PLL_CTRL1, .def =3D 0x1420500f }, + { .reg =3D GP1PLL_CTRL2, .def =3D 0x00023001 }, + { .reg =3D GP1PLL_CTRL3, .def =3D 0x00000000 }, +}; + +static struct clk_regmap t7_gp1_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP1PLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_gp1_pll_mult_range, + .init_regs =3D t7_gp1_init_regs, + .init_count =3D ARRAY_SIZE(t7_gp1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gp1_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_gp1_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D GP1PLL_CTRL0, + .shift =3D 12, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp1_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_gp1_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D HIFIPLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D HIFIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static struct clk_regmap t7_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .l =3D { + .reg_off =3D HIFIPLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_hifi_init_regs, + .init_count =3D ARRAY_SIZE(t7_hifi_init_regs), + .frac_max =3D 100000, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The T7 PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence t7_pcie_pll_init_regs[] =3D { + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x200c04c8 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x300c04c8 }, + { .reg =3D PCIEPLL_CTRL1, .def =3D 0x30000000 }, + { .reg =3D PCIEPLL_CTRL2, .def =3D 0x00001100 }, + { .reg =3D PCIEPLL_CTRL3, .def =3D 0x10058e00 }, + { .reg =3D PCIEPLL_CTRL4, .def =3D 0x000100c0 }, + { .reg =3D PCIEPLL_CTRL5, .def =3D 0x68000048 }, + { .reg =3D PCIEPLL_CTRL5, .def =3D 0x68000068, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL4, .def =3D 0x008100c0, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x340c04c8 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x140c04c8, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL2, .def =3D 0x00001000 } +}; + +static struct clk_regmap t7_pcie_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_pcie_pll_init_regs, + .init_count =3D ARRAY_SIZE(t7_pcie_pll_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_dco", + .ops =3D &meson_clk_pcie_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll_dco_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_dco_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_pcie_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PCIEPLL_CTRL0, + .shift =3D 16, + .width =3D 5, + /* the divisor is 32 when [16:21] =3D 0 */ + .flags =3D CLK_DIVIDER_MAX_AT_ZERO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_dco_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence t7_mpll0_init_regs[] =3D { + { .reg =3D MPLL_CTRL2, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll0_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll0_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL1, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll1_init_regs[] =3D { + { .reg =3D MPLL_CTRL4, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll1_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll1_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL3, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll1_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll2_init_regs[] =3D { + { .reg =3D MPLL_CTRL6, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll2_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll2_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll2_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL5, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll2_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll3_init_regs[] =3D { + { .reg =3D MPLL_CTRL8, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll3_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll3_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll3_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL7, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll3_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hdmi_init_regs[] =3D { + { .reg =3D HDMIPLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D HDMIPLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D HDMIPLL_CTRL3, .def =3D 0x6a28dc00 }, + { .reg =3D HDMIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HDMIPLL_CTRL5, .def =3D 0x39272000 }, + { .reg =3D HDMIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static struct clk_regmap t7_hdmi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .n =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_hdmi_init_regs, + .init_count =3D ARRAY_SIZE(t7_hdmi_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "in0", } + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_hdmi_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HDMIPLL_CTRL0, + .shift =3D 16, + .width =3D 4, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hdmi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_hdmi_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HDMIPLL_CTRL0, + .shift =3D 20, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hdmi_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct pll_mult_range t7_mclk_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static const struct reg_sequence t7_mclk_init_regs[] =3D { + { .reg =3D MCLK_PLL_CNTL1, .def =3D 0x1470500f }, + { .reg =3D MCLK_PLL_CNTL2, .def =3D 0x00023001 }, + { .reg =3D MCLK_PLL_CNTL3, .def =3D 0x18180000 }, + { .reg =3D MCLK_PLL_CNTL4, .def =3D 0x00180303 }, +}; + +static struct clk_regmap t7_mclk_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, + .l_detect =3D { + .reg_off =3D MCLK_PLL_CNTL2, + .shift =3D 6, + .width =3D 1, + }, + .range =3D &t7_mclk_pll_mult_range, + .init_regs =3D t7_mclk_init_regs, + .init_count =3D ARRAY_SIZE(t7_mclk_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +/* max div is 16 */ +static const struct clk_div_table t7_mclk_div[] =3D { + { .val =3D 0, .div =3D 1 }, + { .val =3D 1, .div =3D 2 }, + { .val =3D 2, .div =3D 4 }, + { .val =3D 3, .div =3D 8 }, + { .val =3D 4, .div =3D 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap t7_mclk_pre_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D MCLK_PLL_CNTL0, + .shift =3D 12, + .width =3D 3, + .table =3D t7_mclk_div, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pre_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D MCLK_PLL_CNTL4, + .shift =3D 16, + .width =3D 5, + .flags =3D CLK_DIVIDER_ONE_BASED, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_pre_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MCLK_PLL_CNTL4, + .mask =3D 0x3, + .shift =3D 4, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &t7_mclk_pll.hw }, + { .fw_name =3D "in1", }, + { .fw_name =3D "in2", }, + }, + .num_parents =3D 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_0_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mclk_0_sel.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_pre =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 2, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_0_pre", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_0_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_0_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MCLK_PLL_CNTL4, + .mask =3D 0x3, + .shift =3D 12, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &t7_mclk_pll.hw }, + { .fw_name =3D "in1", }, + { .fw_name =3D "in2", }, + }, + .num_parents =3D 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_1_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_1_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mclk_1_sel.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_pre =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_1_pre", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_1_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_1_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *t7_gp0_hw_clks[] =3D { + [CLKID_GP0_PLL_DCO] =3D &t7_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &t7_gp0_pll.hw, +}; + +static struct clk_hw *t7_gp1_hw_clks[] =3D { + [CLKID_GP1_PLL_DCO] =3D &t7_gp1_pll_dco.hw, + [CLKID_GP1_PLL] =3D &t7_gp1_pll.hw, +}; + +static struct clk_hw *t7_hifi_hw_clks[] =3D { + [CLKID_HIFI_PLL_DCO] =3D &t7_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &t7_hifi_pll.hw, +}; + +static struct clk_hw *t7_pcie_hw_clks[] =3D { + [CLKID_PCIE_PLL_DCO] =3D &t7_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] =3D &t7_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] =3D &t7_pcie_pll_od.hw, + [CLKID_PCIE_PLL] =3D &t7_pcie_pll.hw, +}; + +static struct clk_hw *t7_mpll_hw_clks[] =3D { + [CLKID_MPLL_PREDIV] =3D &t7_mpll_prediv.hw, + [CLKID_MPLL0_DIV] =3D &t7_mpll0_div.hw, + [CLKID_MPLL0] =3D &t7_mpll0.hw, + [CLKID_MPLL1_DIV] =3D &t7_mpll1_div.hw, + [CLKID_MPLL1] =3D &t7_mpll1.hw, + [CLKID_MPLL2_DIV] =3D &t7_mpll2_div.hw, + [CLKID_MPLL2] =3D &t7_mpll2.hw, + [CLKID_MPLL3_DIV] =3D &t7_mpll3_div.hw, + [CLKID_MPLL3] =3D &t7_mpll3.hw, +}; + +static struct clk_hw *t7_hdmi_hw_clks[] =3D { + [CLKID_HDMI_PLL_DCO] =3D &t7_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &t7_hdmi_pll_od.hw, + [CLKID_HDMI_PLL] =3D &t7_hdmi_pll.hw, +}; + +static struct clk_hw *t7_mclk_hw_clks[] =3D { + [CLKID_MCLK_PLL_DCO] =3D &t7_mclk_pll_dco.hw, + [CLKID_MCLK_PRE] =3D &t7_mclk_pre_od.hw, + [CLKID_MCLK_PLL] =3D &t7_mclk_pll.hw, + [CLKID_MCLK_0_SEL] =3D &t7_mclk_0_sel.hw, + [CLKID_MCLK_0_DIV2] =3D &t7_mclk_0_div2.hw, + [CLKID_MCLK_0_PRE] =3D &t7_mclk_0_pre.hw, + [CLKID_MCLK_0] =3D &t7_mclk_0.hw, + [CLKID_MCLK_1_SEL] =3D &t7_mclk_1_sel.hw, + [CLKID_MCLK_1_DIV2] =3D &t7_mclk_1_div2.hw, + [CLKID_MCLK_1_PRE] =3D &t7_mclk_1_pre.hw, + [CLKID_MCLK_1] =3D &t7_mclk_1.hw, +}; + +static const struct meson_clkc_data t7_gp0_data =3D { + .hw_clks =3D { + .hws =3D t7_gp0_hw_clks, + .num =3D ARRAY_SIZE(t7_gp0_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_gp1_data =3D { + .hw_clks =3D { + .hws =3D t7_gp1_hw_clks, + .num =3D ARRAY_SIZE(t7_gp1_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_hifi_data =3D { + .hw_clks =3D { + .hws =3D t7_hifi_hw_clks, + .num =3D ARRAY_SIZE(t7_hifi_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_pcie_data =3D { + .hw_clks =3D { + .hws =3D t7_pcie_hw_clks, + .num =3D ARRAY_SIZE(t7_pcie_hw_clks), + }, +}; + +static const struct reg_sequence t7_mpll_init_regs[] =3D { + { .reg =3D MPLL_CTRL0, .def =3D 0x00000543 } +}; + +static const struct meson_clkc_data t7_mpll_data =3D { + .hw_clks =3D { + .hws =3D t7_mpll_hw_clks, + .num =3D ARRAY_SIZE(t7_mpll_hw_clks), + }, + .init_regs =3D t7_mpll_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll_init_regs), +}; + +static const struct meson_clkc_data t7_hdmi_data =3D { + .hw_clks =3D { + .hws =3D t7_hdmi_hw_clks, + .num =3D ARRAY_SIZE(t7_hdmi_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_mclk_data =3D { + .hw_clks =3D { + .hws =3D t7_mclk_hw_clks, + .num =3D ARRAY_SIZE(t7_mclk_hw_clks), + }, +}; + +static const struct of_device_id t7_pll_clkc_match_table[] =3D { + { .compatible =3D "amlogic,t7-gp0-pll", .data =3D &t7_gp0_data, }, + { .compatible =3D "amlogic,t7-gp1-pll", .data =3D &t7_gp1_data, }, + { .compatible =3D "amlogic,t7-hifi-pll", .data =3D &t7_hifi_data, }, + { .compatible =3D "amlogic,t7-pcie-pll", .data =3D &t7_pcie_data, }, + { .compatible =3D "amlogic,t7-mpll", .data =3D &t7_mpll_data, }, + { .compatible =3D "amlogic,t7-hdmi-pll", .data =3D &t7_hdmi_data, }, + { .compatible =3D "amlogic,t7-mclk-pll", .data =3D &t7_mclk_data, }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); + +static struct platform_driver t7_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "t7-pll-clkc", + .of_match_table =3D t7_pll_clkc_match_table, + }, +}; +module_platform_driver(t7_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); +MODULE_AUTHOR("Jian Hu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.47.1