From nobody Tue Dec 2 02:04:16 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D446348456; Fri, 21 Nov 2025 11:14:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723696; cv=none; b=UblnzOWF+dtObWK2nsx/7QAA2EKog8KSxXdCkRIUmS/n3e3osWx1FVFL5LBx2yQ/YIx+uJoh9PUXw0P99suhOMQwTEIgJzTRLvMnlip4ANR2/yakFf3ZyNTR+zHVZ9sSUQsLCK00BlF0YUF5r6qb54No5iiOUWlOB+so5W3uX/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723696; c=relaxed/simple; bh=E5igYXBmCyNyaq/a26aueEflhZpCWAta5CLO4LkMre8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tu6OXHH7Was0HrYOWb8aQuPEEUqrsHwdfyJVlME9JZSXVezzdHbJjdy+3CL3cGFEEqAzXk8pw/ImQMu6LeI+FuN8yGf+prGSb8Hx1WPMQMQ8eRGLZKYp/dJqbJczBLBrTJe/cpyWEoqHfhgmL3+Myx2MEau+P4th8QauzqtMu7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:40 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , Conor Dooley , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller Date: Fri, 21 Nov 2025 18:59:30 +0800 Message-ID: <20251121105934.1759745-2-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu Reviewed-by: Conor Dooley --- .../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++++++++++++++++++ .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +++++++++ 2 files changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-= clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml new file mode 100644 index 000000000000..49c61f65deff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 PLL Clock Control Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + - Xianwei Zhao + +properties: + compatible: + enum: + - amlogic,t7-gp0-pll + - amlogic,t7-gp1-pll + - amlogic,t7-hifi-pll + - amlogic,t7-pcie-pll + - amlogic,t7-mpll + - amlogic,t7-hdmi-pll + - amlogic,t7-mclk-pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: mclk pll input oscillator gate + - description: oscillator input clock source for mclk_sel_0 + - description: fixed input clock source for mclk_sel_0 + minItems: 1 + + clock-names: + items: + - const: in0 + - const: in1 + - const: in2 + minItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: amlogic,t7-mclk-pll + + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,t7-gp0-pll + - amlogic,t7-gp1--pll + - amlogic,t7-hifi-pll + - amlogic,t7-pcie-pll + - amlogic,t7-mpll + - amlogic,t7-hdmi-pll + + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8080 { + compatible =3D "amlogic,t7-gp0-pll"; + reg =3D <0 0x8080 0 0x20>; + clocks =3D <&scmi_clk 2>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + clock-controller@8300 { + compatible =3D "amlogic,t7-mclk-pll"; + reg =3D <0 0x8300 0 0x18>; + clocks =3D <&scmi_clk 2>, + <&xtal>, + <&scmi_clk 31>; + clock-names =3D "in0", "in1", "in2"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-b= indings/clock/amlogic,t7-pll-clkc.h new file mode 100644 index 000000000000..e2481f2f1163 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_PLL_CLKC_H +#define __T7_PLL_CLKC_H + +/* GP0 */ +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 + +/* GP1 */ +#define CLKID_GP1_PLL_DCO 0 +#define CLKID_GP1_PLL 1 + +/* HIFI */ +#define CLKID_HIFI_PLL_DCO 0 +#define CLKID_HIFI_PLL 1 + +/* PCIE */ +#define CLKID_PCIE_PLL_DCO 0 +#define CLKID_PCIE_PLL_DCO_DIV2 1 +#define CLKID_PCIE_PLL_OD 2 +#define CLKID_PCIE_PLL 3 + +/* MPLL */ +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 + +/* HDMI */ +#define CLKID_HDMI_PLL_DCO 0 +#define CLKID_HDMI_PLL_OD 1 +#define CLKID_HDMI_PLL 2 + +/* MCLK */ +#define CLKID_MCLK_PLL_DCO 0 +#define CLKID_MCLK_PRE 1 +#define CLKID_MCLK_PLL 2 +#define CLKID_MCLK_0_SEL 3 +#define CLKID_MCLK_0_DIV2 4 +#define CLKID_MCLK_0_PRE 5 +#define CLKID_MCLK_0 6 +#define CLKID_MCLK_1_SEL 7 +#define CLKID_MCLK_1_DIV2 8 +#define CLKID_MCLK_1_PRE 9 +#define CLKID_MCLK_1 10 + +#endif /* __T7_PLL_CLKC_H */ --=20 2.47.1