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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:29.0891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d579ef9-6164-47e4-46ff-08de28e6c1bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9075 Content-Type: text/plain; charset="utf-8" This way the caller can select the one it wants to use. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 55 ++++++++++++++++--------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 353682c0e8f0..3d850893b97f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -177,6 +177,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_job *job, u32 nu /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @adev: the device being used + * @entity: entity to run the window setup job * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map @@ -189,6 +190,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_job *job, u32 nu * the physical address for local memory. */ static int amdgpu_ttm_map_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, struct ttm_buffer_object *bo, struct ttm_resource *mem, struct amdgpu_res_cursor *mm_cur, @@ -235,7 +237,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes =3D num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; =20 - r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, + r =3D amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, &job, @@ -275,6 +277,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, /** * amdgpu_ttm_copy_mem_to_mem - Helper function for copy * @adev: amdgpu device + * @entity: entity to run the jobs * @src: buffer/address where to read from * @dst: buffer/address where to write to * @size: number of bytes to copy @@ -289,6 +292,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, */ __attribute__((nonnull)) static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, const struct amdgpu_copy_mem *src, const struct amdgpu_copy_mem *dst, uint64_t size, bool tmz, @@ -320,12 +324,14 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_d= evice *adev, cur_size =3D min3(src_mm.size, dst_mm.size, 256ULL << 20); =20 /* Map src to window 0 and dst to window 1. */ - r =3D amdgpu_ttm_map_buffer(adev, src->bo, src->mem, &src_mm, + r =3D amdgpu_ttm_map_buffer(adev, entity, + src->bo, src->mem, &src_mm, 0, tmz, &cur_size, &from); if (r) goto error; =20 - r =3D amdgpu_ttm_map_buffer(adev, dst->bo, dst->mem, &dst_mm, + r =3D amdgpu_ttm_map_buffer(adev, entity, + dst->bo, dst->mem, &dst_mm, 1, tmz, &cur_size, &to); if (r) goto error; @@ -394,7 +400,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, src.offset =3D 0; dst.offset =3D 0; =20 - r =3D amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, + r =3D amdgpu_ttm_copy_mem_to_mem(adev, + &adev->mman.move_entity, + &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), bo->base.resv, &fence); @@ -2220,17 +2228,16 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, unsigned int num_dw, struct dma_resv *resv, bool vm_needs_flush, struct amdgpu_job **job, - bool delayed, u64 k_job_id) + u64 k_job_id) { enum amdgpu_ib_pool_type pool =3D AMDGPU_IB_POOL_DELAYED; int r; - struct drm_sched_entity *entity =3D delayed ? &adev->mman.clear_entity.ba= se : - &adev->mman.move_entity.base; - r =3D amdgpu_job_alloc_with_ib(adev, entity, + r =3D amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, pool, job, k_job_id); if (r) { @@ -2275,8 +2282,8 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, ui= nt64_t src_offset, max_bytes =3D adev->mman.buffer_funcs->copy_max_bytes; num_loops =3D DIV_ROUND_UP(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, num_dw, - resv, vm_needs_flush, &job, false, + r =3D amdgpu_ttm_prepare_job(adev, &adev->mman.move_entity, num_dw, + resv, vm_needs_flush, &job, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) goto error_free; @@ -2301,11 +2308,13 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, = uint64_t src_offset, return r; } =20 -static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, uint32_t src_da= ta, +static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint32_t src_data, uint64_t dst_addr, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, - bool vm_needs_flush, bool delayed, + bool vm_needs_flush, u64 k_job_id) { unsigned int num_loops, num_dw; @@ -2317,8 +2326,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *= adev, uint32_t src_data, max_bytes =3D adev->mman.buffer_funcs->fill_max_bytes; num_loops =3D DIV_ROUND_UP_ULL(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush, - &job, delayed, k_job_id); + r =3D amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, + vm_needs_flush, &job, k_job_id); if (r) return r; =20 @@ -2379,13 +2388,14 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, /* Never clear more than 256MiB at once to avoid timeouts */ size =3D min(cursor.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &cursor, + r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.clear_entity, + &bo->tbo, bo->tbo.resource, &cursor, 1, false, &size, &addr); if (r) goto err; =20 - r =3D amdgpu_ttm_fill_mem(adev, 0, addr, size, resv, - &next, true, true, + r =3D amdgpu_ttm_fill_mem(adev, &adev->mman.clear_entity, 0, addr, size,= resv, + &next, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) goto err; @@ -2409,10 +2419,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, u64 k_job_id) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_ttm_buffer_entity *entity; struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; int r; =20 + entity =3D delayed ? &adev->mman.clear_entity : + &adev->mman.move_entity; + if (!adev->mman.buffer_funcs_enabled) { dev_err(adev->dev, "Trying to clear memory with ring turned off.\n"); @@ -2429,13 +2443,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, /* Never fill more than 256MiB at once to avoid timeouts */ cur_size =3D min(dst.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &dst, + r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.default_entity, + &bo->tbo, bo->tbo.resource, &dst, 1, false, &cur_size, &to); if (r) goto error; =20 - r =3D amdgpu_ttm_fill_mem(adev, src_data, to, cur_size, resv, - &next, true, delayed, k_job_id); + r =3D amdgpu_ttm_fill_mem(adev, entity, src_data, to, cur_size, resv, + &next, true, k_job_id); if (r) goto error; =20 --=20 2.43.0