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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:08.4149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00d78700-f9e9-4495-b6e7-08de28e74479 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6754 Content-Type: text/plain; charset="utf-8" No functional change for now, as we always use entity 0. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 51 ++++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +- 3 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 2ee48f76483d..56663e82efef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1323,7 +1323,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) goto out; =20 r =3D amdgpu_fill_buffer(adev, - &adev->mman.clear_entity, abo, 0, &bo->base._resv, + &adev->mman.clear_entities[0], abo, 0, &bo->base._resv, &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 9024dde0c5a7..d7f041e43eca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2224,10 +2224,12 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); u32 used_windows, reserved_windows; + u32 num_clear_entities; uint64_t size; - int r; + int r, i, j; =20 - reserved_windows =3D 3; + num_clear_entities =3D adev->sdma.num_instances; + reserved_windows =3D 2 + num_clear_entities; =20 if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) @@ -2250,21 +2252,11 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) 1, NULL); if (r) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", + "Failed setting up TTM BO eviction entity (%d)\n", r); return 0; } =20 - r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { - dev_err(adev->dev, - "Failed setting up TTM BO clear entity (%d)\n", - r); - goto error_free_entity; - } - r =3D drm_sched_entity_init(&adev->mman.move_entity.base, DRM_SCHED_PRIORITY_NORMAL, &sched, 1, NULL); @@ -2272,26 +2264,48 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } =20 + adev->mman.num_clear_entities =3D num_clear_entities; + adev->mman.clear_entities =3D kcalloc(num_clear_entities, + sizeof(struct amdgpu_ttm_buffer_entity), + GFP_KERNEL); + if (!adev->mman.clear_entities) + goto error_free_entity; + + for (i =3D 0; i < num_clear_entities; i++) { + r =3D drm_sched_entity_init(&adev->mman.clear_entities[i].base, + DRM_SCHED_PRIORITY_NORMAL, &sched, + 1, NULL); + if (r) { + for (j =3D 0; j < i; j++) + drm_sched_entity_destroy( + &adev->mman.clear_entities[j].base); + kfree(adev->mman.clear_entities); + goto error_free_entity; + } + } + /* Statically assign GART windows to each entity. */ used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.default_entit= y, 0, false, false); used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, used_windows, true, true); - used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, - used_windows, false, true); + for (i =3D 0; i < num_clear_entities; i++) + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entiti= es[i], + used_windows, false, true); WARN_ON(used_windows !=3D reserved_windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); drm_sched_entity_destroy(&adev->mman.move_entity.base); + for (i =3D 0; i < num_clear_entities; i++) + drm_sched_entity_destroy(&adev->mman.clear_entities[i].base); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ ttm_resource_manager_cleanup(man); + kfree(adev->mman.clear_entities); } =20 /* this just adjusts TTM size idea, which sets lpfn to the correct value = */ @@ -2456,8 +2470,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *ade= v, =20 if (!fence) return -EINVAL; - - entity =3D &adev->mman.clear_entity; + entity =3D &adev->mman.clear_entities[0]; *fence =3D dma_fence_get_stub(); =20 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 0b3b03f43bab..250ef54a5550 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -72,8 +72,9 @@ struct amdgpu_mman { struct mutex gtt_window_lock; =20 struct amdgpu_ttm_buffer_entity default_entity; /* has no gart windows */ - struct amdgpu_ttm_buffer_entity clear_entity; struct amdgpu_ttm_buffer_entity move_entity; + struct amdgpu_ttm_buffer_entity *clear_entities; + u32 num_clear_entities; =20 struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; --=20 2.43.0