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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:16:37.0607 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 594f82e0-99a5-4bcb-6642-08de28e70e07 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8241 Content-Type: text/plain; charset="utf-8" ttm is going to use a variable number of windows so we need to get rid of the hardcoded value. Since amdgpu_gtt_mgr_init is initialized after amdgpu_ttm_set_buffer_funcs_status is called with enable=3Dfalse, we still need to determine the reserved windows count before doing the real initialisation so a warning is added if the actual value doesn't match the reserved one. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 3 ++- drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 12 ++++-------- 6 files changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_gtt_mgr.c index 895c1e4c6747..924151b6cfd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -269,10 +269,12 @@ static const struct ttm_resource_manager_func amdgpu_= gtt_mgr_func =3D { * * @adev: amdgpu_device pointer * @gtt_size: maximum size of GTT + * @reserved_windows: num of already used windows * * Allocate and initialize the GTT manager. */ -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, + u32 reserved_windows) { struct amdgpu_gtt_mgr *mgr =3D &adev->mman.gtt_mgr; struct ttm_resource_manager *man =3D &mgr->manager; @@ -283,8 +285,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uin= t64_t gtt_size) =20 ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); =20 - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - start +=3D amdgpu_vce_required_gart_pages(adev); + start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows; + start +=3D amdgpu_vce_required_gart_pages(adev, start); size =3D (adev->gmc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 1371a40d4687..3a0511d1739f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1907,6 +1907,7 @@ static int amdgpu_ttm_buffer_entity_init(struct amdgp= u_ttm_buffer_entity *entity int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; + u32 reserved_windows; int r; =20 dma_set_max_seg_size(adev->dev, UINT_MAX); @@ -1939,7 +1940,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Change the size here instead of the init above so only lpfn is affecte= d */ - amdgpu_ttm_set_buffer_funcs_status(adev, false); + reserved_windows =3D amdgpu_ttm_set_buffer_funcs_status(adev, false); #ifdef CONFIG_64BIT #ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) @@ -2035,7 +2036,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Initialize GTT memory pool */ - r =3D amdgpu_gtt_mgr_init(adev, gtt_size); + r =3D amdgpu_gtt_mgr_init(adev, gtt_size, reserved_windows); if (r) { dev_err(adev->dev, "Failed initializing GTT heap.\n"); return r; @@ -2174,17 +2175,21 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) * * Enable/disable use of buffer functions during suspend/resume. This shou= ld * only be called at bootup or when userspace isn't running. + * + * Returns: the number of GART reserved window */ -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool e= nable) +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool en= able) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); - u32 used_windows; + u32 used_windows, reserved_windows; uint64_t size; int r; =20 + reserved_windows =3D 3; + if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) - return; + return reserved_windows; =20 if (enable) { struct amdgpu_ring *ring; @@ -2199,7 +2204,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); - return; + return 0; } =20 r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, @@ -2230,6 +2235,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) used_windows, true, true); used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, used_windows, false, true); + WARN_ON(used_windows !=3D reserved_windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); drm_sched_entity_destroy(&adev->mman.clear_entity.base); @@ -2248,10 +2254,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) man->size =3D size; adev->mman.buffer_funcs_enabled =3D enable; =20 - return; + return reserved_windows; =20 error_free_entity: drm_sched_entity_destroy(&adev->mman.default_entity.base); + return 0; } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index a7eed678bd3f..2a78cf8a3f9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -40,7 +40,6 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -134,7 +133,7 @@ struct amdgpu_copy_mem { #define AMDGPU_COPY_FLAGS_GET(value, field) \ (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAG= S_##field##_MASK) =20 -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, u32= reserved_windows); void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); @@ -168,8 +167,8 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, =20 int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, - bool enable); +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, + bool enable); int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.c index a7d8f1ce6ac2..56308efce465 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -459,11 +459,13 @@ void amdgpu_vce_free_handles(struct amdgpu_device *ad= ev, struct drm_file *filp) * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. * For VCE2+, this is not needed so return zero. */ -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev, u64 gtt_tra= nsfer_end) { /* VCE IP block not added yet, so can't use amdgpu_ip_version */ - if (adev->family =3D=3D AMDGPU_FAMILY_SI) + if (adev->family =3D=3D AMDGPU_FAMILY_SI) { + adev->vce.gart_page_start =3D gtt_transfer_end; return 512; + } =20 return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.h index 1c3464ce5037..d07302535d33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -52,6 +52,7 @@ struct amdgpu_vce { uint32_t srbm_soft_reset; unsigned num_rings; uint32_t keyselect; + u64 gart_page_start; }; =20 int amdgpu_vce_early_init(struct amdgpu_device *adev); @@ -61,7 +62,7 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, st= ruct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *= filp); -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev, u64 gtt_tra= nsfer_end); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job= *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/am= dgpu/vce_v1_0.c index 9ae424618556..dd18fc45225d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -47,11 +47,6 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 =20 -#define VCE_V1_0_GART_PAGE_START \ - (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) -#define VCE_V1_0_GART_ADDR_START \ - (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) - static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); =20 @@ -541,6 +536,7 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct am= dgpu_device *adev) u64 num_pages =3D ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_= SIZE; u64 pa =3D amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags =3D AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VAL= ID; + u64 vce_gart_addr_start =3D adev->vce.gart_page_start * AMDGPU_GPU_PAGE_S= IZE; =20 /* * Check if the VCPU BO already has a 32-bit address. @@ -550,12 +546,12 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct = amdgpu_device *adev) return 0; =20 /* Check if we can map the VCPU BO in GART to a 32-bit address. */ - if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + if (adev->gmc.gart_start + vce_gart_addr_start > max_vcpu_bo_addr) return -EINVAL; =20 - amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_page_start, num_pages, flags, adev->gart.ptr); - adev->vce.gpu_addr =3D adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; + adev->vce.gpu_addr =3D adev->gmc.gart_start + vce_gart_addr_start; if (adev->vce.gpu_addr > max_vcpu_bo_addr) return -EINVAL; =20 --=20 2.43.0