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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:13:54.5104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cd90008-eee1-4513-ab29-08de28e6ad22 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7853 Content-Type: text/plain; charset="utf-8" Userspace jobs have drm_file.client_id as a unique identifier as job's owners. For kernel jobs, we can allocate arbitrary values - the risk of overlap with userspace ids is small (given that it's a u64 value). In the unlikely case the overlap happens, it'll only impact trace events. Since this ID is traced in the gpu_scheduler trace events, this allows to determine the source of each job sent to the hardware. To make grepping easier, the IDs are defined as they will appear in the trace output. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Signed-off-by: Arunpravin Paneer Selvam Link: https://lore.kernel.org/r/20250604122827.2191-1-pierre-eric.pelloux-p= rayer@amd.com Acked-by: Christian K=C3=B6nig Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 19 +++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 +++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 12 +++++---- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 ++- 19 files changed, 84 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gfx.c index 5a1904b0b064..1ffbd416a8ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1551,7 +1551,8 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct a= mdgpu_ring *ring) owner =3D (void *)(unsigned long)atomic_inc_return(&counter); =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, &entity, owner, - 64, 0, &job); + 64, 0, &job, + AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER); if (r) goto err; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index 0017bd10d452..ea8ec160b98a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -690,7 +690,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, - &job); + &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB); if (r) goto error_alloc; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_job.c index efa3281145f6..b284bd8021df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -232,11 +232,12 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, stru= ct amdgpu_vm *vm, int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, struct drm_sched_entity *entity, void *owner, size_t size, enum amdgpu_ib_pool_type pool_type, - struct amdgpu_job **job) + struct amdgpu_job **job, u64 k_job_id) { int r; =20 - r =3D amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 0); + r =3D amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, + k_job_id); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_job.h index d25f1fcf0242..7abf069d17d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -44,6 +44,22 @@ struct amdgpu_fence; enum amdgpu_ib_pool_type; =20 +/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */ +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE (18446744073709551615U= LL) +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES (18446744073709551614U= LL) +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE (18446744073709551613U= LL) +#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR (18446744073709551612U= LL) +#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER (18446744073709551611U= LL) +#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610U= LL) +#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER (18446744073709551609U= LL) +#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE (18446744073709551608U= LL) +#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT (18446744073709551607U= LL) +#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER (18446744073709551606U= LL) +#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER (18446744073709551605U= LL) +#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604U= LL) +#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603U= LL) +#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602U= LL) + struct amdgpu_job { struct drm_sched_job base; struct amdgpu_vm *vm; @@ -97,7 +113,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct = amdgpu_vm *vm, int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, struct drm_sched_entity *entity, void *owner, size_t size, enum amdgpu_ib_pool_type pool_type, - struct amdgpu_job **job); + struct amdgpu_job **job, + u64 k_job_id); void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gd= s, struct amdgpu_bo *gws, struct amdgpu_bo *oa); void amdgpu_job_free_resources(struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_jpeg.c index 91678621f1ff..63ee6ba6a931 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -196,7 +196,8 @@ static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *= ring, uint32_t handle, int i, r; =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, - AMDGPU_IB_POOL_DIRECT, &job); + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 24ebba43a469..926a3f09a776 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1322,7 +1322,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true); + r =3D amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true, + AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 04a79ef05f90..6a1434391fb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -226,7 +226,8 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_obje= ct *bo, r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, - AMDGPU_IB_POOL_DELAYED, &job); + AMDGPU_IB_POOL_DELAYED, &job, + AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER); if (r) return r; =20 @@ -398,7 +399,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, struct dma_fence *wipe_fence =3D NULL; =20 r =3D amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence, - false); + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -1480,7 +1481,8 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_b= uffer_object *bo, r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, AMDGPU_IB_POOL_DELAYED, - &job); + &job, + AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA); if (r) goto out; =20 @@ -2204,7 +2206,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devic= e *adev, struct dma_resv *resv, bool vm_needs_flush, struct amdgpu_job **job, - bool delayed) + bool delayed, u64 k_job_id) { enum amdgpu_ib_pool_type pool =3D direct_submit ? AMDGPU_IB_POOL_DIRECT : @@ -2214,7 +2216,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devic= e *adev, &adev->mman.high_pr; r =3D amdgpu_job_alloc_with_ib(adev, entity, AMDGPU_FENCE_OWNER_UNDEFINED, - num_dw * 4, pool, job); + num_dw * 4, pool, job, k_job_id); if (r) return r; =20 @@ -2254,7 +2256,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint= 64_t src_offset, num_loops =3D DIV_ROUND_UP(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); r =3D amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, - resv, vm_needs_flush, &job, false); + resv, vm_needs_flush, &job, false, + AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) return r; =20 @@ -2289,7 +2292,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ri= ng, uint32_t src_data, uint64_t dst_addr, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, - bool vm_needs_flush, bool delayed) + bool vm_needs_flush, bool delayed, + u64 k_job_id) { struct amdgpu_device *adev =3D ring->adev; unsigned int num_loops, num_dw; @@ -2302,7 +2306,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ri= ng, uint32_t src_data, num_loops =3D DIV_ROUND_UP_ULL(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); r =3D amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, - &job, delayed); + &job, delayed, k_job_id); if (r) return r; =20 @@ -2372,7 +2376,8 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, goto err; =20 r =3D amdgpu_ttm_fill_mem(ring, 0, addr, size, resv, - &next, true, true); + &next, true, true, + AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) goto err; =20 @@ -2391,7 +2396,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, uint32_t src_data, struct dma_resv *resv, struct dma_fence **f, - bool delayed) + bool delayed, + u64 k_job_id) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; @@ -2421,7 +2427,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, goto error; =20 r =3D amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, - &next, true, delayed); + &next, true, delayed, k_job_id); if (r) goto error; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 054d48823d5f..577ee04ce0bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -175,7 +175,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, uint32_t src_data, struct dma_resv *resv, struct dma_fence **fence, - bool delayed); + bool delayed, + u64 k_job_id); =20 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_uvd.c index 74758b5ffc6c..5c38f0d30c87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1136,7 +1136,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ri= ng, struct amdgpu_bo *bo, r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity, AMDGPU_FENCE_OWNER_UNDEFINED, 64, direct ? AMDGPU_IB_POOL_DIRECT : - AMDGPU_IB_POOL_DELAYED, &job); + AMDGPU_IB_POOL_DELAYED, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.c index 709ca369cb52..a7d8f1ce6ac2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -491,7 +491,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring= *ring, uint32_t handle, r =3D amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity, AMDGPU_FENCE_OWNER_UNDEFINED, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, - &job); + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 @@ -582,7 +582,8 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_rin= g *ring, uint32_t handle, AMDGPU_FENCE_OWNER_UNDEFINED, ib_size_dw * 4, direct ? AMDGPU_IB_POOL_DIRECT : - AMDGPU_IB_POOL_DELAYED, &job); + AMDGPU_IB_POOL_DELAYED, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vcn.c index 5ae7cc0d5f57..5e0786ea911b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -626,7 +626,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *= ring, =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 64, AMDGPU_IB_POOL_DIRECT, - &job); + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) goto err; =20 @@ -806,7 +806,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_rin= g *ring, =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, - &job); + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) goto err; =20 @@ -936,7 +936,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_= ring *ring, uint32_t hand =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, - &job); + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 @@ -1003,7 +1003,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdg= pu_ring *ring, uint32_t han =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, - &job); + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_vm.c index e2587eea6c4a..193de267984e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -989,7 +989,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, params.vm =3D vm; params.immediate =3D immediate; =20 - r =3D vm->update_funcs->prepare(¶ms, NULL); + r =3D vm->update_funcs->prepare(¶ms, NULL, + AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES); if (r) goto error; =20 @@ -1158,7 +1159,8 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev= , struct amdgpu_vm *vm, dma_fence_put(tmp); } =20 - r =3D vm->update_funcs->prepare(¶ms, sync); + r =3D vm->update_funcs->prepare(¶ms, sync, + AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE); if (r) goto error_free; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_vm.h index 330e4bdea387..139642eacdd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -310,7 +310,7 @@ struct amdgpu_vm_update_params { struct amdgpu_vm_update_funcs { int (*map_table)(struct amdgpu_bo_vm *bo); int (*prepare)(struct amdgpu_vm_update_params *p, - struct amdgpu_sync *sync); + struct amdgpu_sync *sync, u64 k_job_id); int (*update)(struct amdgpu_vm_update_params *p, struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_vm_cpu.c index 0c1ef5850a5e..22e2e5b47341 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -40,12 +40,14 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm = *table) * * @p: see amdgpu_vm_update_params definition * @sync: sync obj with fences to wait on + * @k_job_id: the id for tracing/debug purposes * * Returns: * Negativ errno, 0 for success. */ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, - struct amdgpu_sync *sync) + struct amdgpu_sync *sync, + u64 k_job_id) { if (!sync) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/am= d/amdgpu/amdgpu_vm_pt.c index f6ffc207ec2a..c7a7d51080a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -26,6 +26,7 @@ #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_vm.h" +#include "amdgpu_job.h" =20 /* * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt @@ -396,7 +397,8 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, stru= ct amdgpu_vm *vm, params.vm =3D vm; params.immediate =3D immediate; =20 - r =3D vm->update_funcs->prepare(¶ms, NULL); + r =3D vm->update_funcs->prepare(¶ms, NULL, + AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR); if (r) goto exit; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_vm_sdma.c index 46d9fb433ab2..36805dcfa159 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -40,7 +40,7 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *= table) =20 /* Allocate a new job for @count PTE updates */ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p, - unsigned int count) + unsigned int count, u64 k_job_id) { enum amdgpu_ib_pool_type pool =3D p->immediate ? AMDGPU_IB_POOL_IMMEDIATE : AMDGPU_IB_POOL_DELAYED; @@ -56,7 +56,7 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_upda= te_params *p, ndw =3D min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW); =20 r =3D amdgpu_job_alloc_with_ib(p->adev, entity, AMDGPU_FENCE_OWNER_VM, - ndw * 4, pool, &p->job); + ndw * 4, pool, &p->job, k_job_id); if (r) return r; =20 @@ -69,16 +69,17 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_up= date_params *p, * * @p: see amdgpu_vm_update_params definition * @sync: amdgpu_sync object with fences to wait for + * @k_job_id: identifier of the job, for tracing purpose * * Returns: * Negativ errno, 0 for success. */ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, - struct amdgpu_sync *sync) + struct amdgpu_sync *sync, u64 k_job_id) { int r; =20 - r =3D amdgpu_vm_sdma_alloc_job(p, 0); + r =3D amdgpu_vm_sdma_alloc_job(p, 0, k_job_id); if (r) return r; =20 @@ -249,7 +250,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_updat= e_params *p, if (r) return r; =20 - r =3D amdgpu_vm_sdma_alloc_job(p, count); + r =3D amdgpu_vm_sdma_alloc_job(p, count, + AMDGPU_KERNEL_JOB_ID_VM_UPDATE); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/am= dgpu/uvd_v6_0.c index 1c07b701d0e4..ceb94bbb03a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -217,7 +217,8 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ri= ng *ring, uint32_t handle int i, r; =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, - AMDGPU_IB_POOL_DIRECT, &job); + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 @@ -281,7 +282,8 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_r= ing *ring, int i, r; =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, - AMDGPU_IB_POOL_DIRECT, &job); + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/am= dgpu/uvd_v7_0.c index 9d237b5937fb..1f8866f3f63c 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -225,7 +225,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ri= ng *ring, u32 handle, int i, r; =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, - AMDGPU_IB_POOL_DIRECT, &job); + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 @@ -288,7 +289,8 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_r= ing *ring, u32 handle, int i, r; =20 r =3D amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, - AMDGPU_IB_POOL_DIRECT, &job); + AMDGPU_IB_POOL_DIRECT, &job, + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST); if (r) return r; =20 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 3653c563ee9a..46c84fc60af1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -67,7 +67,8 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, - &job); + &job, + AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP); if (r) return r; =20 --=20 2.43.0 From nobody Tue Dec 2 01:30:20 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010067.outbound.protection.outlook.com [52.101.56.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70F6E2F5A37 for ; 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Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Chrstian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 6a1434391fb8..8d0043ad5336 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2182,8 +2182,10 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) } else { drm_sched_entity_destroy(&adev->mman.high_pr); drm_sched_entity_destroy(&adev->mman.low_pr); - dma_fence_put(man->move); - man->move =3D NULL; + /* Drop all the old fences since re-creating the scheduler entities + * will allocate new contexts. + */ + ttm_resource_manager_cleanup(man); } =20 /* this just adjusts TTM size idea, which sets lpfn to the correct value = */ --=20 2.43.0 From nobody Tue Dec 2 01:30:20 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010016.outbound.protection.outlook.com [52.101.46.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D792E2C029F; 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Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 +++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +- 4 files changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/dr= m/amd/amdgpu/amdgpu_benchmark.c index 199693369c7c..02c2479a8840 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device = *adev, unsigned size, for (i =3D 0; i < n; i++) { struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; r =3D amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence, - false, false, 0); + false, 0); if (r) goto exit_do_move; r =3D dma_fence_wait(fence, false); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 8d0043ad5336..071afbacb3d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -346,7 +346,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, } =20 r =3D amdgpu_copy_buffer(ring, from, to, cur_size, resv, - &next, false, true, copy_flags); + &next, true, copy_flags); if (r) goto error; =20 @@ -2203,16 +2203,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, - bool direct_submit, unsigned int num_dw, struct dma_resv *resv, bool vm_needs_flush, struct amdgpu_job **job, bool delayed, u64 k_job_id) { - enum amdgpu_ib_pool_type pool =3D direct_submit ? - AMDGPU_IB_POOL_DIRECT : - AMDGPU_IB_POOL_DELAYED; + enum amdgpu_ib_pool_type pool =3D AMDGPU_IB_POOL_DELAYED; int r; struct drm_sched_entity *entity =3D delayed ? &adev->mman.low_pr : &adev->mman.high_pr; @@ -2238,7 +2235,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devic= e *adev, int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, - struct dma_fence **fence, bool direct_submit, + struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags) { struct amdgpu_device *adev =3D ring->adev; @@ -2248,7 +2245,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint= 64_t src_offset, unsigned int i; int r; =20 - if (!direct_submit && !ring->sched.ready) { + if (!ring->sched.ready) { dev_err(adev->dev, "Trying to move memory with ring turned off.\n"); return -EINVAL; @@ -2257,7 +2254,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint= 64_t src_offset, max_bytes =3D adev->mman.buffer_funcs->copy_max_bytes; num_loops =3D DIV_ROUND_UP(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, + r =3D amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush, &job, false, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) @@ -2275,10 +2272,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uin= t64_t src_offset, =20 amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); - if (direct_submit) - r =3D amdgpu_job_submit_direct(job, ring, fence); - else - *fence =3D amdgpu_job_submit(job); + *fence =3D amdgpu_job_submit(job); if (r) goto error_free; =20 @@ -2307,7 +2301,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ri= ng, uint32_t src_data, max_bytes =3D adev->mman.buffer_funcs->fill_max_bytes; num_loops =3D DIV_ROUND_UP_ULL(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, + r =3D amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush, &job, delayed, k_job_id); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 577ee04ce0bf..50e40380fe95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -166,7 +166,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_d= evice *adev, int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, - struct dma_fence **fence, bool direct_submit, + struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:08.2348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24e66c87-b4dd-480a-09a2-08de28e6b551 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9225 Content-Type: text/plain; charset="utf-8" With the removal of the direct_submit argument, the ring param becomes useless: the jobs are always submitted to buffer_funcs_ring. Some functions are getting an amdgpu_device argument since they were getting it from the ring arg. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 46 ++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +- 4 files changed, 27 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/dr= m/amd/amdgpu/amdgpu_benchmark.c index 02c2479a8840..3636b757c974 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -37,8 +37,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device = *adev, unsigned size, =20 stime =3D ktime_get(); for (i =3D 0; i < n; i++) { - struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; - r =3D amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence, + r =3D amdgpu_copy_buffer(adev, saddr, daddr, size, NULL, &fence, false, 0); if (r) goto exit_do_move; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 071afbacb3d2..d54b57078946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -164,11 +164,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_obje= ct *bo, =20 /** * amdgpu_ttm_map_buffer - Map memory into the GART windows + * @adev: the device being used * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map * @window: which GART window to use - * @ring: DMA ring to use for the copy * @tmz: if we should setup a TMZ enabled mapping * @size: in number of bytes to map, out number of bytes mapped * @addr: resulting address inside the MC address space @@ -176,15 +176,16 @@ static void amdgpu_evict_flags(struct ttm_buffer_obje= ct *bo, * Setup one of the GART windows to access a specific piece of memory or r= eturn * the physical address for local memory. */ -static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, +static int amdgpu_ttm_map_buffer(struct amdgpu_device *adev, + struct ttm_buffer_object *bo, struct ttm_resource *mem, struct amdgpu_res_cursor *mm_cur, - unsigned int window, struct amdgpu_ring *ring, + unsigned int window, bool tmz, uint64_t *size, uint64_t *addr) { - struct amdgpu_device *adev =3D ring->adev; unsigned int offset, num_pages, num_dw, num_bytes; uint64_t src_addr, dst_addr; + struct amdgpu_ring *ring; struct amdgpu_job *job; void *cpu_addr; uint64_t flags; @@ -239,6 +240,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_obje= ct *bo, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); =20 + ring =3D adev->mman.buffer_funcs_ring; amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); =20 @@ -286,7 +288,6 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, struct dma_resv *resv, struct dma_fence **f) { - struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; struct amdgpu_res_cursor src_mm, dst_mm; struct dma_fence *fence =3D NULL; int r =3D 0; @@ -312,13 +313,13 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_d= evice *adev, cur_size =3D min3(src_mm.size, dst_mm.size, 256ULL << 20); =20 /* Map src to window 0 and dst to window 1. */ - r =3D amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, - 0, ring, tmz, &cur_size, &from); + r =3D amdgpu_ttm_map_buffer(adev, src->bo, src->mem, &src_mm, + 0, tmz, &cur_size, &from); if (r) goto error; =20 - r =3D amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, - 1, ring, tmz, &cur_size, &to); + r =3D amdgpu_ttm_map_buffer(adev, dst->bo, dst->mem, &dst_mm, + 1, tmz, &cur_size, &to); if (r) goto error; =20 @@ -345,7 +346,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, write_compress_disable)); } =20 - r =3D amdgpu_copy_buffer(ring, from, to, cur_size, resv, + r =3D amdgpu_copy_buffer(adev, from, to, cur_size, resv, &next, true, copy_flags); if (r) goto error; @@ -2232,19 +2233,21 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_dev= ice *adev, DMA_RESV_USAGE_BOOKKEEP); } =20 -int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, +int amdgpu_copy_buffer(struct amdgpu_device *adev, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags) { - struct amdgpu_device *adev =3D ring->adev; unsigned int num_loops, num_dw; + struct amdgpu_ring *ring; struct amdgpu_job *job; uint32_t max_bytes; unsigned int i; int r; =20 + ring =3D adev->mman.buffer_funcs_ring; + if (!ring->sched.ready) { dev_err(adev->dev, "Trying to move memory with ring turned off.\n"); @@ -2284,15 +2287,15 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, ui= nt64_t src_offset, return r; } =20 -static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, +static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, uint32_t src_da= ta, uint64_t dst_addr, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, bool delayed, u64 k_job_id) { - struct amdgpu_device *adev =3D ring->adev; unsigned int num_loops, num_dw; + struct amdgpu_ring *ring; struct amdgpu_job *job; uint32_t max_bytes; unsigned int i; @@ -2316,6 +2319,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ri= ng, uint32_t src_data, byte_count -=3D cur_size; } =20 + ring =3D adev->mman.buffer_funcs_ring; amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); *fence =3D amdgpu_job_submit(job); @@ -2338,7 +2342,6 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_fence **fence) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; struct amdgpu_res_cursor cursor; u64 addr; int r =3D 0; @@ -2366,12 +2369,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, /* Never clear more than 256MiB at once to avoid timeouts */ size =3D min(cursor.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &cursor, - 1, ring, false, &size, &addr); + r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &cursor, + 1, false, &size, &addr); if (r) goto err; =20 - r =3D amdgpu_ttm_fill_mem(ring, 0, addr, size, resv, + r =3D amdgpu_ttm_fill_mem(adev, 0, addr, size, resv, &next, true, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) @@ -2396,7 +2399,6 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, u64 k_job_id) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; int r; @@ -2417,12 +2419,12 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, /* Never fill more than 256MiB at once to avoid timeouts */ cur_size =3D min(dst.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, - 1, ring, false, &cur_size, &to); + r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &dst, + 1, false, &cur_size, &to); if (r) goto error; =20 - r =3D amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, + r =3D amdgpu_ttm_fill_mem(adev, src_data, to, cur_size, resv, &next, true, delayed, k_job_id); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 50e40380fe95..76e00a6510c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -163,7 +163,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); -int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, +int amdgpu_copy_buffer(struct amdgpu_device *adev, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 378af0b2aaa9..0ad44acb08f2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -152,7 +152,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev= , dma_addr_t *sys, goto out_unlock; } =20 - r =3D amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE, + r =3D amdgpu_copy_buffer(adev, gart_s, gart_d, size * PAGE_SIZE, NULL, &next, true, 0); if (r) { dev_err(adev->dev, "fail %d to copy memory\n", r); --=20 2.43.0 From nobody Tue Dec 2 01:30:20 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010029.outbound.protection.outlook.com [52.101.56.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6982C029F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:14.7940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96c5ae34-c4a1-475f-a0bd-08de28e6b939 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8806 No functional change for now, but this struct will have more fields added in the next commit. Technically the change introduces synchronisation issue, because dependencies between successive jobs are not taken care of properly. For instance, amdgpu_ttm_clear_buffer uses amdgpu_ttm_map_buffer then amdgpu_ttm_fill_mem which use different entities (default_entity then move/clear entity). But it's all working as expected, because all entities use the same sdma instance for now and default_entity has a higher prio so its job always gets scheduler first. The next commits will deal with these dependencies correctly. Acked-by: Felix Kuehling Reviewed-by: Christian K=C3=B6nig --- v2: renamed amdgpu_ttm_buffer_entity --- Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 +++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 12 ++++++---- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 13 ++++++---- 4 files changed, 39 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index ea8ec160b98a..94e07b9ec7b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -687,7 +687,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, * itself at least for GART. */ mutex_lock(&adev->mman.gtt_window_lock); - r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, + r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.bas= e, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index d54b57078946..17e1892c44a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -224,7 +224,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes =3D num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; =20 - r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, &job, @@ -1479,7 +1479,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_b= uffer_object *bo, memcpy(adev->mman.sdma_access_ptr, buf, len); =20 num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); - r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job, @@ -2161,7 +2161,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) =20 ring =3D adev->mman.buffer_funcs_ring; sched =3D &ring->sched; - r =3D drm_sched_entity_init(&adev->mman.high_pr, + r =3D drm_sched_entity_init(&adev->mman.default_entity.base, DRM_SCHED_PRIORITY_KERNEL, &sched, 1, NULL); if (r) { @@ -2171,18 +2171,30 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) return; } =20 - r =3D drm_sched_entity_init(&adev->mman.low_pr, + r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, + DRM_SCHED_PRIORITY_NORMAL, &sched, + 1, NULL); + if (r) { + dev_err(adev->dev, + "Failed setting up TTM BO clear entity (%d)\n", + r); + goto error_free_entity; + } + + r =3D drm_sched_entity_init(&adev->mman.move_entity.base, DRM_SCHED_PRIORITY_NORMAL, &sched, 1, NULL); if (r) { dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); + drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } } else { - drm_sched_entity_destroy(&adev->mman.high_pr); - drm_sched_entity_destroy(&adev->mman.low_pr); + drm_sched_entity_destroy(&adev->mman.default_entity.base); + drm_sched_entity_destroy(&adev->mman.clear_entity.base); + drm_sched_entity_destroy(&adev->mman.move_entity.base); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ @@ -2200,7 +2212,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) return; =20 error_free_entity: - drm_sched_entity_destroy(&adev->mman.high_pr); + drm_sched_entity_destroy(&adev->mman.default_entity.base); } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, @@ -2212,8 +2224,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devic= e *adev, { enum amdgpu_ib_pool_type pool =3D AMDGPU_IB_POOL_DELAYED; int r; - struct drm_sched_entity *entity =3D delayed ? &adev->mman.low_pr : - &adev->mman.high_pr; + struct drm_sched_entity *entity =3D delayed ? &adev->mman.clear_entity.ba= se : + &adev->mman.move_entity.base; r =3D amdgpu_job_alloc_with_ib(adev, entity, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, pool, job, k_job_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 76e00a6510c6..41bbc25680a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -52,6 +52,10 @@ struct amdgpu_gtt_mgr { spinlock_t lock; }; =20 +struct amdgpu_ttm_buffer_entity { + struct drm_sched_entity base; +}; + struct amdgpu_mman { struct ttm_device bdev; struct ttm_pool *ttm_pools; @@ -64,10 +68,10 @@ struct amdgpu_mman { bool buffer_funcs_enabled; =20 struct mutex gtt_window_lock; - /* High priority scheduler entity for buffer moves */ - struct drm_sched_entity high_pr; - /* Low priority scheduler entity for VRAM clearing */ - struct drm_sched_entity low_pr; + + struct amdgpu_ttm_buffer_entity default_entity; + struct amdgpu_ttm_buffer_entity clear_entity; + struct amdgpu_ttm_buffer_entity move_entity; =20 struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 0ad44acb08f2..ade1d4068d29 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -45,7 +45,9 @@ svm_migrate_direct_mapping_addr(struct amdgpu_device *ade= v, u64 addr) } =20 static int -svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, +svm_migrate_gart_map(struct amdgpu_ring *ring, + struct amdgpu_ttm_buffer_entity *entity, + u64 npages, dma_addr_t *addr, u64 *gart_addr, u64 flags) { struct amdgpu_device *adev =3D ring->adev; @@ -63,7 +65,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes =3D npages * 8; =20 - r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r =3D amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, @@ -128,11 +130,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *ad= ev, dma_addr_t *sys, { const u64 GTT_MAX_PAGES =3D AMDGPU_GTT_MAX_TRANSFER_SIZE; struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; + struct amdgpu_ttm_buffer_entity *entity; u64 gart_s, gart_d; struct dma_fence *next; u64 size; int r; =20 + entity =3D &adev->mman.move_entity; + mutex_lock(&adev->mman.gtt_window_lock); =20 while (npages) { @@ -140,10 +145,10 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *ad= ev, dma_addr_t *sys, =20 if (direction =3D=3D FROM_VRAM_TO_RAM) { gart_s =3D svm_migrate_direct_mapping_addr(adev, *vram); - r =3D svm_migrate_gart_map(ring, size, sys, &gart_d, 0); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:21.0398 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2021f780-fc61-47e8-0f68-08de28e6bcf3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8425 Content-Type: text/plain; charset="utf-8" Deduplicate the IB padding code and will also be used later to check locking. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 34 ++++++++++++------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 17e1892c44a2..be1232b2d55e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -162,6 +162,18 @@ static void amdgpu_evict_flags(struct ttm_buffer_objec= t *bo, *placement =3D abo->placement; } =20 +static struct dma_fence * +amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_job *job, = u32 num_dw) +{ + struct amdgpu_ring *ring; + + ring =3D adev->mman.buffer_funcs_ring; + amdgpu_ring_pad_ib(ring, &job->ibs[0]); + WARN_ON(job->ibs[0].length_dw > num_dw); + + return amdgpu_job_submit(job); +} + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @adev: the device being used @@ -185,7 +197,6 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, { unsigned int offset, num_pages, num_dw, num_bytes; uint64_t src_addr, dst_addr; - struct amdgpu_ring *ring; struct amdgpu_job *job; void *cpu_addr; uint64_t flags; @@ -240,10 +251,6 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device = *adev, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); =20 - ring =3D adev->mman.buffer_funcs_ring; - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - flags =3D amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); if (tmz) flags |=3D AMDGPU_PTE_TMZ; @@ -261,7 +268,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); } =20 - dma_fence_put(amdgpu_job_submit(job)); + dma_fence_put(amdgpu_ttm_job_submit(adev, job, num_dw)); return 0; } =20 @@ -1497,10 +1504,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_= buffer_object *bo, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, 0); =20 - amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - - fence =3D amdgpu_job_submit(job); + fence =3D amdgpu_ttm_job_submit(adev, job, num_dw); =20 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) r =3D -ETIMEDOUT; @@ -2285,11 +2289,9 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, u= int64_t src_offset, byte_count -=3D cur_size_in_bytes; } =20 - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - *fence =3D amdgpu_job_submit(job); if (r) goto error_free; + *fence =3D amdgpu_ttm_job_submit(adev, job, num_dw); =20 return r; =20 @@ -2307,7 +2309,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *= adev, uint32_t src_data, u64 k_job_id) { unsigned int num_loops, num_dw; - struct amdgpu_ring *ring; struct amdgpu_job *job; uint32_t max_bytes; unsigned int i; @@ -2331,10 +2332,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device = *adev, uint32_t src_data, byte_count -=3D cur_size; } =20 - ring =3D adev->mman.buffer_funcs_ring; - amdgpu_ring_pad_ib(ring, &job->ibs[0]); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:25.1297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eab09efa-6aef-46b7-dfac-08de28e6bf62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5890 Content-Type: text/plain; charset="utf-8" If amdgpu_job_alloc_with_ib fails, amdgpu_ttm_prepare_job should clear the pointer to NULL, this way the caller can call amdgpu_job_free on all failures without risking a double free. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index be1232b2d55e..353682c0e8f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2233,8 +2233,10 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devi= ce *adev, r =3D amdgpu_job_alloc_with_ib(adev, entity, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, pool, job, k_job_id); - if (r) + if (r) { + *job =3D NULL; return r; + } =20 if (vm_needs_flush) { (*job)->vm_pd_addr =3D amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? @@ -2277,7 +2279,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, ui= nt64_t src_offset, resv, vm_needs_flush, &job, false, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) - return r; + goto error_free; =20 for (i =3D 0; i < num_loops; i++) { uint32_t cur_size_in_bytes =3D min(byte_count, max_bytes); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:29.0891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d579ef9-6164-47e4-46ff-08de28e6c1bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9075 Content-Type: text/plain; charset="utf-8" This way the caller can select the one it wants to use. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 55 ++++++++++++++++--------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 353682c0e8f0..3d850893b97f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -177,6 +177,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_job *job, u32 nu /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @adev: the device being used + * @entity: entity to run the window setup job * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map @@ -189,6 +190,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_job *job, u32 nu * the physical address for local memory. */ static int amdgpu_ttm_map_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, struct ttm_buffer_object *bo, struct ttm_resource *mem, struct amdgpu_res_cursor *mm_cur, @@ -235,7 +237,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes =3D num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; =20 - r =3D amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, + r =3D amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, &job, @@ -275,6 +277,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, /** * amdgpu_ttm_copy_mem_to_mem - Helper function for copy * @adev: amdgpu device + * @entity: entity to run the jobs * @src: buffer/address where to read from * @dst: buffer/address where to write to * @size: number of bytes to copy @@ -289,6 +292,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, */ __attribute__((nonnull)) static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, const struct amdgpu_copy_mem *src, const struct amdgpu_copy_mem *dst, uint64_t size, bool tmz, @@ -320,12 +324,14 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_d= evice *adev, cur_size =3D min3(src_mm.size, dst_mm.size, 256ULL << 20); =20 /* Map src to window 0 and dst to window 1. */ - r =3D amdgpu_ttm_map_buffer(adev, src->bo, src->mem, &src_mm, + r =3D amdgpu_ttm_map_buffer(adev, entity, + src->bo, src->mem, &src_mm, 0, tmz, &cur_size, &from); if (r) goto error; =20 - r =3D amdgpu_ttm_map_buffer(adev, dst->bo, dst->mem, &dst_mm, + r =3D amdgpu_ttm_map_buffer(adev, entity, + dst->bo, dst->mem, &dst_mm, 1, tmz, &cur_size, &to); if (r) goto error; @@ -394,7 +400,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, src.offset =3D 0; dst.offset =3D 0; =20 - r =3D amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, + r =3D amdgpu_ttm_copy_mem_to_mem(adev, + &adev->mman.move_entity, + &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), bo->base.resv, &fence); @@ -2220,17 +2228,16 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, unsigned int num_dw, struct dma_resv *resv, bool vm_needs_flush, struct amdgpu_job **job, - bool delayed, u64 k_job_id) + u64 k_job_id) { enum amdgpu_ib_pool_type pool =3D AMDGPU_IB_POOL_DELAYED; int r; - struct drm_sched_entity *entity =3D delayed ? &adev->mman.clear_entity.ba= se : - &adev->mman.move_entity.base; - r =3D amdgpu_job_alloc_with_ib(adev, entity, + r =3D amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, pool, job, k_job_id); if (r) { @@ -2275,8 +2282,8 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, ui= nt64_t src_offset, max_bytes =3D adev->mman.buffer_funcs->copy_max_bytes; num_loops =3D DIV_ROUND_UP(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, num_dw, - resv, vm_needs_flush, &job, false, + r =3D amdgpu_ttm_prepare_job(adev, &adev->mman.move_entity, num_dw, + resv, vm_needs_flush, &job, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) goto error_free; @@ -2301,11 +2308,13 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, = uint64_t src_offset, return r; } =20 -static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, uint32_t src_da= ta, +static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint32_t src_data, uint64_t dst_addr, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, - bool vm_needs_flush, bool delayed, + bool vm_needs_flush, u64 k_job_id) { unsigned int num_loops, num_dw; @@ -2317,8 +2326,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *= adev, uint32_t src_data, max_bytes =3D adev->mman.buffer_funcs->fill_max_bytes; num_loops =3D DIV_ROUND_UP_ULL(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush, - &job, delayed, k_job_id); + r =3D amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, + vm_needs_flush, &job, k_job_id); if (r) return r; =20 @@ -2379,13 +2388,14 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, /* Never clear more than 256MiB at once to avoid timeouts */ size =3D min(cursor.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &cursor, + r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.clear_entity, + &bo->tbo, bo->tbo.resource, &cursor, 1, false, &size, &addr); if (r) goto err; =20 - r =3D amdgpu_ttm_fill_mem(adev, 0, addr, size, resv, - &next, true, true, + r =3D amdgpu_ttm_fill_mem(adev, &adev->mman.clear_entity, 0, addr, size,= resv, + &next, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) goto err; @@ -2409,10 +2419,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, u64 k_job_id) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_ttm_buffer_entity *entity; struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; int r; =20 + entity =3D delayed ? &adev->mman.clear_entity : + &adev->mman.move_entity; + if (!adev->mman.buffer_funcs_enabled) { dev_err(adev->dev, "Trying to clear memory with ring turned off.\n"); @@ -2429,13 +2443,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, /* Never fill more than 256MiB at once to avoid timeouts */ cur_size =3D min(dst.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &bo->tbo, bo->tbo.resource, &dst, + r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.default_entity, + &bo->tbo, bo->tbo.resource, &dst, 1, false, &cur_size, &to); if (r) goto error; =20 - r =3D amdgpu_ttm_fill_mem(adev, src_data, to, cur_size, resv, - &next, true, delayed, k_job_id); + r =3D amdgpu_ttm_fill_mem(adev, entity, src_data, to, cur_size, resv, + &next, true, k_job_id); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:33.4560 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f71f6a36-8ec8-4a37-6317-08de28e6c459 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF183341E5B Content-Type: text/plain; charset="utf-8" This way the caller can select the one it wants to use. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 34 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 16 +++++---- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 +- 5 files changed, 32 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/dr= m/amd/amdgpu/amdgpu_benchmark.c index 3636b757c974..a050167e76a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -37,7 +37,8 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device = *adev, unsigned size, =20 stime =3D ktime_get(); for (i =3D 0; i < n; i++) { - r =3D amdgpu_copy_buffer(adev, saddr, daddr, size, NULL, &fence, + r =3D amdgpu_copy_buffer(adev, &adev->mman.default_entity, + saddr, daddr, size, NULL, &fence, false, 0); if (r) goto exit_do_move; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 926a3f09a776..858eb9fa061b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1322,8 +1322,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true, - AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + r =3D amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._res= v, + &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 3d850893b97f..1d3afad885da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -359,7 +359,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, write_compress_disable)); } =20 - r =3D amdgpu_copy_buffer(adev, from, to, cur_size, resv, + r =3D amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv, &next, true, copy_flags); if (r) goto error; @@ -414,8 +414,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence =3D NULL; =20 - r =3D amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence, - false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + r =3D amdgpu_fill_buffer(&adev->mman.move_entity, + abo, 0, NULL, &wipe_fence, + AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -2258,7 +2259,9 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_devic= e *adev, DMA_RESV_USAGE_BOOKKEEP); } =20 -int amdgpu_copy_buffer(struct amdgpu_device *adev, uint64_t src_offset, +int amdgpu_copy_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, @@ -2282,7 +2285,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, ui= nt64_t src_offset, max_bytes =3D adev->mman.buffer_funcs->copy_max_bytes; num_loops =3D DIV_ROUND_UP(byte_count, max_bytes); num_dw =3D ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); - r =3D amdgpu_ttm_prepare_job(adev, &adev->mman.move_entity, num_dw, + r =3D amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, vm_needs_flush, &job, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) @@ -2411,22 +2414,18 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, return r; } =20 -int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - bool delayed, - u64 k_job_id) +int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + uint32_t src_data, + struct dma_resv *resv, + struct dma_fence **f, + u64 k_job_id) { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ttm_buffer_entity *entity; struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; int r; =20 - entity =3D delayed ? &adev->mman.clear_entity : - &adev->mman.move_entity; - if (!adev->mman.buffer_funcs_enabled) { dev_err(adev->dev, "Trying to clear memory with ring turned off.\n"); @@ -2443,13 +2442,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, /* Never fill more than 256MiB at once to avoid timeouts */ cur_size =3D min(dst.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.default_entity, + r =3D amdgpu_ttm_map_buffer(adev, entity, &bo->tbo, bo->tbo.resource, &dst, 1, false, &cur_size, &to); if (r) goto error; =20 - r =3D amdgpu_ttm_fill_mem(adev, entity, src_data, to, cur_size, resv, + r =3D amdgpu_ttm_fill_mem(adev, entity, + src_data, to, cur_size, resv, &next, true, k_job_id); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 41bbc25680a2..9288599c9c46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -167,7 +167,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); -int amdgpu_copy_buffer(struct amdgpu_device *adev, uint64_t src_offset, +int amdgpu_copy_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, @@ -175,12 +177,12 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, ui= nt64_t src_offset, int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence); -int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **fence, - bool delayed, - u64 k_job_id); +int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + uint32_t src_data, + struct dma_resv *resv, + struct dma_fence **f, + u64 k_job_id); =20 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index ade1d4068d29..9c76f1ba0e55 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -157,7 +157,8 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev= , dma_addr_t *sys, goto out_unlock; } =20 - r =3D amdgpu_copy_buffer(adev, gart_s, gart_d, size * PAGE_SIZE, + r =3D amdgpu_copy_buffer(adev, entity, + gart_s, gart_d, size * PAGE_SIZE, NULL, &next, true, 0); if (r) { dev_err(adev->dev, "fail %d to copy memory\n", r); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:39.2887 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6907149-da9f-470e-d38b-08de28e6c7d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5763 Content-Type: text/plain; charset="utf-8" Instead of getting it through amdgpu_ttm_adev(bo->tbo.bdev). Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 ++++-- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 858eb9fa061b..2ee48f76483d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -725,7 +725,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type =3D=3D TTM_PL_VRAM) { struct dma_fence *fence; =20 - r =3D amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r =3D amdgpu_ttm_clear_buffer(adev, bo, bo->tbo.base.resv, &fence); if (unlikely(r)) goto fail_unreserve; =20 @@ -1322,7 +1322,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._res= v, + r =3D amdgpu_fill_buffer(adev, + &adev->mman.clear_entity, abo, 0, &bo->base._resv, &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 1d3afad885da..57dff2df433b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -414,7 +414,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence =3D NULL; =20 - r =3D amdgpu_fill_buffer(&adev->mman.move_entity, + r =3D amdgpu_fill_buffer(adev, &adev->mman.move_entity, abo, 0, NULL, &wipe_fence, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { @@ -2350,6 +2350,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *= adev, =20 /** * amdgpu_ttm_clear_buffer - clear memory buffers + * @adev: amdgpu device object * @bo: amdgpu buffer object * @resv: reservation object * @fence: dma_fence associated with the operation @@ -2359,11 +2360,11 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device= *adev, * Returns: * 0 for success or a negative error code on failure. */ -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, + struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence) { - struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_res_cursor cursor; u64 addr; int r =3D 0; @@ -2414,14 +2415,14 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, return r; } =20 -int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, +int amdgpu_fill_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, struct amdgpu_bo *bo, uint32_t src_data, struct dma_resv *resv, struct dma_fence **f, u64 k_job_id) { - struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 9288599c9c46..d0f55a7edd30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -174,10 +174,12 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, + struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:14:42.9825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 106a47d2-9aa9-4caa-4411-08de28e6ca07 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 Content-Type: text/plain; charset="utf-8" If multiple entities share the same window we must make sure that jobs using them are executed sequentially. This commit gives separate windows to each entity, so jobs from multiple entities could execute in parallel if needed. (for now they all use the first sdma engine, so it makes no difference yet). The entity stores the gart window offsets to centralize the "window id" to "window offset" in a single place. default_entity doesn't get any windows reserved since there is no use for them. --- v3: - renamed gart_window_lock -> lock (Christian) - added amdgpu_ttm_buffer_entity_init (Christian) - fixed gart_addr in svm_migrate_gart_map (Felix) - renamed gart_window_idX -> gart_window_offs[] - added amdgpu_compute_gart_address --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 56 ++++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 14 +++++- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 9 ++-- 4 files changed, 61 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index 94e07b9ec7b4..0d2784fe0be3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -686,7 +686,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, * translation. Avoid this by doing the invalidation from the SDMA * itself at least for GART. */ - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&adev->mman.default_entity.lock); r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.bas= e, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, @@ -699,7 +699,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, job->ibs->ptr[job->ibs->length_dw++] =3D ring->funcs->nop; amdgpu_ring_pad_ib(ring, &job->ibs[0]); fence =3D amdgpu_job_submit(job); - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); =20 dma_fence_wait(fence, false); dma_fence_put(fence); @@ -707,7 +707,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, return; =20 error_alloc: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); } =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 57dff2df433b..1371a40d4687 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -229,9 +229,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, =20 *size =3D min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); =20 - *addr =3D adev->gmc.gart_start; - *addr +=3D (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * - AMDGPU_GPU_PAGE_SIZE; + *addr =3D amdgpu_compute_gart_address(&adev->gmc, entity, window); *addr +=3D offset; =20 num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); @@ -249,7 +247,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, src_addr +=3D job->ibs[0].gpu_addr; =20 dst_addr =3D amdgpu_bo_gpu_offset(adev->gart.bo); - dst_addr +=3D window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; + dst_addr +=3D (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT)= * 8; amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); =20 @@ -314,7 +312,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, amdgpu_res_first(src->mem, src->offset, size, &src_mm); amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); =20 - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (src_mm.remaining) { uint64_t from, to, cur_size, tiling_flags; uint32_t num_type, data_format, max_com, write_compress_disable; @@ -371,7 +369,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, amdgpu_res_next(&dst_mm, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); *f =3D fence; return r; } @@ -1876,6 +1874,27 @@ static void amdgpu_ttm_mmio_remap_bo_fini(struct amd= gpu_device *adev) adev->rmmio_remap.bo =3D NULL; } =20 +static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *= entity, + int starting_gart_window, + bool needs_src_gart_window, + bool needs_dst_gart_window) +{ + mutex_init(&entity->lock); + if (needs_src_gart_window) { + entity->gart_window_offs[0] =3D + (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * + AMDGPU_GPU_PAGE_SIZE; + starting_gart_window++; + } + if (needs_dst_gart_window) { + entity->gart_window_offs[1] =3D + (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * + AMDGPU_GPU_PAGE_SIZE; + starting_gart_window++; + } + return starting_gart_window; +} + /* * amdgpu_ttm_init - Init the memory management (ttm) as well as various * gtt/vram related fields. @@ -1890,8 +1909,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) uint64_t gtt_size; int r; =20 - mutex_init(&adev->mman.gtt_window_lock); - dma_set_max_seg_size(adev->dev, UINT_MAX); /* No others user of address space so set it to 0 */ r =3D ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, @@ -2161,6 +2178,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool e= nable) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); + u32 used_windows; uint64_t size; int r; =20 @@ -2204,6 +2222,14 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } + + /* Statically assign GART windows to each entity. */ + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.default_entit= y, + 0, false, false); + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, + used_windows, true, true); + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, + used_windows, false, true); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); drm_sched_entity_destroy(&adev->mman.clear_entity.base); @@ -2365,6 +2391,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *ade= v, struct dma_resv *resv, struct dma_fence **fence) { + struct amdgpu_ttm_buffer_entity *entity; struct amdgpu_res_cursor cursor; u64 addr; int r =3D 0; @@ -2375,11 +2402,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *a= dev, if (!fence) return -EINVAL; =20 + entity =3D &adev->mman.clear_entity; *fence =3D dma_fence_get_stub(); =20 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); =20 - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (cursor.remaining) { struct dma_fence *next =3D NULL; u64 size; @@ -2392,13 +2420,13 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *a= dev, /* Never clear more than 256MiB at once to avoid timeouts */ size =3D min(cursor.size, 256ULL << 20); =20 - r =3D amdgpu_ttm_map_buffer(adev, &adev->mman.clear_entity, + r =3D amdgpu_ttm_map_buffer(adev, entity, &bo->tbo, bo->tbo.resource, &cursor, 1, false, &size, &addr); if (r) goto err; =20 - r =3D amdgpu_ttm_fill_mem(adev, &adev->mman.clear_entity, 0, addr, size,= resv, + r =3D amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, &next, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) @@ -2410,7 +2438,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *ade= v, amdgpu_res_next(&cursor, size); } err: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); =20 return r; } @@ -2435,7 +2463,7 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, =20 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); =20 - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (dst.remaining) { struct dma_fence *next; uint64_t cur_size, to; @@ -2461,7 +2489,7 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, amdgpu_res_next(&dst, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); if (f) *f =3D dma_fence_get(fence); dma_fence_put(fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index d0f55a7edd30..a7eed678bd3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -29,6 +29,7 @@ #include #include "amdgpu_vram_mgr.h" #include "amdgpu_hmm.h" +#include "amdgpu_gmc.h" =20 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -39,7 +40,7 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 +#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -54,6 +55,8 @@ struct amdgpu_gtt_mgr { =20 struct amdgpu_ttm_buffer_entity { struct drm_sched_entity base; + struct mutex lock; + u32 gart_window_offs[2]; }; =20 struct amdgpu_mman { @@ -69,7 +72,7 @@ struct amdgpu_mman { =20 struct mutex gtt_window_lock; =20 - struct amdgpu_ttm_buffer_entity default_entity; + struct amdgpu_ttm_buffer_entity default_entity; /* has no gart windows */ struct amdgpu_ttm_buffer_entity clear_entity; struct amdgpu_ttm_buffer_entity move_entity; =20 @@ -201,6 +204,13 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct = amdgpu_bo *bo, } #endif =20 +static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc, + struct amdgpu_ttm_buffer_entity *entity, + int index) +{ + return gmc->gart_start + entity->gart_window_offs[index]; +} + void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_ra= nge *range); int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 9c76f1ba0e55..0cc1d2b35026 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -59,8 +59,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, void *cpu_addr; int r; =20 - /* use gart window 0 */ - *gart_addr =3D adev->gmc.gart_start; + *gart_addr =3D amdgpu_compute_gart_address(&adev->gmc, entity, 0); =20 num_dw =3D ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes =3D npages * 8; @@ -116,7 +115,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, * multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wa= it for * the last sdma finish fence which is returned to check copy memory is do= ne. * - * Context: Process context, takes and releases gtt_window_lock + * Context: Process context * * Return: * 0 - OK, otherwise error code @@ -138,7 +137,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev= , dma_addr_t *sys, =20 entity =3D &adev->mman.move_entity; =20 - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); =20 while (npages) { size =3D min(GTT_MAX_PAGES, npages); @@ -175,7 +174,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev= , dma_addr_t *sys, } =20 out_unlock: - mutex_unlock(&adev->mman.gtt_window_lock); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:16:37.0607 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 594f82e0-99a5-4bcb-6642-08de28e70e07 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8241 Content-Type: text/plain; charset="utf-8" ttm is going to use a variable number of windows so we need to get rid of the hardcoded value. Since amdgpu_gtt_mgr_init is initialized after amdgpu_ttm_set_buffer_funcs_status is called with enable=3Dfalse, we still need to determine the reserved windows count before doing the real initialisation so a warning is added if the actual value doesn't match the reserved one. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 3 ++- drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 12 ++++-------- 6 files changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_gtt_mgr.c index 895c1e4c6747..924151b6cfd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -269,10 +269,12 @@ static const struct ttm_resource_manager_func amdgpu_= gtt_mgr_func =3D { * * @adev: amdgpu_device pointer * @gtt_size: maximum size of GTT + * @reserved_windows: num of already used windows * * Allocate and initialize the GTT manager. */ -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, + u32 reserved_windows) { struct amdgpu_gtt_mgr *mgr =3D &adev->mman.gtt_mgr; struct ttm_resource_manager *man =3D &mgr->manager; @@ -283,8 +285,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uin= t64_t gtt_size) =20 ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); =20 - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - start +=3D amdgpu_vce_required_gart_pages(adev); + start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows; + start +=3D amdgpu_vce_required_gart_pages(adev, start); size =3D (adev->gmc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 1371a40d4687..3a0511d1739f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1907,6 +1907,7 @@ static int amdgpu_ttm_buffer_entity_init(struct amdgp= u_ttm_buffer_entity *entity int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; + u32 reserved_windows; int r; =20 dma_set_max_seg_size(adev->dev, UINT_MAX); @@ -1939,7 +1940,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Change the size here instead of the init above so only lpfn is affecte= d */ - amdgpu_ttm_set_buffer_funcs_status(adev, false); + reserved_windows =3D amdgpu_ttm_set_buffer_funcs_status(adev, false); #ifdef CONFIG_64BIT #ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) @@ -2035,7 +2036,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Initialize GTT memory pool */ - r =3D amdgpu_gtt_mgr_init(adev, gtt_size); + r =3D amdgpu_gtt_mgr_init(adev, gtt_size, reserved_windows); if (r) { dev_err(adev->dev, "Failed initializing GTT heap.\n"); return r; @@ -2174,17 +2175,21 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) * * Enable/disable use of buffer functions during suspend/resume. This shou= ld * only be called at bootup or when userspace isn't running. + * + * Returns: the number of GART reserved window */ -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool e= nable) +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool en= able) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); - u32 used_windows; + u32 used_windows, reserved_windows; uint64_t size; int r; =20 + reserved_windows =3D 3; + if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) - return; + return reserved_windows; =20 if (enable) { struct amdgpu_ring *ring; @@ -2199,7 +2204,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); - return; + return 0; } =20 r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, @@ -2230,6 +2235,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) used_windows, true, true); used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, used_windows, false, true); + WARN_ON(used_windows !=3D reserved_windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); drm_sched_entity_destroy(&adev->mman.clear_entity.base); @@ -2248,10 +2254,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) man->size =3D size; adev->mman.buffer_funcs_enabled =3D enable; =20 - return; + return reserved_windows; =20 error_free_entity: drm_sched_entity_destroy(&adev->mman.default_entity.base); + return 0; } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index a7eed678bd3f..2a78cf8a3f9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -40,7 +40,6 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -134,7 +133,7 @@ struct amdgpu_copy_mem { #define AMDGPU_COPY_FLAGS_GET(value, field) \ (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAG= S_##field##_MASK) =20 -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, u32= reserved_windows); void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); @@ -168,8 +167,8 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, =20 int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, - bool enable); +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, + bool enable); int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.c index a7d8f1ce6ac2..56308efce465 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -459,11 +459,13 @@ void amdgpu_vce_free_handles(struct amdgpu_device *ad= ev, struct drm_file *filp) * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. * For VCE2+, this is not needed so return zero. */ -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev, u64 gtt_tra= nsfer_end) { /* VCE IP block not added yet, so can't use amdgpu_ip_version */ - if (adev->family =3D=3D AMDGPU_FAMILY_SI) + if (adev->family =3D=3D AMDGPU_FAMILY_SI) { + adev->vce.gart_page_start =3D gtt_transfer_end; return 512; + } =20 return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.h index 1c3464ce5037..d07302535d33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -52,6 +52,7 @@ struct amdgpu_vce { uint32_t srbm_soft_reset; unsigned num_rings; uint32_t keyselect; + u64 gart_page_start; }; =20 int amdgpu_vce_early_init(struct amdgpu_device *adev); @@ -61,7 +62,7 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, st= ruct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *= filp); -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev, u64 gtt_tra= nsfer_end); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job= *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/am= dgpu/vce_v1_0.c index 9ae424618556..dd18fc45225d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -47,11 +47,6 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 =20 -#define VCE_V1_0_GART_PAGE_START \ - (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) -#define VCE_V1_0_GART_ADDR_START \ - (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) - static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); =20 @@ -541,6 +536,7 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct am= dgpu_device *adev) u64 num_pages =3D ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_= SIZE; u64 pa =3D amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags =3D AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VAL= ID; + u64 vce_gart_addr_start =3D adev->vce.gart_page_start * AMDGPU_GPU_PAGE_S= IZE; =20 /* * Check if the VCPU BO already has a 32-bit address. @@ -550,12 +546,12 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct = amdgpu_device *adev) return 0; =20 /* Check if we can map the VCPU BO in GART to a 32-bit address. */ - if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + if (adev->gmc.gart_start + vce_gart_addr_start > max_vcpu_bo_addr) return -EINVAL; =20 - amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_page_start, num_pages, flags, adev->gart.ptr); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:16:45.6478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa03336d-edac-4b14-e772-08de28e71325 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9647 Content-Type: text/plain; charset="utf-8" Taking the entity lock is required to guarantee the ordering of execution. The next commit will add a check that the lock is held. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/dr= m/amd/amdgpu/amdgpu_benchmark.c index a050167e76a4..832d9ae101f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -35,6 +35,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device = *adev, unsigned size, struct dma_fence *fence; int i, r; =20 + mutex_lock(&adev->mman.default_entity.lock); stime =3D ktime_get(); for (i =3D 0; i < n; i++) { r =3D amdgpu_copy_buffer(adev, &adev->mman.default_entity, @@ -47,6 +48,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device = *adev, unsigned size, if (r) goto exit_do_move; } + mutex_unlock(&adev->mman.default_entity.lock); =20 exit_do_move: etime =3D ktime_get(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 3a0511d1739f..a803af015d05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1501,6 +1501,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_b= uffer_object *bo, if (r) goto out; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:16:54.9828 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfc83509-8aa2-477a-899e-08de28e718b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9496 Content-Type: text/plain; charset="utf-8" drm_sched_job_arm and drm_sched_entity_push_job must be called under the same lock to guarantee the order of execution. This commit adds a check in amdgpu_ttm_job_submit and fix the places where the lock was missing. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index a803af015d05..164b49d768d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -163,7 +163,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object= *bo, } =20 static struct dma_fence * -amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_job *job, = u32 num_dw) +amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer= _entity *entity, + struct amdgpu_job *job, u32 num_dw) { struct amdgpu_ring *ring; =20 @@ -171,6 +172,8 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_job *job, u32 nu amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); =20 + lockdep_assert_held(&entity->lock); + return amdgpu_job_submit(job); } =20 @@ -268,7 +271,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); } =20 - dma_fence_put(amdgpu_ttm_job_submit(adev, job, num_dw)); + dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw)); return 0; } =20 @@ -1512,7 +1515,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_b= uffer_object *bo, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, 0); =20 - fence =3D amdgpu_ttm_job_submit(adev, job, num_dw); + fence =3D amdgpu_ttm_job_submit(adev, &adev->mman.default_entity, job, nu= m_dw); mutex_unlock(&adev->mman.default_entity.lock); =20 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) @@ -2336,7 +2339,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, byte_count -=3D cur_size_in_bytes; } =20 - *fence =3D amdgpu_ttm_job_submit(adev, job, num_dw); + *fence =3D amdgpu_ttm_job_submit(adev, entity, job, num_dw); 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Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 2a78cf8a3f9f..0b3b03f43bab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -39,7 +39,7 @@ #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 -#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 +#define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; --=20 2.43.0 From nobody Tue Dec 2 01:30:20 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011015.outbound.protection.outlook.com [40.93.194.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A902710957 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:17:15.2177 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6358cf49-f40c-4b71-7c2f-08de28e724c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6548 Content-Type: text/plain; charset="utf-8" Entities' gart windows are contiguous so when copying a buffer and src doesn't need a gart window, its window can be used to extend dst one (and vice versa). This doubles the gart window size and reduces the number of jobs required. --- v2: pass adev instead of ring to amdgpu_ttm_needs_gart_window --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 78 ++++++++++++++++++------- 1 file changed, 58 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 164b49d768d8..489880b2fb8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -177,6 +177,21 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, stru= ct amdgpu_ttm_buffer_entit return amdgpu_job_submit(job); } =20 +static bool amdgpu_ttm_needs_gart_window(struct amdgpu_device *adev, + struct ttm_resource *mem, + struct amdgpu_res_cursor *mm_cur, + bool tmz, + uint64_t *addr) +{ + /* Map only what can't be accessed directly */ + if (!tmz && mem->start !=3D AMDGPU_BO_INVALID_OFFSET) { + *addr =3D amdgpu_ttm_domain_start(adev, mem->mem_type) + + mm_cur->start; + return false; + } + return true; +} + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @adev: the device being used @@ -185,6 +200,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_ttm_buffer_entit * @mem: memory object to map * @mm_cur: range to map * @window: which GART window to use + * @use_two_windows: if true, use a double window * @tmz: if we should setup a TMZ enabled mapping * @size: in number of bytes to map, out number of bytes mapped * @addr: resulting address inside the MC address space @@ -198,6 +214,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, struct ttm_resource *mem, struct amdgpu_res_cursor *mm_cur, unsigned int window, + bool use_two_windows, bool tmz, uint64_t *size, uint64_t *addr) { unsigned int offset, num_pages, num_dw, num_bytes; @@ -213,13 +230,8 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device = *adev, if (WARN_ON(mem->mem_type =3D=3D AMDGPU_PL_PREEMPT)) return -EINVAL; =20 - /* Map only what can't be accessed directly */ - if (!tmz && mem->start !=3D AMDGPU_BO_INVALID_OFFSET) { - *addr =3D amdgpu_ttm_domain_start(adev, mem->mem_type) + - mm_cur->start; + if (!amdgpu_ttm_needs_gart_window(adev, mem, mm_cur, tmz, addr)) return 0; - } - =20 /* * If start begins at an offset inside the page, then adjust the size @@ -228,7 +240,8 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_device *= adev, offset =3D mm_cur->start & ~PAGE_MASK; =20 num_pages =3D PFN_UP(*size + offset); - num_pages =3D min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE); + num_pages =3D min_t(uint32_t, + num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE * (use_two_windows ? 2 : 1)); =20 *size =3D min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); =20 @@ -300,7 +313,9 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_dev= ice *adev, struct dma_resv *resv, struct dma_fence **f) { + bool src_needs_gart_window, dst_needs_gart_window, use_two_gart_windows; struct amdgpu_res_cursor src_mm, dst_mm; + int src_gart_window, dst_gart_window; struct dma_fence *fence =3D NULL; int r =3D 0; uint32_t copy_flags =3D 0; @@ -324,18 +339,40 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_d= evice *adev, /* Never copy more than 256MiB at once to avoid a timeout */ cur_size =3D min3(src_mm.size, dst_mm.size, 256ULL << 20); =20 - /* Map src to window 0 and dst to window 1. */ - r =3D amdgpu_ttm_map_buffer(adev, entity, - src->bo, src->mem, &src_mm, - 0, tmz, &cur_size, &from); - if (r) - goto error; + /* If only one direction needs a gart window to access memory, use both + * windows for it. + */ + src_needs_gart_window =3D + amdgpu_ttm_needs_gart_window(adev, src->mem, &src_mm, tmz, &from); + dst_needs_gart_window =3D + amdgpu_ttm_needs_gart_window(adev, dst->mem, &dst_mm, tmz, &to); =20 - r =3D amdgpu_ttm_map_buffer(adev, entity, - dst->bo, dst->mem, &dst_mm, - 1, tmz, &cur_size, &to); - if (r) - goto error; + if (src_needs_gart_window) { + src_gart_window =3D 0; + use_two_gart_windows =3D !dst_needs_gart_window; + } + if (dst_needs_gart_window) { + dst_gart_window =3D src_needs_gart_window ? 1 : 0; + use_two_gart_windows =3D !src_needs_gart_window; + } + + if (src_needs_gart_window) { + r =3D amdgpu_ttm_map_buffer(adev, entity, + src->bo, src->mem, &src_mm, + src_gart_window, use_two_gart_windows, + tmz, &cur_size, &from); + if (r) + goto error; + } + + if (dst_needs_gart_window) { + r =3D amdgpu_ttm_map_buffer(adev, entity, + dst->bo, dst->mem, &dst_mm, + dst_gart_window, use_two_gart_windows, + tmz, &cur_size, &to); + if (r) + goto error; + } =20 abo_src =3D ttm_to_amdgpu_bo(src->bo); abo_dst =3D ttm_to_amdgpu_bo(dst->bo); @@ -2434,7 +2471,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *ade= v, =20 r =3D amdgpu_ttm_map_buffer(adev, entity, &bo->tbo, bo->tbo.resource, &cursor, - 1, false, &size, &addr); + 1, false, false, &size, &addr); if (r) goto err; =20 @@ -2485,7 +2522,8 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, =20 r =3D amdgpu_ttm_map_buffer(adev, entity, &bo->tbo, bo->tbo.resource, &dst, - 1, false, &cur_size, &to); + 1, false, false, + &cur_size, &to); if (r) goto error; =20 --=20 2.43.0 From nobody Tue Dec 2 01:30:20 2025 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012052.outbound.protection.outlook.com [52.101.48.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4098F33F8DA for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:17:41.2805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff97a502-34f5-4ad6-5043-08de28e7344d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E0.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8546 Content-Type: text/plain; charset="utf-8" All sdma versions used the same logic, so add a helper and move the common code to a single place. Reviewed-by: Christian K=C3=B6nig --- v2: pass amdgpu_vm_pte_funcs as well v3: drop all the *_set_vm_pte_funcs one liners --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++++++++++++ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 35 ++++++------------------ drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 35 ++++++------------------ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 29 ++++++-------------- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 29 ++++++-------------- drivers/gpu/drm/amd/amdgpu/si_dma.c | 31 ++++++--------------- 12 files changed, 105 insertions(+), 228 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index 790e84fec949..a50e3c0a4b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1612,6 +1612,8 @@ struct dma_fence *amdgpu_device_enforce_isolation(str= uct amdgpu_device *adev, bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs); =20 /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_vm.c index 193de267984e..5061d5b0f875 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3228,3 +3228,20 @@ void amdgpu_vm_print_task_info(struct amdgpu_device = *adev, task_info->process_name, task_info->tgid, task_info->task.comm, task_info->task.pid); } + +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs) +{ + struct drm_gpu_scheduler *sched; + int i; + + for (i =3D 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched =3D &adev->sdma.instance[i].page.sched; + else + sched =3D &adev->sdma.instance[i].ring.sched; + adev->vm_manager.vm_pte_scheds[i] =3D sched; + } + adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; + adev->vm_manager.vm_pte_funcs =3D vm_pte_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/am= dgpu/cik_sdma.c index 9e8715b4739d..22780c09177d 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -53,7 +53,6 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =3D static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); =20 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); @@ -919,6 +918,14 @@ static void cik_enable_sdma_mgls(struct amdgpu_device = *adev, } } =20 +static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D cik_sdma_vm_copy_pte, + + .write_pte =3D cik_sdma_vm_write_pte, + .set_pte_pde =3D cik_sdma_vm_set_pte_pde, +}; + static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -933,7 +940,7 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *= ip_block) cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); cik_sdma_set_buffer_funcs(adev); - cik_sdma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); =20 return 0; } @@ -1337,26 +1344,6 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_= device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D cik_sdma_vm_copy_pte, - - .write_pte =3D cik_sdma_vm_write_pte, - .set_pte_pde =3D cik_sdma_vm_set_pte_pde, -}; - -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &cik_sdma_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version cik_sdma_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v2_4.c index 92ce580647cd..0090ace49024 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -51,7 +51,6 @@ =20 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); =20 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); @@ -809,6 +808,14 @@ static void sdma_v2_4_ring_emit_wreg(struct amdgpu_rin= g *ring, amdgpu_ring_write(ring, val); } =20 +static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v2_4_vm_copy_pte, + + .write_pte =3D sdma_v2_4_vm_write_pte, + .set_pte_pde =3D sdma_v2_4_vm_set_pte_pde, +}; + static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -822,7 +829,7 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block = *ip_block) =20 sdma_v2_4_set_ring_funcs(adev); sdma_v2_4_set_buffer_funcs(adev); - sdma_v2_4_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); sdma_v2_4_set_irq_funcs(adev); =20 return 0; @@ -1232,26 +1239,6 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu= _device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v2_4_vm_copy_pte, - - .write_pte =3D sdma_v2_4_vm_write_pte, - .set_pte_pde =3D sdma_v2_4_vm_set_pte_pde, -}; - -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v2_4_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v2_4_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 2, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v3_0.c index 1c076bd1cf73..2526d393162a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -51,7 +51,6 @@ =20 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); =20 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); @@ -1082,6 +1081,14 @@ static void sdma_v3_0_ring_emit_wreg(struct amdgpu_r= ing *ring, amdgpu_ring_write(ring, val); } =20 +static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v3_0_vm_copy_pte, + + .write_pte =3D sdma_v3_0_vm_write_pte, + .set_pte_pde =3D sdma_v3_0_vm_set_pte_pde, +}; + static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1102,7 +1109,7 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v3_0_set_ring_funcs(adev); sdma_v3_0_set_buffer_funcs(adev); - sdma_v3_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); sdma_v3_0_set_irq_funcs(adev); =20 return 0; @@ -1674,26 +1681,6 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu= _device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v3_0_vm_copy_pte, - - .write_pte =3D sdma_v3_0_vm_write_pte, - .set_pte_pde =3D sdma_v3_0_vm_set_pte_pde, -}; - -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v3_0_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v3_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v4_0.c index f38004e6064e..a35d9951e22a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -129,7 +129,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _4_0[] =3D { =20 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); =20 @@ -1751,6 +1750,14 @@ static bool sdma_v4_0_fw_support_paging_queue(struct= amdgpu_device *adev) } } =20 +static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v4_0_vm_copy_pte, + + .write_pte =3D sdma_v4_0_vm_write_pte, + .set_pte_pde =3D sdma_v4_0_vm_set_pte_pde, +}; + static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1769,7 +1776,7 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v4_0_set_ring_funcs(adev); sdma_v4_0_set_buffer_funcs(adev); - sdma_v4_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); sdma_v4_0_set_irq_funcs(adev); sdma_v4_0_set_ras_funcs(adev); =20 @@ -2615,30 +2622,6 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu= _device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v4_0_vm_copy_pte, - - .write_pte =3D sdma_v4_0_vm_write_pte, - .set_pte_pde =3D sdma_v4_0_vm_set_pte_pde, -}; - -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v4_0_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched =3D &adev->sdma.instance[i].page.sched; - else - sched =3D &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] =3D sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - static void sdma_v4_0_get_ras_error_count(uint32_t value, uint32_t instance, uint32_t *sec_count) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd= /amdgpu/sdma_v4_4_2.c index a1443990d5c6..7f77367848d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -104,7 +104,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _4_4_2[] =3D { =20 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); @@ -1347,6 +1346,14 @@ static const struct amdgpu_sdma_funcs sdma_v4_4_2_sd= ma_funcs =3D { .soft_reset_kernel_queue =3D &sdma_v4_4_2_soft_reset_engine, }; =20 +static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v4_4_2_vm_copy_pte, + + .write_pte =3D sdma_v4_4_2_vm_write_pte, + .set_pte_pde =3D sdma_v4_4_2_vm_set_pte_pde, +}; + static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1362,7 +1369,7 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_bl= ock *ip_block) =20 sdma_v4_4_2_set_ring_funcs(adev); sdma_v4_4_2_set_buffer_funcs(adev); - sdma_v4_4_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); sdma_v4_4_2_set_irq_funcs(adev); sdma_v4_4_2_set_ras_funcs(adev); return 0; @@ -2316,30 +2323,6 @@ static void sdma_v4_4_2_set_buffer_funcs(struct amdg= pu_device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v4_4_2_vm_copy_pte, - - .write_pte =3D sdma_v4_4_2_vm_write_pte, - .set_pte_pde =3D sdma_v4_4_2_vm_set_pte_pde, -}; - -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v4_4_2_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched =3D &adev->sdma.instance[i].page.sched; - else - sched =3D &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] =3D sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - /** * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA * @adev: Pointer to the AMDGPU device structure diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v5_0.c index 8ddc4df06a1f..7ce13c5d4e61 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -110,7 +110,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _5_0[] =3D { =20 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring); @@ -1357,6 +1356,13 @@ static const struct amdgpu_sdma_funcs sdma_v5_0_sdma= _funcs =3D { .soft_reset_kernel_queue =3D &sdma_v5_0_soft_reset_engine, }; =20 +static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v5_0_vm_copy_pte, + .write_pte =3D sdma_v5_0_vm_write_pte, + .set_pte_pde =3D sdma_v5_0_vm_set_pte_pde, +}; + static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1368,7 +1374,7 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v5_0_set_ring_funcs(adev); sdma_v5_0_set_buffer_funcs(adev); - sdma_v5_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); sdma_v5_0_set_irq_funcs(adev); sdma_v5_0_set_mqd_funcs(adev); =20 @@ -2073,27 +2079,6 @@ static void sdma_v5_0_set_buffer_funcs(struct amdgpu= _device *adev) } } =20 -static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v5_0_vm_copy_pte, - .write_pte =3D sdma_v5_0_vm_write_pte, - .set_pte_pde =3D sdma_v5_0_vm_set_pte_pde, -}; - -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs =3D=3D NULL) { - adev->vm_manager.vm_pte_funcs =3D &sdma_v5_0_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v5_2.c index 51101b0aa2fa..98beff18cf28 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -111,7 +111,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _5_2[] =3D { =20 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring); @@ -1248,6 +1247,13 @@ static void sdma_v5_2_ring_emit_reg_write_reg_wait(s= truct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } =20 +static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v5_2_vm_copy_pte, + .write_pte =3D sdma_v5_2_vm_write_pte, + .set_pte_pde =3D sdma_v5_2_vm_set_pte_pde, +}; + static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1259,7 +1265,7 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v5_2_set_ring_funcs(adev); sdma_v5_2_set_buffer_funcs(adev); - sdma_v5_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); sdma_v5_2_set_irq_funcs(adev); sdma_v5_2_set_mqd_funcs(adev); =20 @@ -2084,27 +2090,6 @@ static void sdma_v5_2_set_buffer_funcs(struct amdgpu= _device *adev) } } =20 -static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v5_2_vm_copy_pte, - .write_pte =3D sdma_v5_2_vm_write_pte, - .set_pte_pde =3D sdma_v5_2_vm_set_pte_pde, -}; - -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs =3D=3D NULL) { - adev->vm_manager.vm_pte_funcs =3D &sdma_v5_2_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_2_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v6_0.c index e3f725bc2f29..c32331b72ba0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -119,7 +119,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _6_0[] =3D { =20 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v6_0_start(struct amdgpu_device *adev); =20 @@ -1268,6 +1267,13 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_de= vice *adev) } } =20 +static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 7, + .copy_pte =3D sdma_v6_0_vm_copy_pte, + .write_pte =3D sdma_v6_0_vm_write_pte, + .set_pte_pde =3D sdma_v6_0_vm_set_pte_pde, +}; + static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1296,7 +1302,7 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v6_0_set_ring_funcs(adev); sdma_v6_0_set_buffer_funcs(adev); - sdma_v6_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); sdma_v6_0_set_irq_funcs(adev); sdma_v6_0_set_mqd_funcs(adev); sdma_v6_0_set_ras_funcs(adev); @@ -1889,25 +1895,6 @@ static void sdma_v6_0_set_buffer_funcs(struct amdgpu= _device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 7, - .copy_pte =3D sdma_v6_0_vm_copy_pte, - .write_pte =3D sdma_v6_0_vm_write_pte, - .set_pte_pde =3D sdma_v6_0_vm_set_pte_pde, -}; - -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v6_0_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v6_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 6, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v7_0.c index 7fee98d37720..9318d23eb71e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -119,7 +119,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list= _7_0[] =3D { =20 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v7_0_start(struct amdgpu_device *adev); =20 @@ -1253,6 +1252,13 @@ static void sdma_v7_0_ring_emit_reg_write_reg_wait(s= truct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } =20 +static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 8, + .copy_pte =3D sdma_v7_0_vm_copy_pte, + .write_pte =3D sdma_v7_0_vm_write_pte, + .set_pte_pde =3D sdma_v7_0_vm_set_pte_pde, +}; + static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -1283,7 +1289,7 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_bloc= k *ip_block) =20 sdma_v7_0_set_ring_funcs(adev); sdma_v7_0_set_buffer_funcs(adev); - sdma_v7_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); sdma_v7_0_set_irq_funcs(adev); sdma_v7_0_set_mqd_funcs(adev); =20 @@ -1831,25 +1837,6 @@ static void sdma_v7_0_set_buffer_funcs(struct amdgpu= _device *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; } =20 -static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs =3D { - .copy_pte_num_dw =3D 8, - .copy_pte =3D sdma_v7_0_vm_copy_pte, - .write_pte =3D sdma_v7_0_vm_write_pte, - .set_pte_pde =3D sdma_v7_0_vm_set_pte_pde, -}; - -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs =3D &sdma_v7_0_vm_pte_funcs; - for (i =3D 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] =3D - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v7_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 7, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdg= pu/si_dma.c index 7f18e4875287..b85df997ed49 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -37,7 +37,6 @@ const u32 sdma_offsets[SDMA_MAX_INSTANCE] =3D =20 static void si_dma_set_ring_funcs(struct amdgpu_device *adev); static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); -static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); static void si_dma_set_irq_funcs(struct amdgpu_device *adev); =20 /** @@ -473,6 +472,14 @@ static void si_dma_ring_emit_wreg(struct amdgpu_ring *= ring, amdgpu_ring_write(ring, val); } =20 +static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs =3D { + .copy_pte_num_dw =3D 5, + .copy_pte =3D si_dma_vm_copy_pte, + + .write_pte =3D si_dma_vm_write_pte, + .set_pte_pde =3D si_dma_vm_set_pte_pde, +}; + static int si_dma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev =3D ip_block->adev; @@ -481,7 +488,7 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip= _block) =20 si_dma_set_ring_funcs(adev); si_dma_set_buffer_funcs(adev); - si_dma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); si_dma_set_irq_funcs(adev); =20 return 0; @@ -830,26 +837,6 @@ static void si_dma_set_buffer_funcs(struct amdgpu_devi= ce *adev) adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; 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Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++++ 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index 54f7c81f287b..7167db54d722 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3309,9 +3309,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device= *adev) if (r) goto init_failed; =20 - if (adev->mman.buffer_funcs_ring && - adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); =20 /* Don't init kfd if whole hive need to be reset during init */ if (adev->init_lvl->level !=3D AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { @@ -4191,8 +4189,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_devi= ce *adev) =20 r =3D amdgpu_device_ip_resume_phase2(adev); =20 - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); =20 if (r) return r; @@ -5321,8 +5318,7 @@ int amdgpu_device_suspend(struct drm_device *dev, boo= l notify_clients) return 0; =20 unwind_evict: - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); amdgpu_fence_driver_hw_init(adev); =20 unwind_userq: @@ -6050,8 +6046,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_re= set_context *reset_context) if (r) goto out; =20 - if (tmp_adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); =20 r =3D amdgpu_device_ip_resume_phase3(tmp_adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 489880b2fb8e..9024dde0c5a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2233,6 +2233,12 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) return reserved_windows; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:00.3951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e18b7b34-3410-4b9f-ec8b-08de28e73fb1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9269 Content-Type: text/plain; charset="utf-8" Until now ttm stored a single pipelined eviction fence which means drivers had to use a single entity for these evictions. To lift this requirement, this commit allows up to 8 entities to be used. Ideally a dma_resv object would have been used as a container of the eviction fences, but the locking rules makes it complex. dma_resv all have the same ww_class, which means "Attempting to lock more mutexes after ww_acquire_done." is an error. One alternative considered was to introduced a 2nd ww_class for specific resv to hold a single "transient" lock (=3D the resv lock would only be held for a short period, without taking any other locks). The other option, is to statically reserve a fence array, and extend the existing code to deal with N fences, instead of 1. The driver is still responsible to reserve the correct number of fence slots. Reviewed-by: Christian K=C3=B6nig --- v2: - simplified code - dropped n_fences - name changes v3: use ttm_resource_manager_cleanup --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- .../gpu/drm/ttm/tests/ttm_bo_validate_test.c | 11 +++-- drivers/gpu/drm/ttm/tests/ttm_resource_test.c | 5 +- drivers/gpu/drm/ttm/ttm_bo.c | 47 ++++++++++--------- drivers/gpu/drm/ttm/ttm_bo_util.c | 38 ++++++++++++--- drivers/gpu/drm/ttm/ttm_resource.c | 31 +++++++----- include/drm/ttm/ttm_resource.h | 29 ++++++++---- 6 files changed, 104 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c b/drivers/gpu= /drm/ttm/tests/ttm_bo_validate_test.c index 3148f5d3dbd6..8f71906c4238 100644 --- a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c +++ b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c @@ -651,7 +651,7 @@ static void ttm_bo_validate_move_fence_signaled(struct = kunit *test) int err; =20 man =3D ttm_manager_type(priv->ttm_dev, mem_type); - man->move =3D dma_fence_get_stub(); + man->eviction_fences[0] =3D dma_fence_get_stub(); =20 bo =3D ttm_bo_kunit_init(test, test->priv, size, NULL); bo->type =3D bo_type; @@ -668,7 +668,7 @@ static void ttm_bo_validate_move_fence_signaled(struct = kunit *test) KUNIT_EXPECT_EQ(test, ctx.bytes_moved, size); =20 ttm_bo_put(bo); - dma_fence_put(man->move); + dma_fence_put(man->eviction_fences[0]); } =20 static const struct ttm_bo_validate_test_case ttm_bo_validate_wait_cases[]= =3D { @@ -732,9 +732,9 @@ static void ttm_bo_validate_move_fence_not_signaled(str= uct kunit *test) =20 spin_lock_init(&fence_lock); man =3D ttm_manager_type(priv->ttm_dev, fst_mem); - man->move =3D alloc_mock_fence(test); + man->eviction_fences[0] =3D alloc_mock_fence(test); =20 - task =3D kthread_create(threaded_fence_signal, man->move, "move-fence-sig= nal"); + task =3D kthread_create(threaded_fence_signal, man->eviction_fences[0], "= move-fence-signal"); if (IS_ERR(task)) KUNIT_FAIL(test, "Couldn't create move fence signal task\n"); =20 @@ -742,7 +742,8 @@ static void ttm_bo_validate_move_fence_not_signaled(str= uct kunit *test) err =3D ttm_bo_validate(bo, placement_val, &ctx_val); dma_resv_unlock(bo->base.resv); =20 - dma_fence_wait_timeout(man->move, false, MAX_SCHEDULE_TIMEOUT); + dma_fence_wait_timeout(man->eviction_fences[0], false, MAX_SCHEDULE_TIMEO= UT); + man->eviction_fences[0] =3D NULL; =20 KUNIT_EXPECT_EQ(test, err, 0); KUNIT_EXPECT_EQ(test, ctx_val.bytes_moved, size); diff --git a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c b/drivers/gpu/dr= m/ttm/tests/ttm_resource_test.c index e6ea2bd01f07..c0e4e35e0442 100644 --- a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c +++ b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c @@ -207,6 +207,7 @@ static void ttm_resource_manager_init_basic(struct kuni= t *test) struct ttm_resource_test_priv *priv =3D test->priv; struct ttm_resource_manager *man; size_t size =3D SZ_16K; + int i; =20 man =3D kunit_kzalloc(test, sizeof(*man), GFP_KERNEL); KUNIT_ASSERT_NOT_NULL(test, man); @@ -216,8 +217,8 @@ static void ttm_resource_manager_init_basic(struct kuni= t *test) KUNIT_ASSERT_PTR_EQ(test, man->bdev, priv->devs->ttm_dev); KUNIT_ASSERT_EQ(test, man->size, size); KUNIT_ASSERT_EQ(test, man->usage, 0); - KUNIT_ASSERT_NULL(test, man->move); - KUNIT_ASSERT_NOT_NULL(test, &man->move_lock); + for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) + KUNIT_ASSERT_NULL(test, man->eviction_fences[i]); =20 for (int i =3D 0; i < TTM_MAX_BO_PRIORITY; ++i) KUNIT_ASSERT_TRUE(test, list_empty(&man->lru[i])); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index f4d9e68b21e7..0b3732ed6f6c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -658,34 +658,35 @@ void ttm_bo_unpin(struct ttm_buffer_object *bo) EXPORT_SYMBOL(ttm_bo_unpin); =20 /* - * Add the last move fence to the BO as kernel dependency and reserve a new - * fence slot. + * Add the pipelined eviction fencesto the BO as kernel dependency and res= erve new + * fence slots. */ -static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, - struct ttm_resource_manager *man, - bool no_wait_gpu) +static int ttm_bo_add_pipelined_eviction_fences(struct ttm_buffer_object *= bo, + struct ttm_resource_manager *man, + bool no_wait_gpu) { struct dma_fence *fence; - int ret; + int i; =20 - spin_lock(&man->move_lock); - fence =3D dma_fence_get(man->move); - spin_unlock(&man->move_lock); + spin_lock(&man->eviction_lock); + for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) { + fence =3D man->eviction_fences[i]; + if (!fence) + continue; =20 - if (!fence) - return 0; - - if (no_wait_gpu) { - ret =3D dma_fence_is_signaled(fence) ? 0 : -EBUSY; - dma_fence_put(fence); - return ret; + if (no_wait_gpu) { + if (!dma_fence_is_signaled(fence)) { + spin_unlock(&man->eviction_lock); + return -EBUSY; + } + } else { + dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + } } + spin_unlock(&man->eviction_lock); =20 - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); - - ret =3D dma_resv_reserve_fences(bo->base.resv, 1); - dma_fence_put(fence); - return ret; + /* TODO: this call should be removed. */ + return dma_resv_reserve_fences(bo->base.resv, 1); } =20 /** @@ -718,7 +719,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_obje= ct *bo, int i, ret; =20 ticket =3D dma_resv_locking_ctx(bo->base.resv); - ret =3D dma_resv_reserve_fences(bo->base.resv, 1); + ret =3D dma_resv_reserve_fences(bo->base.resv, TTM_NUM_MOVE_FENCES); if (unlikely(ret)) return ret; =20 @@ -757,7 +758,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_obje= ct *bo, return ret; } =20 - ret =3D ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu); + ret =3D ttm_bo_add_pipelined_eviction_fences(bo, man, ctx->no_wait_gpu); if (unlikely(ret)) { ttm_resource_free(bo, res); if (ret =3D=3D -EBUSY) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo= _util.c index acbbca9d5c92..2ff35d55e462 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -258,7 +258,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer= _object *bo, ret =3D dma_resv_trylock(&fbo->base.base._resv); WARN_ON(!ret); =20 - ret =3D dma_resv_reserve_fences(&fbo->base.base._resv, 1); + ret =3D dma_resv_reserve_fences(&fbo->base.base._resv, TTM_NUM_MOVE_FENCE= S); if (ret) { dma_resv_unlock(&fbo->base.base._resv); kfree(fbo); @@ -646,20 +646,44 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buf= fer_object *bo, { struct ttm_device *bdev =3D bo->bdev; struct ttm_resource_manager *from; + struct dma_fence *tmp; + int i; =20 from =3D ttm_manager_type(bdev, bo->resource->mem_type); =20 /** * BO doesn't have a TTM we need to bind/unbind. Just remember - * this eviction and free up the allocation + * this eviction and free up the allocation. + * The fence will be saved in the first free slot or in the slot + * already used to store a fence from the same context. Since + * drivers can't use more than TTM_NUM_MOVE_FENCES contexts for + * evictions we should always find a slot to use. */ - spin_lock(&from->move_lock); - if (!from->move || dma_fence_is_later(fence, from->move)) { - dma_fence_put(from->move); - from->move =3D dma_fence_get(fence); + spin_lock(&from->eviction_lock); + for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) { + tmp =3D from->eviction_fences[i]; + if (!tmp) + break; + if (fence->context !=3D tmp->context) + continue; + if (dma_fence_is_later(fence, tmp)) { + dma_fence_put(tmp); + break; + } + goto unlock; + } + if (i < TTM_NUM_MOVE_FENCES) { + from->eviction_fences[i] =3D dma_fence_get(fence); + } else { + WARN(1, "not enough fence slots for all fence contexts"); + spin_unlock(&from->eviction_lock); + dma_fence_wait(fence, false); + goto end; } - spin_unlock(&from->move_lock); =20 +unlock: + spin_unlock(&from->eviction_lock); +end: ttm_resource_free(bo, &bo->resource); } =20 diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_r= esource.c index e2c82ad07eb4..62c34cafa387 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -523,14 +523,15 @@ void ttm_resource_manager_init(struct ttm_resource_ma= nager *man, { unsigned i; =20 - spin_lock_init(&man->move_lock); man->bdev =3D bdev; man->size =3D size; man->usage =3D 0; =20 for (i =3D 0; i < TTM_MAX_BO_PRIORITY; ++i) INIT_LIST_HEAD(&man->lru[i]); - man->move =3D NULL; + spin_lock_init(&man->eviction_lock); + for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) + man->eviction_fences[i] =3D NULL; } EXPORT_SYMBOL(ttm_resource_manager_init); =20 @@ -551,7 +552,7 @@ int ttm_resource_manager_evict_all(struct ttm_device *b= dev, .no_wait_gpu =3D false, }; struct dma_fence *fence; - int ret; + int ret, i; =20 do { ret =3D ttm_bo_evict_first(bdev, man, &ctx); @@ -561,18 +562,24 @@ int ttm_resource_manager_evict_all(struct ttm_device = *bdev, if (ret && ret !=3D -ENOENT) return ret; =20 - spin_lock(&man->move_lock); - fence =3D dma_fence_get(man->move); - spin_unlock(&man->move_lock); + ret =3D 0; =20 - if (fence) { - ret =3D dma_fence_wait(fence, false); - dma_fence_put(fence); - if (ret) - return ret; + spin_lock(&man->eviction_lock); + for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) { + fence =3D man->eviction_fences[i]; + if (fence && !dma_fence_is_signaled(fence)) { + dma_fence_get(fence); + spin_unlock(&man->eviction_lock); + ret =3D dma_fence_wait(fence, false); + dma_fence_put(fence); + if (ret) + return ret; + spin_lock(&man->eviction_lock); + } } + spin_unlock(&man->eviction_lock); =20 - return 0; + return ret; } EXPORT_SYMBOL(ttm_resource_manager_evict_all); =20 diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index f49daa504c36..50e6added509 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -50,6 +50,15 @@ struct io_mapping; struct sg_table; struct scatterlist; =20 +/** + * define TTM_NUM_MOVE_FENCES - How many entities can be used for evictions + * + * Pipelined evictions can be spread on multiple entities. This + * is the max number of entities that can be used by the driver + * for that purpose. + */ +#define TTM_NUM_MOVE_FENCES 8 + /** * enum ttm_lru_item_type - enumerate ttm_lru_item subclasses */ @@ -180,8 +189,8 @@ struct ttm_resource_manager_func { * @size: Size of the managed region. * @bdev: ttm device this manager belongs to * @func: structure pointer implementing the range manager. See above - * @move_lock: lock for move fence - * @move: The fence of the last pipelined move operation. + * @eviction_lock: lock for eviction fences + * @eviction_fences: The fences of the last pipelined move operation. * @lru: The lru list for this memory type. * * This structure is used to identify and manage memory types for a device. @@ -195,12 +204,12 @@ struct ttm_resource_manager { struct ttm_device *bdev; uint64_t size; const struct ttm_resource_manager_func *func; - spinlock_t move_lock; =20 - /* - * Protected by @move_lock. + /* This is very similar to a dma_resv object, but locking rules make + * it difficult to use one in this context. */ - struct dma_fence *move; + spinlock_t eviction_lock; + struct dma_fence *eviction_fences[TTM_NUM_MOVE_FENCES]; =20 /* * Protected by the bdev->lru_lock. @@ -421,8 +430,12 @@ static inline bool ttm_resource_manager_used(struct tt= m_resource_manager *man) static inline void ttm_resource_manager_cleanup(struct ttm_resource_manager *man) { - dma_fence_put(man->move); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:08.4149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00d78700-f9e9-4495-b6e7-08de28e74479 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6754 Content-Type: text/plain; charset="utf-8" No functional change for now, as we always use entity 0. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 51 ++++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +- 3 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 2ee48f76483d..56663e82efef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1323,7 +1323,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) goto out; =20 r =3D amdgpu_fill_buffer(adev, - &adev->mman.clear_entity, abo, 0, &bo->base._resv, + &adev->mman.clear_entities[0], abo, 0, &bo->base._resv, &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 9024dde0c5a7..d7f041e43eca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2224,10 +2224,12 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); u32 used_windows, reserved_windows; + u32 num_clear_entities; uint64_t size; - int r; + int r, i, j; =20 - reserved_windows =3D 3; + num_clear_entities =3D adev->sdma.num_instances; + reserved_windows =3D 2 + num_clear_entities; =20 if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) @@ -2250,21 +2252,11 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) 1, NULL); if (r) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", + "Failed setting up TTM BO eviction entity (%d)\n", r); return 0; } =20 - r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { - dev_err(adev->dev, - "Failed setting up TTM BO clear entity (%d)\n", - r); - goto error_free_entity; - } - r =3D drm_sched_entity_init(&adev->mman.move_entity.base, DRM_SCHED_PRIORITY_NORMAL, &sched, 1, NULL); @@ -2272,26 +2264,48 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } =20 + adev->mman.num_clear_entities =3D num_clear_entities; + adev->mman.clear_entities =3D kcalloc(num_clear_entities, + sizeof(struct amdgpu_ttm_buffer_entity), + GFP_KERNEL); + if (!adev->mman.clear_entities) + goto error_free_entity; + + for (i =3D 0; i < num_clear_entities; i++) { + r =3D drm_sched_entity_init(&adev->mman.clear_entities[i].base, + DRM_SCHED_PRIORITY_NORMAL, &sched, + 1, NULL); + if (r) { + for (j =3D 0; j < i; j++) + drm_sched_entity_destroy( + &adev->mman.clear_entities[j].base); + kfree(adev->mman.clear_entities); + goto error_free_entity; + } + } + /* Statically assign GART windows to each entity. */ used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.default_entit= y, 0, false, false); used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, used_windows, true, true); - used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, - used_windows, false, true); + for (i =3D 0; i < num_clear_entities; i++) + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entiti= es[i], + used_windows, false, true); WARN_ON(used_windows !=3D reserved_windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); drm_sched_entity_destroy(&adev->mman.move_entity.base); + for (i =3D 0; i < num_clear_entities; i++) + drm_sched_entity_destroy(&adev->mman.clear_entities[i].base); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ ttm_resource_manager_cleanup(man); + kfree(adev->mman.clear_entities); } =20 /* this just adjusts TTM size idea, which sets lpfn to the correct value = */ @@ -2456,8 +2470,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_device *ade= v, =20 if (!fence) return -EINVAL; - - entity =3D &adev->mman.clear_entity; + entity =3D &adev->mman.clear_entities[0]; *fence =3D dma_fence_get_stub(); =20 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:16.1558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7f56d9b-0c22-4be5-c485-08de28e74916 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFC41ACEE7B Content-Type: text/plain; charset="utf-8" No functional change for now, as we always use entity 0. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +- 3 files changed, 31 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index d7f041e43eca..438e8a3b7a06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -439,7 +439,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, dst.offset =3D 0; =20 r =3D amdgpu_ttm_copy_mem_to_mem(adev, - &adev->mman.move_entity, + &adev->mman.move_entities[0], &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), @@ -452,7 +452,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence =3D NULL; =20 - r =3D amdgpu_fill_buffer(adev, &adev->mman.move_entity, + r =3D amdgpu_fill_buffer(adev, &adev->mman.move_entities[0], abo, 0, NULL, &wipe_fence, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { @@ -2224,12 +2224,13 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); u32 used_windows, reserved_windows; - u32 num_clear_entities; + u32 num_clear_entities, num_move_entities; uint64_t size; int r, i, j; =20 num_clear_entities =3D adev->sdma.num_instances; - reserved_windows =3D 2 + num_clear_entities; + num_move_entities =3D MIN(adev->sdma.num_instances, TTM_NUM_MOVE_FENCES); + reserved_windows =3D 2 * num_move_entities + num_clear_entities; =20 if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) @@ -2251,20 +2252,25 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) DRM_SCHED_PRIORITY_KERNEL, &sched, 1, NULL); if (r) { - dev_err(adev->dev, - "Failed setting up TTM BO eviction entity (%d)\n", + dev_err(adev->dev, "Failed setting up entity (%d)\n", r); return 0; } =20 - r =3D drm_sched_entity_init(&adev->mman.move_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { - dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", - r); - goto error_free_entity; + adev->mman.num_move_entities =3D num_move_entities; + for (i =3D 0; i < num_move_entities; i++) { + r =3D drm_sched_entity_init(&adev->mman.move_entities[i].base, + DRM_SCHED_PRIORITY_NORMAL, &sched, + 1, NULL); + if (r) { + dev_err(adev->dev, + "Failed setting up TTM BO move entities (%d)\n", + r); + for (j =3D 0; j < i; j++) + drm_sched_entity_destroy( + &adev->mman.move_entities[j].base); + goto error_free_entity; + } } =20 adev->mman.num_clear_entities =3D num_clear_entities; @@ -2279,6 +2285,9 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) DRM_SCHED_PRIORITY_NORMAL, &sched, 1, NULL); if (r) { + for (j =3D 0; j < num_move_entities; j++) + drm_sched_entity_destroy( + &adev->mman.move_entities[j].base); for (j =3D 0; j < i; j++) drm_sched_entity_destroy( &adev->mman.clear_entities[j].base); @@ -2290,15 +2299,17 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) /* Statically assign GART windows to each entity. */ used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.default_entit= y, 0, false, false); - used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, - used_windows, true, true); + for (i =3D 0; i < num_move_entities; i++) + used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entitie= s[i], + used_windows, true, true); for (i =3D 0; i < num_clear_entities; i++) used_windows =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entiti= es[i], used_windows, false, true); WARN_ON(used_windows !=3D reserved_windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); - drm_sched_entity_destroy(&adev->mman.move_entity.base); + for (i =3D 0; i < num_move_entities; i++) + drm_sched_entity_destroy(&adev->mman.move_entities[i].base); for (i =3D 0; i < num_clear_entities; i++) drm_sched_entity_destroy(&adev->mman.clear_entities[i].base); /* Drop all the old fences since re-creating the scheduler entities diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 250ef54a5550..eabc5a1549e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -72,9 +72,10 @@ struct amdgpu_mman { struct mutex gtt_window_lock; =20 struct amdgpu_ttm_buffer_entity default_entity; /* has no gart windows */ - struct amdgpu_ttm_buffer_entity move_entity; struct amdgpu_ttm_buffer_entity *clear_entities; u32 num_clear_entities; + struct amdgpu_ttm_buffer_entity move_entities[TTM_NUM_MOVE_FENCES]; + u32 num_move_entities; =20 struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 0cc1d2b35026..5dd65f05a1e0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -135,7 +135,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev= , dma_addr_t *sys, u64 size; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:21.9707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c306658-b791-4759-1ba9-08de28e74c8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7191 Content-Type: text/plain; charset="utf-8" This makes clear of different BOs run in parallel. Partial jobs to clear a single BO still execute sequentially. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 ++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 56663e82efef..7d8d70135cc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1322,8 +1322,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(adev, - &adev->mman.clear_entities[0], abo, 0, &bo->base._resv, + r =3D amdgpu_fill_buffer(adev, amdgpu_ttm_next_clear_entity(adev), + abo, 0, &bo->base._resv, &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 438e8a3b7a06..8d70bea66dd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2277,6 +2277,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) adev->mman.clear_entities =3D kcalloc(num_clear_entities, sizeof(struct amdgpu_ttm_buffer_entity), GFP_KERNEL); + atomic_set(&adev->mman.next_clear_entity, 0); if (!adev->mman.clear_entities) goto error_free_entity; =20 @@ -2576,6 +2577,17 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, return r; } =20 +struct amdgpu_ttm_buffer_entity * +amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev) +{ + struct amdgpu_mman *mman =3D &adev->mman; + int i; + + i =3D atomic_inc_return(&mman->next_clear_entity) % + mman->num_clear_entities; + return &mman->clear_entities[i]; +} + /** * amdgpu_ttm_evict_resources - evict memory buffers * @adev: amdgpu device object diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index eabc5a1549e9..887531126d9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -73,6 +73,7 @@ struct amdgpu_mman { =20 struct amdgpu_ttm_buffer_entity default_entity; /* has no gart windows */ struct amdgpu_ttm_buffer_entity *clear_entities; + atomic_t next_clear_entity; u32 num_clear_entities; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:32.1974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85b4122a-3313-4222-b75e-08de28e752a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7011 Use TTM_NUM_MOVE_FENCES as an upperbound of how many fences ttm might need to deal with moves/evictions. Acked-by: Felix Kuehling Reviewed-by: Christian K=C3=B6nig --- v2: removed drm_err calls --- Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Felix Kuehling Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 3 +-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 ++---- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 6 ++---- 7 files changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_cs.c index d591dce0f3b3..5215238f8fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -916,9 +916,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser= *p, goto out_free_user_pages; =20 amdgpu_bo_list_for_each_entry(e, p->bo_list) { - /* One fence for TTM and one for each CS job */ r =3D drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base, - 1 + p->gang_size); + TTM_NUM_MOVE_FENCES + p->gang_size); drm_exec_retry_on_contention(&p->exec); if (unlikely(r)) goto out_free_user_pages; @@ -928,7 +927,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser= *p, =20 if (p->uf_bo) { r =3D drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base, - 1 + p->gang_size); + TTM_NUM_MOVE_FENCES + p->gang_size); drm_exec_retry_on_contention(&p->exec); if (unlikely(r)) goto out_free_user_pages; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gem.c index f2505ae5fd65..41fd84a19d66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -354,7 +354,7 @@ static void amdgpu_gem_object_close(struct drm_gem_obje= ct *obj, =20 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { - r =3D drm_exec_prepare_obj(&exec, &bo->tbo.base, 1); + r =3D drm_exec_prepare_obj(&exec, &bo->tbo.base, TTM_NUM_MOVE_FENCES); drm_exec_retry_on_contention(&exec); if (unlikely(r)) goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_vkms.c index 79bad9cbe2ab..b92561eea3da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -326,11 +326,9 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *pl= ane, return r; } =20 - r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, 1); - if (r) { - dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); + r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_NUM_MOVE_FENCES); + if (r) goto error_unlock; - } =20 if (plane->type !=3D DRM_PLANE_TYPE_CURSOR) domain =3D amdgpu_display_supported_domains(adev, rbo->flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_vm.c index 5061d5b0f875..62f37a9ca966 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2656,7 +2656,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct= amdgpu_vm *vm, } =20 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); - r =3D dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + r =3D dma_resv_reserve_fences(root_bo->tbo.base.resv, + TTM_NUM_MOVE_FENCES); if (r) goto error_free_root; =20 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amd= kfd/kfd_svm.c index 97c2270f278f..0f8d85ee97fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -627,9 +627,8 @@ svm_range_vram_node_new(struct kfd_node *node, struct s= vm_range *prange, } } =20 - r =3D dma_resv_reserve_fences(bo->tbo.base.resv, 1); + r =3D dma_resv_reserve_fences(bo->tbo.base.resv, TTM_NUM_MOVE_FENCES); if (r) { - pr_debug("failed %d to reserve bo\n", r); amdgpu_bo_unreserve(bo); goto reserve_bo_failed; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 56cb866ac6f8..ceb55dd183ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -952,11 +952,9 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct dr= m_plane *plane, return r; } =20 - r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, 1); - if (r) { - drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); + r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_NUM_MOVE_FENCES); + if (r) goto error_unlock; - } =20 if (plane->type !=3D DRM_PLANE_TYPE_CURSOR) domain =3D amdgpu_display_supported_domains(adev, rbo->flags); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers= /gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index d9527c05fc87..110f0173eee6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -106,11 +106,9 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeba= ck_connector *wb_connector return r; } =20 - r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, 1); - if (r) { - drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); + r =3D dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_NUM_MOVE_FENCES); + if (r) goto error_unlock; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:18:36.5000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f73801ce-74d3-4c9a-463e-08de28e75537 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9232 Thanks to "drm/ttm: rework pipelined eviction fence handling", ttm can deal correctly with moves and evictions being executed from different contexts. Create several entities and use them in a round-robin fashion. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 8d70bea66dd0..575a4d4a1747 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -427,6 +427,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, { struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo =3D ttm_to_amdgpu_bo(bo); + struct amdgpu_ttm_buffer_entity *entity; struct amdgpu_copy_mem src, dst; struct dma_fence *fence =3D NULL; int r; @@ -438,8 +439,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *= bo, src.offset =3D 0; dst.offset =3D 0; =20 + int e =3D atomic_inc_return(&adev->mman.next_move_entity) % + adev->mman.num_move_entities; + entity =3D &adev->mman.move_entities[e]; + r =3D amdgpu_ttm_copy_mem_to_mem(adev, - &adev->mman.move_entities[0], + entity, &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), @@ -452,7 +457,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence =3D NULL; =20 - r =3D amdgpu_fill_buffer(adev, &adev->mman.move_entities[0], + r =3D amdgpu_fill_buffer(adev, entity, abo, 0, NULL, &wipe_fence, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { @@ -2258,6 +2263,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) } =20 adev->mman.num_move_entities =3D num_move_entities; + atomic_set(&adev->mman.next_move_entity, 0); for (i =3D 0; i < num_move_entities; i++) { r =3D drm_sched_entity_init(&adev->mman.move_entities[i].base, DRM_SCHED_PRIORITY_NORMAL, &sched, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 887531126d9d..0785a2c594f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -76,6 +76,7 @@ struct amdgpu_mman { atomic_t next_clear_entity; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:19:09.2328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd726a4b-f8f8-4867-a9a4-08de28e768b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022570.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4166 Content-Type: text/plain; charset="utf-8" This will allow the use of all of them for clear/fill buffer operations. Since drm_sched_entity_init requires a scheduler array, we store schedulers rather than rings. For the few places that need access to a ring, we can get it from the sched using container_of. Since the code is the same for all sdma versions, add a new helper amdgpu_sdma_set_buffer_funcs_scheds to set buffer_funcs_scheds based on the number of sdma instances. Note: the new sched array is identical to the amdgpu_vm_manager one. These 2 could be merged. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 31 +++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 ++- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 6 +---- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 +-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 ++- 16 files changed, 47 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index a50e3c0a4b18..d07075fe2d8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1614,6 +1614,8 @@ ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu= _ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, const struct amdgpu_vm_pte_funcs *vm_pte_funcs); +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs); =20 /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index 7167db54d722..9d3931d31d96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4527,7 +4527,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->num_rings =3D 0; RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); adev->mman.buffer_funcs =3D NULL; - adev->mman.buffer_funcs_ring =3D NULL; + adev->mman.num_buffer_funcs_scheds =3D 0; adev->vm_manager.vm_pte_funcs =3D NULL; adev->vm_manager.vm_pte_num_scheds =3D 0; adev->gmc.gmc_funcs =3D NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index 0d2784fe0be3..ff9a066870f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -651,12 +651,14 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_devi= ce *adev) void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { - struct amdgpu_ring *ring =3D adev->mman.buffer_funcs_ring; + struct amdgpu_ring *ring; struct amdgpu_vmhub *hub =3D &adev->vmhub[vmhub]; struct dma_fence *fence; struct amdgpu_job *job; int r; =20 + ring =3D to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); + if (!hub->sdma_invalidation_workaround || vmid || !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || !ring->sched.ready) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 575a4d4a1747..eec0cab8060c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -168,7 +168,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struc= t amdgpu_ttm_buffer_entit { struct amdgpu_ring *ring; =20 - ring =3D adev->mman.buffer_funcs_ring; + ring =3D to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); =20 @@ -2241,18 +2241,16 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) return reserved_windows; =20 - if ((!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sche= d.ready) && + if ((!adev->mman.num_buffer_funcs_scheds || !adev->mman.buffer_funcs_sche= ds[0]->ready) && enable) { dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); return 0; } =20 if (enable) { - struct amdgpu_ring *ring; struct drm_gpu_scheduler *sched; =20 - ring =3D adev->mman.buffer_funcs_ring; - sched =3D &ring->sched; + sched =3D adev->mman.buffer_funcs_scheds[0]; r =3D drm_sched_entity_init(&adev->mman.default_entity.base, DRM_SCHED_PRIORITY_KERNEL, &sched, 1, NULL); @@ -2387,7 +2385,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, unsigned int i; int r; =20 - ring =3D adev->mman.buffer_funcs_ring; + ring =3D to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); =20 if (!ring->sched.ready) { dev_err(adev->dev, @@ -2624,6 +2622,27 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device = *adev, int mem_type) return ttm_resource_manager_evict_all(&adev->mman.bdev, man); } =20 +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs) +{ + struct amdgpu_vmhub *hub =3D &adev->vmhub[AMDGPU_GFXHUB(0)]; + struct drm_gpu_scheduler *sched; + int i; + + adev->mman.buffer_funcs =3D buffer_funcs; + + for (i =3D 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched =3D &adev->sdma.instance[i].page.sched; + else + sched =3D &adev->sdma.instance[i].ring.sched; + adev->mman.buffer_funcs_scheds[i] =3D sched; + } + + adev->mman.num_buffer_funcs_scheds =3D hub->sdma_invalidation_workaround ? + 1 : adev->sdma.num_instances; +} + #if defined(CONFIG_DEBUG_FS) =20 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 0785a2c594f7..653a4d17543e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -66,7 +66,8 @@ struct amdgpu_mman { =20 /* buffer handling */ const struct amdgpu_buffer_funcs *buffer_funcs; - struct amdgpu_ring *buffer_funcs_ring; + struct drm_gpu_scheduler *buffer_funcs_scheds[AMDGPU_MAX_RINGS]; + u32 num_buffer_funcs_scheds; bool buffer_funcs_enabled; =20 struct mutex gtt_window_lock; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/am= dgpu/cik_sdma.c index 22780c09177d..26276dcfd458 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1340,8 +1340,7 @@ static const struct amdgpu_buffer_funcs cik_sdma_buff= er_funcs =3D { =20 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &cik_sdma_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &cik_sdma_buffer_funcs); } =20 const struct amdgpu_ip_block_version cik_sdma_ip_block =3D diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v2_4.c index 0090ace49024..c6a059ca59e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -1235,8 +1235,7 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buf= fer_funcs =3D { =20 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v2_4_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v2_4_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =3D { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v3_0.c index 2526d393162a..cb516a25210d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1677,8 +1677,7 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buf= fer_funcs =3D { =20 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v3_0_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =3D diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v4_0.c index a35d9951e22a..f234ee54f39e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2615,11 +2615,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_bu= ffer_funcs =3D { =20 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v4_0_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_0_buffer_funcs); } =20 static void sdma_v4_0_get_ras_error_count(uint32_t value, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd= /amdgpu/sdma_v4_4_2.c index 7f77367848d4..cd7627b03066 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -2316,11 +2316,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_2_= buffer_funcs =3D { =20 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v4_4_2_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); } =20 /** diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v5_0.c index 7ce13c5d4e61..5b495fda4f71 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -2073,10 +2073,8 @@ static const struct amdgpu_buffer_funcs sdma_v5_0_bu= ffer_funcs =3D { =20 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs =3D=3D NULL) { - adev->mman.buffer_funcs =3D &sdma_v5_0_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; - } + if (adev->mman.buffer_funcs =3D=3D NULL) + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_0_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v5_0_ip_block =3D { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v5_2.c index 98beff18cf28..be2d9e57c459 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -2084,10 +2084,8 @@ static const struct amdgpu_buffer_funcs sdma_v5_2_bu= ffer_funcs =3D { =20 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs =3D=3D NULL) { - adev->mman.buffer_funcs =3D &sdma_v5_2_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; - } + if (adev->mman.buffer_funcs =3D=3D NULL) + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_2_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v5_2_ip_block =3D { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v6_0.c index c32331b72ba0..ed8937fe76ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1891,8 +1891,7 @@ static const struct amdgpu_buffer_funcs sdma_v6_0_buf= fer_funcs =3D { =20 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v6_0_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v6_0_ip_block =3D { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v7_0.c index 9318d23eb71e..f4c91153542c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1833,8 +1833,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buf= fer_funcs =3D { =20 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &sdma_v7_0_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_0_buffer_funcs); } =20 const struct amdgpu_ip_block_version sdma_v7_0_ip_block =3D { diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdg= pu/si_dma.c index b85df997ed49..ac6272fcffe9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -833,8 +833,7 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_f= uncs =3D { =20 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs =3D &si_dma_buffer_funcs; - adev->mman.buffer_funcs_ring =3D &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &si_dma_buffer_funcs); } =20 const struct amdgpu_ip_block_version si_dma_ip_block =3D diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd= /amdkfd/kfd_migrate.c index 5dd65f05a1e0..a149265e3611 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -128,13 +128,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *ad= ev, dma_addr_t *sys, struct dma_fence **mfence) { const u64 GTT_MAX_PAGES =3D AMDGPU_GTT_MAX_TRANSFER_SIZE; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:19:14.1679 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92dc8e3b-345c-403a-0203-08de28e76bab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9639 With this change we now have as many clear and move entities as we have sdma engines (limited to TTM_NUM_MOVE_FENCES). To enable load-balancing this patch gives access to all sdma schedulers to all entities. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index eec0cab8060c..39cfe2dbdf03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2233,8 +2233,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) uint64_t size; int r, i, j; =20 - num_clear_entities =3D adev->sdma.num_instances; - num_move_entities =3D MIN(adev->sdma.num_instances, TTM_NUM_MOVE_FENCES); + num_clear_entities =3D MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MO= VE_FENCES); + num_move_entities =3D MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOV= E_FENCES); reserved_windows =3D 2 * num_move_entities + num_clear_entities; =20 if (!adev->mman.initialized || amdgpu_in_reset(adev) || @@ -2248,11 +2248,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu= _device *adev, bool enable) } =20 if (enable) { - struct drm_gpu_scheduler *sched; - - sched =3D adev->mman.buffer_funcs_scheds[0]; r =3D drm_sched_entity_init(&adev->mman.default_entity.base, - DRM_SCHED_PRIORITY_KERNEL, &sched, + DRM_SCHED_PRIORITY_KERNEL, adev->mman.buffer_funcs_scheds, 1, NULL); if (r) { dev_err(adev->dev, "Failed setting up entity (%d)\n", @@ -2264,8 +2261,9 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) atomic_set(&adev->mman.next_move_entity, 0); for (i =3D 0; i < num_move_entities; i++) { r =3D drm_sched_entity_init(&adev->mman.move_entities[i].base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); + DRM_SCHED_PRIORITY_NORMAL, + adev->mman.buffer_funcs_scheds, + adev->mman.num_buffer_funcs_scheds, NULL); if (r) { dev_err(adev->dev, "Failed setting up TTM BO move entities (%d)\n", @@ -2287,8 +2285,9 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_= device *adev, bool enable) =20 for (i =3D 0; i < num_clear_entities; i++) { r =3D drm_sched_entity_init(&adev->mman.clear_entities[i].base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:19:20.8510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45b4bb3a-c1a6-4547-8154-08de28e76fa5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 Content-Type: text/plain; charset="utf-8" It's doing the same thing as amdgpu_fill_buffer(src_data=3D0), so drop it. The only caveat is that amdgpu_res_cleared() return value is only valid right after allocation. --- v2: introduce new "bool consider_clear_status" arg --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 90 +++++----------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +- 3 files changed, 33 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index 7d8d70135cc2..dccc31d0128e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -725,13 +725,17 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type =3D=3D TTM_PL_VRAM) { struct dma_fence *fence; =20 - r =3D amdgpu_ttm_clear_buffer(adev, bo, bo->tbo.base.resv, &fence); + r =3D amdgpu_fill_buffer(adev, amdgpu_ttm_next_clear_entity(adev), + bo, 0, NULL, &fence, + true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (unlikely(r)) goto fail_unreserve; =20 - dma_resv_add_fence(bo->tbo.base.resv, fence, - DMA_RESV_USAGE_KERNEL); - dma_fence_put(fence); + if (fence) { + dma_resv_add_fence(bo->tbo.base.resv, fence, + DMA_RESV_USAGE_KERNEL); + dma_fence_put(fence); + } } if (!bp->resv) amdgpu_bo_unreserve(bo); @@ -1323,8 +1327,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) goto out; =20 r =3D amdgpu_fill_buffer(adev, amdgpu_ttm_next_clear_entity(adev), - abo, 0, &bo->base._resv, - &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + abo, 0, &bo->base._resv, &fence, + false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 39cfe2dbdf03..c65c411ce26e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -459,7 +459,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, =20 r =3D amdgpu_fill_buffer(adev, entity, abo, 0, NULL, &wipe_fence, - AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -2459,79 +2459,28 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device= *adev, } =20 /** - * amdgpu_ttm_clear_buffer - clear memory buffers + * amdgpu_fill_buffer - fill a buffer with a given value * @adev: amdgpu device object - * @bo: amdgpu buffer object - * @resv: reservation object - * @fence: dma_fence associated with the operation + * @entity: optional entity to use. If NULL, the clearing entities will be + * used to load-balance the partial clears + * @bo: the bo to fill + * @src_data: the value to set + * @resv: fences contained in this reservation will be used as dependencie= s. + * @out_fence: the fence from the last clear will be stored here. It might= be + * NULL if no job was run. + * @dependency: optional input dependency fence. + * @consider_clear_status: true if region reported as cleared by amdgpu_re= s_cleared() + * are skipped. + * @k_job_id: trace id * - * Clear the memory buffer resource. - * - * Returns: - * 0 for success or a negative error code on failure. */ -int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, - struct amdgpu_bo *bo, - struct dma_resv *resv, - struct dma_fence **fence) -{ - struct amdgpu_ttm_buffer_entity *entity; - struct amdgpu_res_cursor cursor; - u64 addr; - int r =3D 0; - - if (!adev->mman.buffer_funcs_enabled) - return -EINVAL; - - if (!fence) - return -EINVAL; - entity =3D &adev->mman.clear_entities[0]; - *fence =3D dma_fence_get_stub(); - - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); - - mutex_lock(&entity->lock); - while (cursor.remaining) { - struct dma_fence *next =3D NULL; - u64 size; - - if (amdgpu_res_cleared(&cursor)) { - amdgpu_res_next(&cursor, cursor.size); - continue; - } - - /* Never clear more than 256MiB at once to avoid timeouts */ - size =3D min(cursor.size, 256ULL << 20); - - r =3D amdgpu_ttm_map_buffer(adev, entity, - &bo->tbo, bo->tbo.resource, &cursor, - 1, false, false, &size, &addr); - if (r) - goto err; - - r =3D amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, - &next, true, - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); - if (r) - goto err; - - dma_fence_put(*fence); - *fence =3D next; - - amdgpu_res_next(&cursor, size); - } -err: - mutex_unlock(&entity->lock); - - return r; -} - int amdgpu_fill_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, struct amdgpu_bo *bo, uint32_t src_data, struct dma_resv *resv, - struct dma_fence **f, + struct dma_fence **out_fence, + bool consider_clear_status, u64 k_job_id) { struct dma_fence *fence =3D NULL; @@ -2551,6 +2500,11 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, struct dma_fence *next; uint64_t cur_size, to; =20 + if (consider_clear_status && amdgpu_res_cleared(&dst)) { + amdgpu_res_next(&dst, dst.size); + continue; + } + /* Never fill more than 256MiB at once to avoid timeouts */ cur_size =3D min(dst.size, 256ULL << 20); =20 @@ -2574,9 +2528,7 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, } error: mutex_unlock(&entity->lock); - if (f) - *f =3D dma_fence_get(fence); - dma_fence_put(fence); + *out_fence =3D fence; return r; } =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 653a4d17543e..f3bdbcec9afc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -181,16 +181,13 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, - struct amdgpu_bo *bo, - struct dma_resv *resv, - struct dma_fence **fence); int amdgpu_fill_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, struct amdgpu_bo *bo, uint32_t src_data, struct dma_resv *resv, - struct dma_fence **f, + struct dma_fence **out_fence, + bool consider_clear_status, u64 k_job_id); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:19:24.4888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3183a14-5d98-471f-d20e-08de28e771d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7220 This is the only use case for this function. Reviewed-by: Christian K=C3=B6nig --- v2: amdgpu_ttm_clear_buffer instead of amdgpu_clear_buffer --- Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 27 ++++++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 15 ++++++------ 3 files changed, 25 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index dccc31d0128e..ac1727c3634a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -725,9 +725,9 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type =3D=3D TTM_PL_VRAM) { struct dma_fence *fence; =20 - r =3D amdgpu_fill_buffer(adev, amdgpu_ttm_next_clear_entity(adev), - bo, 0, NULL, &fence, - true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); + r =3D amdgpu_ttm_clear_buffer(adev, amdgpu_ttm_next_clear_entity(adev), + bo, NULL, &fence, + true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (unlikely(r)) goto fail_unreserve; =20 @@ -1326,9 +1326,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(adev, amdgpu_ttm_next_clear_entity(adev), - abo, 0, &bo->base._resv, &fence, - false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + r =3D amdgpu_ttm_clear_buffer(adev, amdgpu_ttm_next_clear_entity(adev), + abo, &bo->base._resv, &fence, + false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index c65c411ce26e..1cc72fd94a4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -457,9 +457,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *b= o, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence =3D NULL; =20 - r =3D amdgpu_fill_buffer(adev, entity, - abo, 0, NULL, &wipe_fence, - false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + r =3D amdgpu_ttm_clear_buffer(adev, entity, + abo, NULL, &wipe_fence, + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -2459,29 +2459,26 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device= *adev, } =20 /** - * amdgpu_fill_buffer - fill a buffer with a given value + * amdgpu_ttm_clear_buffer - fill a buffer with 0 * @adev: amdgpu device object * @entity: optional entity to use. If NULL, the clearing entities will be * used to load-balance the partial clears * @bo: the bo to fill - * @src_data: the value to set * @resv: fences contained in this reservation will be used as dependencie= s. * @out_fence: the fence from the last clear will be stored here. It might= be * NULL if no job was run. - * @dependency: optional input dependency fence. * @consider_clear_status: true if region reported as cleared by amdgpu_re= s_cleared() * are skipped. * @k_job_id: trace id * */ -int amdgpu_fill_buffer(struct amdgpu_device *adev, - struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **out_fence, - bool consider_clear_status, - u64 k_job_id) +int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + struct dma_resv *resv, + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id) { struct dma_fence *fence =3D NULL; struct amdgpu_res_cursor dst; @@ -2516,7 +2513,7 @@ int amdgpu_fill_buffer(struct amdgpu_device *adev, goto error; =20 r =3D amdgpu_ttm_fill_mem(adev, entity, - src_data, to, cur_size, resv, + 0, to, cur_size, resv, &next, true, k_job_id); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index f3bdbcec9afc..fba205c1b5d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -181,14 +181,13 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_fill_buffer(struct amdgpu_device *adev, - struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **out_fence, - bool consider_clear_status, - u64 k_job_id); +int amdgpu_ttm_clear_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + struct dma_resv *resv, + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id); struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgp= u_device *adev); =20 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); --=20 2.43.0