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Fri, 21 Nov 2025 04:50:49 -0500 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v2 2/2] iio: frequency: adf4377: add clk provider support Date: Fri, 21 Nov 2025 09:50:27 +0000 Message-ID: <20251121095027.18304-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121095027.18304-1-antoniu.miclaus@analog.com> References: <20251121095027.18304-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDA3NCBTYWx0ZWRfX6DetIqeEjnkX zsWjZrqPXHUg1YOJJmPOv+d+Cb3lXkFYRDPv8jhollPLYVfGRVhtbj/V2o1vM6sv0zFpWIDbgcE rN4ePyhynAFPWZ3VKP40btukpMwdh7UC6BhMvqBDavdjCq5MyZTDKgtkcwIIkwMG284LmI7bE+x Sx2BXM3KrdFphAwtXiO0U19biw3gJdX2zC5SUm3RKCoA/AzSHHVLj9wBYfgdpmIZt1A/yFu4ZnN PjXXllzq0Oc0CHtAxgO3GH9LvG/DhTd9ho1gM23h/aHIyymBLhXbnUADnWXY0MsSJKY6v4xOv2q EkZo/aZ7UPJT1eJ6rupgGt8TLFcsQMXmK7lHc6vqBav0iv8plqF8bQEchPB49Bt9cy2dE1uMs3h xbQQDC3X/RdruI3Jg2IfNoYRvmxflw== X-Authority-Analysis: v=2.4 cv=DvhbOW/+ c=1 sm=1 tr=0 ts=69203600 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=I9ctbcXp8itbP4OmBmcA:9 X-Proofpoint-GUID: ClohMt_IVNqiQSC2VC6z8RvYHLVSYb8D X-Proofpoint-ORIG-GUID: ClohMt_IVNqiQSC2VC6z8RvYHLVSYb8D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210074 Content-Type: text/plain; charset="utf-8" Add clk provider feature for the adf4377. Even though the driver was sent as an IIO driver in most cases the device is actually seen as a clock provider. This patch aims to cover actual usecases requested by users in order to completely control the output frequencies from userspace. Signed-off-by: Antoniu Miclaus Changes in v2: - Replace deprecated .is_enabled clock operation with .is_prepared - Use modern devm_clk_hw_register() instead of devm_clk_register() - Switch to clk_parent_data with fw_name instead of parent_names array - Use devm_of_clk_add_hw_provider() with of_clk_hw_simple_get for modern DT= integration - Fix indentation alignment in adf4377_clk_recalc_rate function parameter - Remove manual clock provider cleanup by using devm_* variants --- drivers/iio/frequency/adf4377.c | 131 +++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 2 deletions(-) diff --git a/drivers/iio/frequency/adf4377.c b/drivers/iio/frequency/adf437= 7.c index 08833b7035e4..c9c73ed3de2c 100644 --- a/drivers/iio/frequency/adf4377.c +++ b/drivers/iio/frequency/adf4377.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -435,9 +436,14 @@ struct adf4377_state { struct gpio_desc *gpio_ce; struct gpio_desc *gpio_enclk1; struct gpio_desc *gpio_enclk2; + struct clk *clk; + struct clk *clkout; + struct clk_hw hw; u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; =20 +#define to_adf4377_state(h) container_of(h, struct adf4377_state, hw) + static const char * const adf4377_muxout_modes[] =3D { [ADF4377_MUXOUT_HIGH_Z] =3D "high_z", [ADF4377_MUXOUT_LKDET] =3D "lock_detect", @@ -929,6 +935,120 @@ static int adf4377_freq_change(struct notifier_block = *nb, unsigned long action, return NOTIFY_OK; } =20 +static void adf4377_clk_del_provider(void *data) +{ + struct adf4377_state *st =3D data; + + of_clk_del_provider(st->spi->dev.of_node); +} + +static unsigned long adf4377_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + u64 freq; + int ret; + + ret =3D adf4377_get_freq(st, &freq); + if (ret) + return 0; + + return freq; +} + +static int adf4377_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + return adf4377_set_freq(st, rate); +} + +static int adf4377_clk_prepare(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + return regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | + ADF4377_001A_PD_CLKOUT2_MSK, + FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | + FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); +} + +static void adf4377_clk_unprepare(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + + regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | + ADF4377_001A_PD_CLKOUT2_MSK, + FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 1) | + FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 1)); +} + +static int adf4377_clk_is_enabled(struct clk_hw *hw) +{ + struct adf4377_state *st =3D to_adf4377_state(hw); + unsigned int readval; + int ret; + + ret =3D regmap_read(st->regmap, 0x1a, &readval); + if (ret) + return ret; + + return !(readval & (ADF4377_001A_PD_CLKOUT1_MSK | ADF4377_001A_PD_CLKOUT2= _MSK)); +} + +static const struct clk_ops adf4377_clk_ops =3D { + .recalc_rate =3D adf4377_clk_recalc_rate, + .set_rate =3D adf4377_clk_set_rate, + .prepare =3D adf4377_clk_prepare, + .unprepare =3D adf4377_clk_unprepare, + .is_enabled =3D adf4377_clk_is_enabled, +}; + +static int adf4377_clk_register(struct adf4377_state *st) +{ + struct spi_device *spi =3D st->spi; + struct clk_init_data init; + struct clk *clk; + const char *parent_name; + int ret; + + if (!device_property_present(&spi->dev, "#clock-cells")) + return 0; + + if (device_property_read_string(&spi->dev, "clock-output-names", &init.na= me)) { + init.name =3D devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk", + fwnode_get_name(dev_fwnode(&spi->dev))); + if (!init.name) + return -ENOMEM; + } + + parent_name =3D of_clk_get_parent_name(spi->dev.of_node, 0); + if (!parent_name) + return -EINVAL; + + init.ops =3D &adf4377_clk_ops; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + init.flags =3D CLK_SET_RATE_PARENT; + + st->hw.init =3D &init; + clk =3D devm_clk_register(&spi->dev, &st->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + st->clk =3D clk; + + ret =3D of_clk_add_provider(spi->dev.of_node, of_clk_src_simple_get, clk); + if (ret) + return ret; + + st->clkout =3D clk; + + return devm_add_action_or_reset(&spi->dev, adf4377_clk_del_provider, st); +} + static const struct adf4377_chip_info adf4377_chip_info =3D { .name =3D "adf4377", .has_gpio_enclk2 =3D true, @@ -958,8 +1078,6 @@ static int adf4377_probe(struct spi_device *spi) =20 indio_dev->info =3D &adf4377_info; indio_dev->name =3D "adf4377"; - indio_dev->channels =3D adf4377_channels; - indio_dev->num_channels =3D ARRAY_SIZE(adf4377_channels); =20 st->regmap =3D regmap; st->spi =3D spi; @@ -979,6 +1097,15 @@ static int adf4377_probe(struct spi_device *spi) if (ret) return ret; =20 + ret =3D adf4377_clk_register(st); + if (ret) + return ret; + + if (!st->clkout) { + indio_dev->channels =3D adf4377_channels; + indio_dev->num_channels =3D ARRAY_SIZE(adf4377_channels); + } + return devm_iio_device_register(&spi->dev, indio_dev); } =20 --=20 2.43.0