From nobody Tue Dec 2 01:30:20 2025 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2CC433F8A4; Fri, 21 Nov 2025 09:23:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763717029; cv=none; b=AsgRu0J4vuiqZ14LXvnD/59yi9XHsnk9tz0yY87dGO2pBWXDvVdYUhQ/bhR1QBURUceHfKYy+PKXy1D0kAaaOy7GaYNsOjVWtCgoSyYtvlWxerWIVWm/c2wS8evSB9Vl62hOfibDBlQXuHYp88euDSIzHFOG2KEtJ1BOWq66IcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763717029; c=relaxed/simple; bh=Bt2Hwt9sCR5WG2aRUAwBi8UUiftFYTbEFxblcAUpPr0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r9qRo/hzmYA/eYhe3g34odi7cMXWsjre6oW0UlLWoo5RY+x78L0MzK11rtzNkHP6uC8cjIZjMq2+PcVtqL1FfnAR9vypwhTx9H6z9YXMQu5Bpa+ezKgTUfVPZiG1wur8B+PE+JH7Dfr0pmriahp0wtMEjHt7q6ei/Px5FpqUbqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=5adxCFnY; arc=none smtp.client-ip=113.46.200.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="5adxCFnY" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=HP4T9Ux78gNIlOGmGsvDsFgk5odPVemp6LKwfalw7UY=; b=5adxCFnYtZP2WE1LbfvuKRRXT1JiztDVoW03rbWUI/v5H9cGRx+kWCpAgaUfizgE9Y6O2HdUE TpGdLfyM9yjlcDiwechxX0z6rWUmBv/yUFhVPOQh75CmwUzlgaQTVHp3gSmbuKwQkJ1SVDidL9w y23dAw0NO6DZhA4Gwb18TsU= Received: from mail.maildlp.com (unknown [172.19.162.254]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4dCV916Swqz1prkV; Fri, 21 Nov 2025 17:21:57 +0800 (CST) Received: from kwepemr100010.china.huawei.com (unknown [7.202.195.125]) by mail.maildlp.com (Postfix) with ESMTPS id B0F5018048D; Fri, 21 Nov 2025 17:23:43 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemr100010.china.huawei.com (7.202.195.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 21 Nov 2025 17:23:43 +0800 From: Tian Zheng To: , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v2 1/5] arm64/sysreg: Add HDBSS related register information Date: Fri, 21 Nov 2025 17:23:38 +0800 Message-ID: <20251121092342.3393318-2-zhengtian10@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251121092342.3393318-1-zhengtian10@huawei.com> References: <20251121092342.3393318-1-zhengtian10@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr100010.china.huawei.com (7.202.195.125) Content-Type: text/plain; charset="utf-8" From: eillon The ARM architecture added the HDBSS feature and descriptions of related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version, add them to Linux. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/esr.h | 2 ++ arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index e1deed824464..a6f3cf0b9b86 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -159,6 +159,8 @@ #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) /* ISS2 field definitions for Data Aborts */ +#define ESR_ELx_HDBSSF_SHIFT (11) +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) #define ESR_ELx_TagAccess_SHIFT (9) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 1da290aeedce..b71122680a03 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -124,6 +124,7 @@ TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) /* VTCR_EL2 Registers bits */ +#define VTCR_EL2_HDBSS (1UL << 45) #define VTCR_EL2_DS TCR_EL2_DS #define VTCR_EL2_RES1 (1U << 31) #define VTCR_EL2_HD (1 << 22) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 1c6cdf9d54bb..f489703338b5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -4408,6 +4408,34 @@ Sysreg GCSPR_EL2 3 4 2 5 1 Fields GCSPR_ELx EndSysreg +Sysreg HDBSSBR_EL2 3 4 2 3 2 +Res0 63:56 +Field 55:12 BADDR +Res0 11:4 +Enum 3:0 SZ + 0b0001 8KB + 0b0010 16KB + 0b0011 32KB + 0b0100 64KB + 0b0101 128KB + 0b0110 256KB + 0b0111 512KB + 0b1000 1MB + 0b1001 2MB +EndEnum +EndSysreg + +Sysreg HDBSSPROD_EL2 3 4 2 3 3 +Res0 63:32 +Enum 31:26 FSC + 0b000000 OK + 0b010000 ExternalAbort + 0b101000 GPF +EndEnum +Res0 25:19 +Field 18:0 INDEX +EndSysreg + Sysreg DACR32_EL2 3 4 3 0 0 Res0 63:32 Field 31:30 D15 -- 2.33.0 From nobody Tue Dec 2 01:30:20 2025 Received: from canpmsgout11.his.huawei.com (canpmsgout11.his.huawei.com [113.46.200.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851272F363E; 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Fri, 21 Nov 2025 17:23:43 +0800 From: Tian Zheng To: , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v2 2/5] KVM: arm64: Support set the DBM attr during memory abort Date: Fri, 21 Nov 2025 17:23:39 +0800 Message-ID: <20251121092342.3393318-3-zhengtian10@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251121092342.3393318-1-zhengtian10@huawei.com> References: <20251121092342.3393318-1-zhengtian10@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr100010.china.huawei.com (7.202.195.125) Content-Type: text/plain; charset="utf-8" From: eillon Add DBM support to automatically promote write-clean pages to write-dirty, preventing users from being trapped in EL2 due to missing write permissions. Since the DBM attribute was introduced in ARMv8.1 and remains optional in later architecture revisions, including ARMv9.5. Support set the DBM attr during user_mem_abort(). Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/kvm_pgtable.h | 4 ++++ arch/arm64/kvm/hyp/pgtable.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 2888b5d03757..2fa24953d1a6 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -91,6 +91,8 @@ typedef u64 kvm_pte_t; #define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54) +#define KVM_PTE_LEAF_ATTR_HI_S2_DBM BIT(51) + #define KVM_PTE_LEAF_ATTR_HI_S1_GP BIT(50) #define KVM_PTE_LEAF_ATTR_S2_PERMS (KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | \ @@ -245,6 +247,7 @@ enum kvm_pgtable_stage2_flags { * @KVM_PGTABLE_PROT_R: Read permission. * @KVM_PGTABLE_PROT_DEVICE: Device attributes. * @KVM_PGTABLE_PROT_NORMAL_NC: Normal noncacheable attributes. + * @KVM_PGTABLE_PROT_DBM: Dirty bit management attribute. * @KVM_PGTABLE_PROT_SW0: Software bit 0. * @KVM_PGTABLE_PROT_SW1: Software bit 1. * @KVM_PGTABLE_PROT_SW2: Software bit 2. @@ -257,6 +260,7 @@ enum kvm_pgtable_prot { KVM_PGTABLE_PROT_DEVICE =3D BIT(3), KVM_PGTABLE_PROT_NORMAL_NC =3D BIT(4), + KVM_PGTABLE_PROT_DBM =3D BIT(5), KVM_PGTABLE_PROT_SW0 =3D BIT(55), KVM_PGTABLE_PROT_SW1 =3D BIT(56), diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index c351b4abd5db..ce41c6924ebe 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -694,6 +694,9 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt= , enum kvm_pgtable_prot p if (prot & KVM_PGTABLE_PROT_W) attr |=3D KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; 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a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=XSG5z7NezWuc0avnwC5SfAzocygjZiNaU3gOAAGSw08=; b=NHtZg8euW9umBzAFbKKuTno6mueSgWMgcjgqSAsN4SNFgEVkFhh4PxkGHnIKfJeAg7qbhyoF9 mdq2Vr/FDTfM3qWwOvHcfhj+KrtHIaoYNlT15NFg4wTOtz/UYcn3urnXMWOt2qcjXEUhzu7ww7M a46AtZbRptp5H2obWVOpDDI= Received: from mail.maildlp.com (unknown [172.19.163.44]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4dCV941023zLlSZ; Fri, 21 Nov 2025 17:22:00 +0800 (CST) Received: from kwepemr100010.china.huawei.com (unknown [7.202.195.125]) by mail.maildlp.com (Postfix) with ESMTPS id B76CB140295; Fri, 21 Nov 2025 17:23:44 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemr100010.china.huawei.com (7.202.195.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 21 Nov 2025 17:23:44 +0800 From: Tian Zheng To: , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v2 3/5] KVM: arm64: Add support for FEAT_HDBSS Date: Fri, 21 Nov 2025 17:23:40 +0800 Message-ID: <20251121092342.3393318-4-zhengtian10@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251121092342.3393318-1-zhengtian10@huawei.com> References: <20251121092342.3393318-1-zhengtian10@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr100010.china.huawei.com (7.202.195.125) Content-Type: text/plain; charset="utf-8" From: eillon Armv9.5 introduces the Hardware Dirty Bit State Structure (HDBSS) feature, indicated by ID_AA64MMFR1_EL1.HAFDBS =3D=3D 0b0100. Add the Kconfig for FEAT_HDBSS and support detecting and enabling the feature. A CPU capability is added to notify the user of the feature. Add KVM_CAP_ARM_HW_DIRTY_STATE_TRACK ioctl and basic framework for ARM64 HDBSS support. Since the HDBSS buffer size is configurable and cannot be determined at KVM initialization, an IOCTL interface is required. Actually exposing the new capability to user space happens in a later patch. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/include/asm/cpucaps.h | 2 ++ arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/include/asm/kvm_host.h | 4 ++++ arch/arm64/include/asm/sysreg.h | 12 ++++++++++++ arch/arm64/kernel/cpufeature.c | 9 +++++++++ arch/arm64/tools/cpucaps | 1 + include/uapi/linux/kvm.h | 1 + tools/include/uapi/linux/kvm.h | 1 + 9 files changed, 49 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 6663ffd23f25..1edf75888a09 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2201,6 +2201,20 @@ config ARM64_GCS endmenu # "ARMv9.4 architectural features" +menu "ARMv9.5 architectural features" + +config ARM64_HDBSS + bool "Enable support for Hardware Dirty state tracking Structure (HDBSS)" + help + Hardware Dirty state tracking Structure(HDBSS) enhances tracking + translation table descriptors' dirty state to reduce the cost of + surveying for dirtied granules. + + The feature introduces new assembly registers (HDBSSBR_EL2 and + HDBSSPROD_EL2), which are accessed via generated register accessors. + +endmenu # "ARMv9.5 architectural features" + config ARM64_SVE bool "ARM Scalable Vector Extension support" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpuc= aps.h index 9d769291a306..5e5a26f28dec 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -48,6 +48,8 @@ cpucap_is_possible(const unsigned int cap) return IS_ENABLED(CONFIG_ARM64_GCS); case ARM64_HAFT: return IS_ENABLED(CONFIG_ARM64_HAFT); + case ARM64_HAS_HDBSS: + return IS_ENABLED(CONFIG_ARM64_HDBSS); case ARM64_UNMAP_KERNEL_AT_EL0: return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0); case ARM64_WORKAROUND_843419: diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index e223cbf350e4..b231415a2b76 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -856,6 +856,11 @@ static inline bool system_supports_haft(void) return cpus_have_final_cap(ARM64_HAFT); } +static inline bool system_supports_hdbss(void) +{ + return cpus_have_final_cap(ARM64_HAS_HDBSS); +} + static __always_inline bool system_supports_mpam(void) { return alternative_has_cap_unlikely(ARM64_MPAM); diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 64302c438355..d962932f0e5f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -60,6 +60,10 @@ #define KVM_HAVE_MMU_RWLOCK +/* HDBSS entry field definitions */ +#define HDBSS_ENTRY_VALID BIT(0) +#define HDBSS_ENTRY_IPA GENMASK_ULL(55, 12) + /* * Mode of operation configurable with kvm-arm.mode early param. * See Documentation/admin-guide/kernel-parameters.txt for more informatio= n. diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index c231d2a3e515..3511edea1fbc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1129,6 +1129,18 @@ #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) +/* + * Definitions for the HDBSS feature + */ +#define HDBSS_MAX_SIZE HDBSSBR_EL2_SZ_2MB + +#define HDBSSBR_EL2(baddr, sz) (((baddr) & GENMASK(55, 12 + sz)) | \ + FIELD_PREP(HDBSSBR_EL2_SZ_MASK, sz)) +#define HDBSSBR_BADDR(br) ((br) & GENMASK(55, (12 + HDBSSBR_SZ(br)))) +#define HDBSSBR_SZ(br) FIELD_GET(HDBSSBR_EL2_SZ_MASK, br) + +#define HDBSSPROD_IDX(prod) FIELD_GET(HDBSSPROD_EL2_INDEX_MASK, prod) + #define ARM64_FEATURE_FIELD_BITS 4 #ifdef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e25b0f84a22d..f39973b68bdb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2710,6 +2710,15 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) }, +#endif +#ifdef CONFIG_ARM64_HDBSS + { + .desc =3D "Hardware Dirty state tracking structure (HDBSS)", + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .capability =3D ARM64_HAS_HDBSS, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HDBSS) + }, #endif { .desc =3D "CRC32 instructions", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 1b32c1232d28..4be19bb4543e 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -64,6 +64,7 @@ HAS_TLB_RANGE HAS_VA52 HAS_VIRT_HOST_EXTN HAS_WFXT +HAS_HDBSS HAFT HW_DBM KVM_HVHE diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 52f6000ab020..59340189afac 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -963,6 +963,7 @@ struct kvm_enable_cap { #define KVM_CAP_RISCV_MP_STATE_RESET 242 #define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 243 #define KVM_CAP_GUEST_MEMFD_FLAGS 244 +#define KVM_CAP_ARM_HW_DIRTY_STATE_TRACK 245 struct kvm_irq_routing_irqchip { __u32 irqchip; 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charset="utf-8" From: eillon Implement the HDBSS enable/disable functionality using the KVM_CAP_ARM_HW_DIRTY_STATE_TRACK ioctl. Userspace (e.g., QEMU) can enable HDBSS by invoking the ioctl at the start of live migration, configuring the buffer size. The feature is disabled by invoking the ioctl again with size set to 0 once migration completes. Add support for updating the dirty bitmap based on the HDBSS buffer. Similar to the x86 PML implementation, KVM flushes the buffer on all VM-Exits, so running vCPUs only need to be kicked to force a VM-Exit. Signed-off-by: eillon Signed-off-by: Tian Zheng --- arch/arm64/include/asm/kvm_host.h | 10 +++ arch/arm64/include/asm/kvm_mmu.h | 17 +++++ arch/arm64/kvm/arm.c | 107 ++++++++++++++++++++++++++++++ arch/arm64/kvm/handle_exit.c | 45 +++++++++++++ arch/arm64/kvm/hyp/vhe/switch.c | 1 + arch/arm64/kvm/mmu.c | 10 +++ arch/arm64/kvm/reset.c | 3 + include/linux/kvm_host.h | 1 + 8 files changed, 194 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index d962932f0e5f..408e4c2b3d1a 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -87,6 +87,7 @@ int __init kvm_arm_init_sve(void); u32 __attribute_const__ kvm_target_cpu(void); void kvm_reset_vcpu(struct kvm_vcpu *vcpu); void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); +void kvm_arm_vcpu_free_hdbss(struct kvm_vcpu *vcpu); struct kvm_hyp_memcache { phys_addr_t head; @@ -793,6 +794,12 @@ struct vcpu_reset_state { bool reset; }; +struct vcpu_hdbss_state { + phys_addr_t base_phys; + u32 size; + u32 next_index; +}; + struct vncr_tlb; struct kvm_vcpu_arch { @@ -897,6 +904,9 @@ struct kvm_vcpu_arch { /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */ struct vncr_tlb *vncr_tlb; + + /* HDBSS registers info */ + struct vcpu_hdbss_state hdbss; }; /* diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index e4069f2ce642..6ace1080aed5 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -331,6 +331,23 @@ static __always_inline void __load_stage2(struct kvm_s= 2_mmu *mmu, asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); } +static __always_inline void __load_hdbss(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + u64 br_el2, prod_el2; + + if (!kvm->enable_hdbss) + return; + + br_el2 =3D HDBSSBR_EL2(vcpu->arch.hdbss.base_phys, vcpu->arch.hdbss.size); + prod_el2 =3D vcpu->arch.hdbss.next_index; + + write_sysreg_s(br_el2, SYS_HDBSSBR_EL2); + write_sysreg_s(prod_el2, SYS_HDBSSPROD_EL2); + + isb(); +} + static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu) { return container_of(mmu->arch, struct kvm, arch); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 870953b4a8a7..64f65e3c2a89 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -79,6 +79,92 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } +void kvm_arm_vcpu_free_hdbss(struct kvm_vcpu *vcpu) +{ + struct page *hdbss_pg =3D NULL; + + hdbss_pg =3D phys_to_page(vcpu->arch.hdbss.base_phys); + if (hdbss_pg) + __free_pages(hdbss_pg, vcpu->arch.hdbss.size); + + vcpu->arch.hdbss =3D (struct vcpu_hdbss_state) { + .base_phys =3D 0, + .size =3D 0, + .next_index =3D 0, + }; +} + +static int kvm_cap_arm_enable_hdbss(struct kvm *kvm, + struct kvm_enable_cap *cap) +{ + unsigned long i; + struct kvm_vcpu *vcpu; + struct page *hdbss_pg =3D NULL; + int size =3D cap->args[0]; + int ret =3D 0; + + if (!system_supports_hdbss()) { + kvm_err("This system does not support HDBSS!\n"); + return -EINVAL; + } + + if (size < 0 || size > HDBSS_MAX_SIZE) { + kvm_err("Invalid HDBSS buffer size: %d!\n", size); + return -EINVAL; + } + + /* Enable the HDBSS feature if size > 0, otherwise disable it. */ + if (size) { + kvm_for_each_vcpu(i, vcpu, kvm) { + hdbss_pg =3D alloc_pages(GFP_KERNEL_ACCOUNT, size); + if (!hdbss_pg) { + kvm_err("Alloc HDBSS buffer failed!\n"); + ret =3D -ENOMEM; + goto error_alloc; + } + + vcpu->arch.hdbss =3D (struct vcpu_hdbss_state) { + .base_phys =3D page_to_phys(hdbss_pg), + .size =3D size, + .next_index =3D 0, + }; + } + + kvm->enable_hdbss =3D true; + kvm->arch.mmu.vtcr |=3D VTCR_EL2_HD | VTCR_EL2_HDBSS; + + /* + * We should kick vcpus out of guest mode here to load new + * vtcr value to vtcr_el2 register when re-enter guest mode. + */ + kvm_for_each_vcpu(i, vcpu, kvm) + kvm_vcpu_kick(vcpu); + } else if (kvm->enable_hdbss) { + kvm->arch.mmu.vtcr &=3D ~(VTCR_EL2_HD | VTCR_EL2_HDBSS); + + kvm_for_each_vcpu(i, vcpu, kvm) { + /* Kick vcpus to flush hdbss buffer. */ + kvm_vcpu_kick(vcpu); + + kvm_arm_vcpu_free_hdbss(vcpu); + } + + kvm->enable_hdbss =3D false; + } + + return ret; + +error_alloc: + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!vcpu->arch.hdbss.base_phys && !vcpu->arch.hdbss.size) + continue; + + kvm_arm_vcpu_free_hdbss(vcpu); + } + + return ret; +} + int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { @@ -132,6 +218,11 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, } mutex_unlock(&kvm->lock); break; + case KVM_CAP_ARM_HW_DIRTY_STATE_TRACK: + mutex_lock(&kvm->lock); + r =3D kvm_cap_arm_enable_hdbss(kvm, cap); + mutex_unlock(&kvm->lock); + break; default: break; } @@ -420,6 +511,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) r =3D kvm_supports_cacheable_pfnmap(); break; + case KVM_CAP_ARM_HW_DIRTY_STATE_TRACK: + r =3D system_supports_hdbss(); + break; default: r =3D 0; } @@ -1837,7 +1931,20 @@ long kvm_arch_vcpu_ioctl(struct file *filp, void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *mems= lot) { + /* + * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called + * before reporting dirty_bitmap to userspace. KVM flushes the buffers + * on all VM-Exits, thus we only need to kick running vCPUs to force a + * VM-Exit. + */ + struct kvm_vcpu *vcpu; + unsigned long i; + if (!kvm->enable_hdbss) + return; + + kvm_for_each_vcpu(i, vcpu, kvm) + kvm_vcpu_kick(vcpu); } static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm, diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index cc7d5d1709cb..9ba0ea6305ef 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -412,6 +412,49 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_= vcpu *vcpu) return arm_exit_handlers[esr_ec]; } +static void kvm_flush_hdbss_buffer(struct kvm_vcpu *vcpu) +{ + int idx, curr_idx; + u64 *hdbss_buf; + struct kvm *kvm =3D vcpu->kvm; + u64 br_el2; + + if (!kvm->enable_hdbss) + return; + + dsb(sy); + isb(); + curr_idx =3D HDBSSPROD_IDX(read_sysreg_s(SYS_HDBSSPROD_EL2)); + br_el2 =3D HDBSSBR_EL2(vcpu->arch.hdbss.base_phys, vcpu->arch.hdbss.size); + + /* Do nothing if HDBSS buffer is empty or br_el2 is NULL */ + if (curr_idx =3D=3D 0 || br_el2 =3D=3D 0) + return; + + hdbss_buf =3D page_address(phys_to_page(vcpu->arch.hdbss.base_phys)); + if (!hdbss_buf) { + kvm_err("Enter flush hdbss buffer with buffer =3D=3D NULL!"); + return; + } + + guard(write_lock_irqsave)(&vcpu->kvm->mmu_lock); + for (idx =3D 0; idx < curr_idx; idx++) { + u64 gpa; + + gpa =3D hdbss_buf[idx]; + if (!(gpa & HDBSS_ENTRY_VALID)) + continue; + + gpa &=3D HDBSS_ENTRY_IPA; + kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); + } + + /* reset HDBSS index */ + write_sysreg_s(0, SYS_HDBSSPROD_EL2); + vcpu->arch.hdbss.next_index =3D 0; + isb(); +} + /* * We may be single-stepping an emulated instruction. If the emulation * has been completed in the kernel, we can return to userspace with a @@ -447,6 +490,8 @@ int handle_exit(struct kvm_vcpu *vcpu, int exception_in= dex) { struct kvm_run *run =3D vcpu->run; + kvm_flush_hdbss_buffer(vcpu); + if (ARM_SERROR_PENDING(exception_index)) { /* * The SError is handled by handle_exit_early(). If the guest diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switc= h.c index 9984c492305a..3787c9c5810d 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -220,6 +220,7 @@ void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu) __vcpu_load_switch_sysregs(vcpu); __vcpu_load_activate_traps(vcpu); __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); + __load_hdbss(vcpu); } void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 7cc964af8d30..91a2f9dbb406 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1843,6 +1843,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, if (writable) prot |=3D KVM_PGTABLE_PROT_W; + if (writable && kvm->enable_hdbss && logging_active) + prot |=3D KVM_PGTABLE_PROT_DBM; + if (exec_fault) prot |=3D KVM_PGTABLE_PROT_X; @@ -1950,6 +1953,13 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) is_iabt =3D kvm_vcpu_trap_is_iabt(vcpu); + /* + * HDBSS buffer already flushed when enter handle_trap_exceptions(). + * Nothing to do here. + */ + if (ESR_ELx_ISS2(esr) & ESR_ELx_HDBSSF) + return 1; + if (esr_fsc_is_translation_fault(esr)) { /* Beyond sanitised PARange (which is the IPA limit) */ if (fault_ipa >=3D BIT_ULL(get_kvm_ipa_limit())) { diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 959532422d3a..65e8f890f863 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -161,6 +161,9 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) free_page((unsigned long)vcpu->arch.ctxt.vncr_array); kfree(vcpu->arch.vncr_tlb); kfree(vcpu->arch.ccsidr); + + if (vcpu->arch.hdbss.base_phys || vcpu->arch.hdbss.size) + kvm_arm_vcpu_free_hdbss(vcpu); } static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 5bd76cf394fa..aa8138604b1e 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -876,6 +876,7 @@ struct kvm { struct xarray mem_attr_array; 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charset="utf-8" A new ioctl (KVM_CAP_ARM_HW_DIRTY_STATE_TRACK) provides a mechanism for userspace to configure the HDBSS buffer size during live migration, enabling hardware-assisted dirty page tracking. Signed-off-by: eillon Signed-off-by: Tian Zheng --- Documentation/virt/kvm/api.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 57061fa29e6a..25d60ff136e9 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -8703,6 +8703,21 @@ This capability indicate to the userspace whether a = PFNMAP memory region can be safely mapped as cacheable. This relies on the presence of force write back (FWB) feature support on the hardware. +7.44 KVM_CAP_ARM_HW_DIRTY_STATE_TRACK +:Architectures: arm64 +:Type: VM +:Parameters: args[0] is the allocation order determining HDBSS buffer size +:Returns: 0 on success, negative value on failure + +Enables hardware-assisted dirty page tracking via the Hardware Dirty State +Tracking Structure (HDBSS). + +When live migration is initiated, userspace can enable this feature by +setting KVM_CAP_ARM_HW_DIRTY_STATE_TRACK through IOCTL. KVM will allocate +per-vCPU HDBSS buffers. + +The feature is disabled by invoking the ioctl again. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- 2.33.0