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Fri, 21 Nov 2025 01:09:04 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:9cce:8ab9:bc72:76cd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fb9022sm9762811f8f.36.2025.11.21.01.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 01:09:03 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH] clk: renesas: r9a09g077: Propagate rate changes through mux parents Date: Fri, 21 Nov 2025 09:08:53 +0000 Message-ID: <20251121090853.5220-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Enable CLK_SET_RATE_PARENT for mux clocks so that rate changes can properly propagate to their parent clocks. Several clocks in the R9A09G077 CPG tree depend on upstream PLL or divider outputs being recalculated when a child requests a new frequency. Without this flag, rate adjustments stop at the mux layer, leaving parent rates unchanged and preventing the clock tree from converging on the intended values. Set the flag in DEF_MUX to ensure that parent clocks participate in rate negotiation, which is required for correct operation of the display and peripheral related clocks being added for RZ/T2H support. Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g077-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 7367a713991d..dfd77a1ecc92 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -78,7 +78,7 @@ enum rzt2h_clk_types { #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags= ) \ DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf =3D _conf, \ .parent_names =3D _parent_names, .num_parents =3D _num_parents, \ - .flag =3D 0, .mux_flags =3D _mux_flags) + .flag =3D CLK_SET_RATE_PARENT, .mux_flags =3D _mux_flags) #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, .flag =3D 0) --=20 2.52.0