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Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] powercap: intel_rapl: Enable MSR-based RAPL PMU support Date: Thu, 20 Nov 2025 16:05:39 -0800 Message-ID: <20251121000539.386069-3-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121000539.386069-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20251121000539.386069-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, RAPL PMU support requires adding CPU model entries to arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are not architectural and require platform-specific customization, making arch/x86 an inappropriate location for this functionality. The powercap subsystem already handles RAPL functionality and is the natural place to consolidate all RAPL features. The powercap RAPL driver already includes PMU support for TPMI-based RAPL interfaces, making it straightforward to extend this support to MSR-based RAPL interfaces as well. This consolidation eliminates the need to maintain RAPL support in multiple subsystems and provides a unified approach for both TPMI and MSR-based RAPL implementations. The MSR-based PMU support includes the following updates: 1. Register MSR-based PMU support for the supported platforms and unregister it when no online CPUs remain in the package. 2. Remove existing checks that restrict RAPL PMU support to TPMI-based interfaces and extend the logic to allow MSR-based RAPL interfaces. atomic-safe MSR reads when invoked from PMU event handlers 3. Define a CPU model list to determine which processors should register RAPL PMU interface through the powercap driver for MSR-based RAPL, excluding those that support TPMI interface. This list prevents conflicts with existing arch/x86 PMU code that already registers RAPL PMU for some processors. Add Panther Lake & Wildcat Lake to the CPU models list. Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 12 ++++++------ drivers/powercap/intel_rapl_msr.c | 24 ++++++++++++++++++++++-- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 066779460bc8..03979d32aa34 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -1594,11 +1594,11 @@ static int get_pmu_cpu(struct rapl_package *rp) if (!rp->has_pmu) return nr_cpu_ids; =20 - /* Only TPMI RAPL is supported for now */ - if (rp->priv->type !=3D RAPL_IF_TPMI) + /* Only TPMI & MSR RAPL are supported for now */ + if (rp->priv->type !=3D RAPL_IF_TPMI && rp->priv->type !=3D RAPL_IF_MSR) return nr_cpu_ids; =20 - /* TPMI RAPL uses any CPU in the package for PMU */ + /* TPMI/MSR RAPL uses any CPU in the package for PMU */ for_each_online_cpu(cpu) if (topology_physical_package_id(cpu) =3D=3D rp->id) return cpu; @@ -1611,11 +1611,11 @@ static bool is_rp_pmu_cpu(struct rapl_package *rp, = int cpu) if (!rp->has_pmu) return false; =20 - /* Only TPMI RAPL is supported for now */ - if (rp->priv->type !=3D RAPL_IF_TPMI) + /* Only TPMI & MSR RAPL are supported for now */ + if (rp->priv->type !=3D RAPL_IF_TPMI && rp->priv->type !=3D RAPL_IF_MSR) return false; =20 - /* TPMI RAPL uses any CPU in the package for PMU */ + /* TPMI/MSR RAPL uses any CPU in the package for PMU */ return topology_physical_package_id(cpu) =3D=3D rp->id; } =20 diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index 46b716ea45b2..15660c6ea5a7 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -33,6 +33,8 @@ /* private data for RAPL MSR Interface */ static struct rapl_if_priv *rapl_msr_priv; =20 +static bool rapl_msr_pmu __ro_after_init; + static struct rapl_if_priv rapl_msr_priv_intel =3D { .type =3D RAPL_IF_MSR, .reg_unit.msr =3D MSR_RAPL_POWER_UNIT, @@ -79,6 +81,8 @@ static int rapl_cpu_online(unsigned int cpu) rp =3D rapl_add_package_cpuslocked(cpu, rapl_msr_priv, true); if (IS_ERR(rp)) return PTR_ERR(rp); + if (rapl_msr_pmu) + rapl_package_add_pmu(rp); } cpumask_set_cpu(cpu, &rp->cpumask); return 0; @@ -95,10 +99,14 @@ static int rapl_cpu_down_prep(unsigned int cpu) =20 cpumask_clear_cpu(cpu, &rp->cpumask); lead_cpu =3D cpumask_first(&rp->cpumask); - if (lead_cpu >=3D nr_cpu_ids) + if (lead_cpu >=3D nr_cpu_ids) { + if (rapl_msr_pmu) + rapl_package_remove_pmu(rp); rapl_remove_package_cpuslocked(rp); - else if (rp->lead_cpu =3D=3D cpu) + } else if (rp->lead_cpu =3D=3D cpu) { rp->lead_cpu =3D lead_cpu; + } + return 0; } =20 @@ -168,6 +176,13 @@ static const struct x86_cpu_id pl4_support_ids[] =3D { {} }; =20 +/* List of MSR-based RAPL PMU support CPUs */ +static const struct x86_cpu_id pmu_support_ids[] =3D { + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), + {} +}; + static int rapl_msr_probe(struct platform_device *pdev) { const struct x86_cpu_id *id =3D x86_match_cpu(pl4_support_ids); @@ -195,6 +210,11 @@ static int rapl_msr_probe(struct platform_device *pdev) pr_info("PL4 support detected.\n"); } =20 + if (x86_match_cpu(pmu_support_ids)) { + rapl_msr_pmu =3D true; + pr_info("MSR-based RAPL PMU support enabled\n"); + } + rapl_msr_priv->control_type =3D powercap_register_control_type(NULL, "int= el-rapl", NULL); if (IS_ERR(rapl_msr_priv->control_type)) { pr_debug("failed to register powercap control_type.\n"); --=20 2.43.0