From nobody Tue Dec 2 01:30:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE0A134CFA1; Fri, 21 Nov 2025 13:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763732650; cv=none; b=UJ5CajBfYQEj/3RAeOTLny6Ab6Jqg8gn+yOFAob5FGh1HvFfnvG5aT5RIyhtwPvuFfpUhx0OIFW6Ylmae4Xqg927EC6/tgwiJ3pHybJdEr4icxxWVqCwMUDHqbNGkKMBWPSfPQbZRMUsRxm8KlxIB6YDwPO8NPEP9PT4500KmvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763732650; c=relaxed/simple; bh=Ngz4pYB+tJwskK/2e2v6SrMSgYaik/dmE+6l4zJ63mw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t0srxpskzRcH9IHJbghBdPo6xluAa3gqLK8I7pVVw45pJDVjL9xTsJnax7BkSS3Z2Ki/NJZ7RtIjKQPsLMAe5G4cC0yAEzo5jIJB0KJFoqIqht6/4CpKAIbJ4wuA9/mbjz2JC8XHDGTreI6aW2gRABkfFUDX8OlMVmDmQ9IoAvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L4Ymhv68; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L4Ymhv68" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17A32C4CEFB; Fri, 21 Nov 2025 13:44:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763732650; bh=Ngz4pYB+tJwskK/2e2v6SrMSgYaik/dmE+6l4zJ63mw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L4Ymhv686ddYKssiczei2H/0gnm9QRk3XP/8ToBKlU49Rn1EL6pd6VddsJw75SHi6 GZCa3XTt3O8NUd6x2+Qc8aM2GaGQNQOg2PhfKfY8UyiCK0Z7zmfC4oJ9Gi4e6Odll/ /2ugiI+t9msUHObZLTDxmYPTCvjuJSBrkP+vvEX6+bzucf/sKVjXlR7pVLi/bsf02K NAu5Pefb44jEDKjxcCBPLulTaSPDGArLjYRPVxuWS2UIlnkER2sS9TMuci+ThA2Kma Qw2oxQB2l9HwSjEqik+wyI6JXqBPAc28FvaD9uSr30Kpc50NuuPqr65GUDODrX/Jnv z3/F8P+2AAmxg== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Claudiu Beznea , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE Date: Fri, 21 Nov 2025 13:44:00 +0000 Message-ID: <20251121-prude-dilation-79d275fec296@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251121-tartar-drew-ba31c5ec9192@spud> References: <20251121-tartar-drew-ba31c5ec9192@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=867; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=twE2/xw0EdY4lCByaHHfukqX9Ahnfe+zRoGGS/KLfAU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkKOfPF+dPyJc5oCj1MzPJVEZM85uQqqHPX+6uOabPYI QX2mU0dpSwMYlwMsmKKLIm3+1qk1v9x2eHc8xZmDisTyBAGLk4BmIjzX4Z/quLrpLjzxOc2rNN8 wLuB1/KpGVuWlpNInHmEvWvAPp+LDP/0fTRO8R+yy50bZZd2RXXevVuTjlycs7P6qeEE0Sf8cr8 5AQ== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley This driver is used by non-polarfire devices now, and the ARCH_MICROCHIP symbol has been defined for some time on RISCV so drop it without any functional change. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index cab9a909893b..a0ef14310417 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -5,8 +5,8 @@ config COMMON_CLK_PIC32 =20 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" - depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST - default ARCH_MICROCHIP_POLARFIRE + depends on ARCH_MICROCHIP || COMPILE_TEST + default y depends on MFD_SYSCON select AUXILIARY_BUS select COMMON_CLK_DIVIDER_REGMAP --=20 2.51.0 From nobody Tue Dec 2 01:30:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94A2D34D38E; Fri, 21 Nov 2025 13:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 21 Nov 2025 13:44:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763732653; bh=/v1QAlCCWNbMx8wdrlD6B9enfAEnlVlEnoMDUomq2iQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ol/gUFQMczSrgF4dRYg+nQikDPq38qhKah68ijPzBb9d3Y2CCyFjY5jc+AYaYj+H5 8m+xYq7jgfeA3ukeVAH04lzhon4UHa8zmUDaEMPvqNhE36DOSGXSH1skt5cxPYydSN 3d4bwn+kA1N3/NeQsH/cLqXq90D/PAk8pv+qTCBTX/VjHJIZjJshfyaLJYofvS3cQA LJiOHt9lzGBypP54svXdLPiOW8+MBjbwhbJPAUrwPbDtgBSOfbzcCMrOfSgUkjkp7/ L9VguOhd8Grjkf82EmhnmFFeIgt6LAoZlLUp02saR4N0ybn+YgIa0ZyI6hhbjjPQX/ 5MyCG3gbgaXTg== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Claudiu Beznea , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Pierre-Henry Moussay Subject: [PATCH v2 2/3] dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility Date: Fri, 21 Nov 2025 13:44:01 +0000 Message-ID: <20251121-trade-slacked-5fc7c1139cb2@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251121-tartar-drew-ba31c5ec9192@spud> References: <20251121-tartar-drew-ba31c5ec9192@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1011; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=6u/MVsorAWOBiuYW/sM6Lc9tNpUToYIrlt3K2vcU0zQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkKOfMz906riTc7xdT856JynvxRZbZp8tvWTz5RKr9o8 ZxdSz2XdZSyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAivsUM/xRktZm5fr7iXed4 ZJbyffkL5z5emWB6f/8qlW1tbYXVu30ZGV4Er1sTmKh0IJJnv2Cc5Edt7qdXubY07GqPZW3L6Z6 7hAcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pierre-Henry Moussay pic64gx SoC Clock Conditioning Circuitry is compatibles with the Polarfire SoC Signed-off-by: Pierre-Henry Moussay Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yam= l b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml index f1770360798f..9a6b50527c42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -17,7 +17,11 @@ description: | =20 properties: compatible: - const: microchip,mpfs-ccc + oneOf: + - items: + - const: microchip,pic64gx-ccc + - const: microchip,mpfs-ccc + - const: microchip,mpfs-ccc =20 reg: items: --=20 2.51.0 From nobody Tue Dec 2 01:30:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65BAB34E75E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MrcXdDJf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4B69C4CEFB; Fri, 21 Nov 2025 13:44:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763732656; bh=0+J1Q5CKVMTP2xhn6YpjpspBi2tj6Gjjxk8nh8alXSY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MrcXdDJfyvU/I3meVg/ArtkEdEJx5REMlOb+eK7jKHWiSdBCUuRvZm5Eda3nnwROr tM58qKQjtrApyMD6gWUjO4pcmzRjUXsDdDaLGyyuHGlDi0pv+x3VmG623BS0d5zvpJ FKYpJblG+oBsMVYEETH3cbQ79tLlnCXx/rQ7fpmAlhYRoMXZteLfdTgd5bFwXaWUg5 x4/F6y2j2UgxFMTXfRQGhcQNC309vIDGWSJ+JsVchrLEAi76LXGcoXKsuJxuPjKkUV q9PoYR7va2W052QLZpCrXc47d3E9i0qZyPZYUPVJ/Rw1kE5gqmYrVsPh2UUDkSJMv8 fUotfhTBuhOog== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Claudiu Beznea , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Pierre-Henry Moussay Subject: [PATCH v2 3/3] dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility Date: Fri, 21 Nov 2025 13:44:02 +0000 Message-ID: <20251121-unclip-shabby-a7a16e865146@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251121-tartar-drew-ba31c5ec9192@spud> References: <20251121-tartar-drew-ba31c5ec9192@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1375; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=BAqYmh3+kZOKEzACbZi5m6qzBFcZG08zjLdoiX1jvnQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkKOfMTLvxZIKvxR3R3ZPbj37b/pu479/R0njDjUV29i ObZk5LvdJSyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiaiYM/yxqF7nGc1v1pHDq ZZ763J5xM7IyYm3eebWswNroeTZ6zxl+s3Z7KBlM0oj+8Kf41vkdukI1vaGnXjoV7BM62F574BI vKwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pierre-Henry Moussay pic64gx has a clock controller compatible with mpfs-clkcfg. Don't permit the deprecated configuration that was never supported for this SoC. Signed-off-by: Pierre-Henry Moussay Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index ee4f31596d97..a23703c281d1 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -19,7 +19,11 @@ description: | =20 properties: compatible: - const: microchip,mpfs-clkcfg + oneOf: + - items: + - const: microchip,pic64gx-clkcfg + - const: microchip,mpfs-clkcfg + - const: microchip,mpfs-clkcfg =20 reg: oneOf: @@ -69,6 +73,16 @@ required: - clocks - '#clock-cells' =20 +if: + properties: + compatible: + contains: + const: microchip,pic64gx-clkcfg +then: + properties: + reg: + maxItems: 1 + additionalProperties: false =20 examples: --=20 2.51.0