From nobody Tue Dec 2 01:26:16 2025 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BFEA3594F; Fri, 21 Nov 2025 15:45:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763739962; cv=none; b=PF1LEGkS4idGTQvBH6sAPSfM2aoyL4glKq/VRYUjuBBQELuyROE5WfSDL2QjG7bbggTW1LGir3JqgNKBdvxpiqvpthMttC/zcvYKBMsvoebRaaSneYakrBB4pO+2aQ+W9qKgwJ5m11EOPmI+CuAZulGOSFW0b8Hwb3QFh+I+zOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763739962; c=relaxed/simple; bh=ezU6u32vNzWRTEjEI099Q2bFP3GbsC3ZN8ncckHyZPY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U0ZQBNknL8HX30msLlbbMdMds79M/yEWiEYjyEGWbQv0QfHG6reOrS3NMdM+IHSbwjPOc2aP66xxe+K10+DtHOG3skc5ll+9+j9hrrVEcGsOarOCvD3m4d4vfly9aUJiC1maXGuHx7XTDaFNaXflMWZnmDFyztgsFvgxZDwmxsE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com; spf=pass smtp.mailfrom=linux.ibm.com; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b=aRxkW+Zk; arc=none smtp.client-ip=148.163.156.1 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="aRxkW+Zk" Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5ALD5BqO021442; Fri, 21 Nov 2025 15:45:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=gXnwg8 wzaxANiAB/gZJl9Ul1qELkH93rZ/kCTGNdriI=; b=aRxkW+Zk+u3R21bAKkcjMj egTsnA5ZDPu4H2oW6ffYW+25gg8sQPW9JWgd2jnnMXCEbu9KvgRRtg4xnW/e9QN9 hxj2ezA/O79B70rcH0gQr4vv19LEvnDSsjhe/tzwro7IYOf2aPWfJTI4tXzOtL3e sMZLVinoTpWHReA/l3Zzb6gI52geu4yjHj12t0Q64SX/dwi/PgArQX6xdDWG/Cka mbkrlZR2Qf8rgIXB+lxWZN+4up6FNlkWv+ZidOYiy1jCM94VpRFK1HdiK4pYoyn5 DxFfPk19qlITNS8Cc4reHdMZQn3fGRCQ0r9EBbmHfFbOm4hzDjsnvxEfgBpymHXA == Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4aejjwmt76-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Nov 2025 15:45:53 +0000 (GMT) Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 5ALDVDJ2007031; Fri, 21 Nov 2025 15:45:52 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 4af62jvs9v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Nov 2025 15:45:52 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 5ALFjmYt16580928 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Nov 2025 15:45:48 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8D2E620040; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A7932004D; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) From: Tobias Schumacher Date: Fri, 21 Nov 2025 16:45:42 +0100 Subject: [PATCH v6 1/2] genirq: Change hwirq parameter to irq_hw_number_t Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-implement-msi-domain-v6-1-444f4a6479c3@linux.ibm.com> References: <20251121-implement-msi-domain-v6-0-444f4a6479c3@linux.ibm.com> In-Reply-To: <20251121-implement-msi-domain-v6-0-444f4a6479c3@linux.ibm.com> To: Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Niklas Schnelle , Gerald Schaefer , Gerd Bayer , Halil Pasic , Matthew Rosato , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, Tobias Schumacher , Farhan Ali X-Mailer: b4 0.14.2 X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=BanVE7t2 c=1 sm=1 tr=0 ts=69208931 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=apPMBW2BC5_Ovgk0KuUA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE1MDAzMiBTYWx0ZWRfXzDz7YVV1O7tb 7ES6XYxT8Ct2yGsK00TIoLmGxxu9iGJaq2pRWSTlnZvwv5wOS6Z7h70zqQj6Dbr4MwolyX0WHeY 7oYAC0zqAeXWOXdGi9CxrFRjil492M6Q0LZOaGJ4XW2e9QX3z2AiekyCardrfkUrODU/VxOX99H bd6rnlXedM00a2de29Ps8xuEQ9bFOQVh8byvkl3kSdDMup5kQUt0UEFICV9LrH79jcOd649aQxq uwUTaIWvaq3TSf7sBAnMCwLrF8YNxcvDZ2Uifd13HBnDDOXPyzksi0KyZhD69qUCaJbJk8dmHOb Bc9sDIRLSK4J03hZhHUp8xo2Jv90I29dQTOj1+mJFsIUEy0/oiU2CTlxMeAl6Rr7efKycaREn1q oCwCUTso6bzt/Zi9c8bWySsJtSG7Cw== X-Proofpoint-GUID: nOeyL3EeU_wFrcUcP7gjFh24d9BsaPo1 X-Proofpoint-ORIG-GUID: nOeyL3EeU_wFrcUcP7gjFh24d9BsaPo1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_04,2025-11-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511150032 The irqdomain implementation internally represents hardware IRQs as irq_hw_number_t, which is defined as unsigned long int. When providing an irq_hw_number_t to the generic_handle_domain() functions that expect and unsigned int hwirq, this can lead to a loss of information. Change the hwirq parameter to irq_hw_number_t to support the full range of hwirqs. Reviewed-by: Thomas Gleixner Reviewed-by: Niklas Schnelle Reviewed-by: Farhan Ali Signed-off-by: Tobias Schumacher --- include/linux/irqdesc.h | 6 +++--- kernel/irq/irqdesc.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index fd091c35d5721eee37a2fd3d5526559671d5048d..03b63aea73bb21ae1456910afa5= 34d60f9cfa94d 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -183,9 +183,9 @@ int generic_handle_irq_safe(unsigned int irq); * and handle the result interrupt number. Return -EINVAL if * conversion failed. */ -int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwir= q); -int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int= hwirq); -int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwir= q); +int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t h= wirq); +int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_numbe= r_t hwirq); +int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t h= wirq); #endif =20 /* Test to see if a driver has successfully requested an irq */ diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index db714d3014b5f7b62403ea04b80331ec6b1dc642..0cd3198496bc0766c81c353c3ff= 80ea184793d6a 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -720,7 +720,7 @@ EXPORT_SYMBOL_GPL(generic_handle_irq_safe); * This function must be called from an IRQ context with irq regs * initialized. */ -int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwir= q) +int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t h= wirq) { return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); } @@ -738,7 +738,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_irq); * context). If the interrupt is marked as 'enforce IRQ-context only' then * the function must be invoked from hard interrupt context. */ -int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int= hwirq) +int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_numbe= r_t hwirq) { unsigned long flags; int ret; @@ -761,7 +761,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_irq_safe); * This function must be called from an NMI context with irq regs * initialized. **/ -int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwir= q) +int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t h= wirq) { WARN_ON_ONCE(!in_nmi()); return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); --=20 2.48.1 From nobody Tue Dec 2 01:26:16 2025 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1132B3346A9; Fri, 21 Nov 2025 15:45:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763739963; cv=none; b=BBO2Tf1IZi7WaFGUcEf38LUWdCK2/s4Y6io5N3DWw49BIWolfnn0PILh3GMMffMDrzcZSASaKMsGD9AB4/9IqA2M80RwaPejt0YDnDA29hf/2tlWNmby9bt4LXCMVjfBOTbCcnN+RYffNsAfyhXsmDIXtgvmoWZWxauv3wQLc1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763739963; c=relaxed/simple; bh=KSljg0PglJqxoT/Hb7lmTk40p9M1VrQHW8JzGE25aYM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eruNGYMveor/u0xHzFIZbjUlExzO3Y0c1Sw7Wwdqp/pCjMqgpdbAzCoaBZJ5VsBaOGBp5jE9tefdcyVY34Or9KeGpfgRYkvGHOpZwWbFYo1eN9m2kank8aapgZrNl8vVjvB71R30rfsqmKJMjVEjNSFIePzv/FWZdrQIqjsQg3s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com; spf=pass smtp.mailfrom=linux.ibm.com; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b=WkWRisbE; arc=none smtp.client-ip=148.163.156.1 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="WkWRisbE" Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5ALFKBbC027963; Fri, 21 Nov 2025 15:45:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=bX6k31 aOVVzog4DNn6qB4K+Q4lp6+J/Z5gotYv/ARIU=; b=WkWRisbEnSjybHjST6qd16 1+Ha3MDvmHKODkIYG7GZvMbXbiNMm/XfF3IeW6OkWmwVRqfZMuh03frQ/wfNswjW fiqtQgBaYnFIx7Zhb5YgAkrP/W2liizlxoqu/EbfTDmnwHoHsFrGupV0roaU6umF w8VkfA2NZl4kLtsrWUEkWdaZLPnQuJYn0v5mQKNdZItYGMH5mzauPNt8wCQ7hYFZ NblGh1jTFeXeS01zM3XCJ4dgYNlnNFxSZRdHb5U9lsBvjLDW/j7conk+oAZKBsXn UOwSoU8UQCwRTVLTl+UCWMNzSc4HRPh9cpRlREYIKqU1ig8PFZjyL27WcXyBSmZg == Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4aejkacqh5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Nov 2025 15:45:54 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 5ALFU8No005122; Fri, 21 Nov 2025 15:45:53 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4af5bkn06b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Nov 2025 15:45:52 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 5ALFjmdQ16580930 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Nov 2025 15:45:49 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D3BC420040; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 91ACA2004E; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 21 Nov 2025 15:45:48 +0000 (GMT) From: Tobias Schumacher Date: Fri, 21 Nov 2025 16:45:43 +0100 Subject: [PATCH v6 2/2] s390/pci: Migrate s390 IRQ logic to IRQ domain API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-implement-msi-domain-v6-2-444f4a6479c3@linux.ibm.com> References: <20251121-implement-msi-domain-v6-0-444f4a6479c3@linux.ibm.com> In-Reply-To: <20251121-implement-msi-domain-v6-0-444f4a6479c3@linux.ibm.com> To: Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Niklas Schnelle , Gerald Schaefer , Gerd Bayer , Halil Pasic , Matthew Rosato , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, Tobias Schumacher X-Mailer: b4 0.14.2 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: dJFQmXMyQLUq7sflHfhUe0e_B3cNBHt5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE1MDAzMiBTYWx0ZWRfX0eboK3iFE/3H F1wPAC2VvrOJnBhIjARtxEuFqlQcJz4KiXJsq64tKcn9NmKpTO0K7RlVe7EHwvi3DrSRiF++/W+ y0bZOmlT4W+tvSVFJ2CBtIexiVBFTKKshaSBXGnUTfvUIaRn4EW2/G1B3j8XwljO2pQoBqoK8Y8 OGhzBl07+pSP8dnR0jVEdxlFTTGLUw9Ts50ubmNjn3SObkQUGKgGIDCvJMQV1vpjW3mS5fzHM3r pON0GfAjV2VrthqbuDNhivTHzgIHk++NmLvlyL3C+oHmHm8SMLTq6mREF0yoBqaJX9R/tpcRKyq cy1/INTW9rqghyW6/aa1bJRRw7FSjc5jKLSjd/nfShGz8W0DkDvIIoVf5VJgzHUhE4LUXkk0stk kMXtMQvm/xQhtLgK2sHzuyiKvrBJNQ== X-Proofpoint-ORIG-GUID: dJFQmXMyQLUq7sflHfhUe0e_B3cNBHt5 X-Authority-Analysis: v=2.4 cv=XtL3+FF9 c=1 sm=1 tr=0 ts=69208932 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=fldua093tNUuFrKgQdEA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_04,2025-11-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511150032 s390 is one of the last architectures using the legacy API for setup and teardown of PCI MSI IRQs. Migrate the s390 IRQ allocation and teardown to the MSI parent domain API. For details, see: https://lore.kernel.org/lkml/20221111120501.026511281@linutronix.de In detail, create an MSI parent domain for each PCI domain. When a PCI device sets up MSI or MSI-X IRQs, the library creates a per-device IRQ domain for this device, which is used by the device for allocating and freeing IRQs. The per-device domain delegates this allocation and freeing to the parent-domain. In the end, the corresponding callbacks of the parent domain are responsible for allocating and freeing the IRQs. The allocation is split into two parts: - zpci_msi_prepare() is called once for each device and allocates the required resources. On s390, each PCI function has its own airq vector and a summary bit, which must be configured once per function. This is done in prepare(). - zpci_msi_alloc() can be called multiple times for allocating one or more MSI/MSI-X IRQs. This creates a mapping between the virtual IRQ number in the kernel and the hardware IRQ number. Freeing is split into two counterparts: - zpci_msi_free() reverts the effects of zpci_msi_alloc() and - zpci_msi_teardown() reverts the effects of zpci_msi_prepare(). This is called once when all IRQs are freed before a device is removed. Since the parent domain in the end allocates the IRQs, the hwirq encoding must be unambiguous for all IRQs of all devices. This is achieved by encoding the hwirq using the devfn and the MSI index. Reviewed-by: Niklas Schnelle Signed-off-by: Tobias Schumacher Reviewed-by: Farhan Ali Reviewed-by: Gerd Bayer --- arch/s390/Kconfig | 1 + arch/s390/include/asm/pci.h | 4 + arch/s390/pci/pci_bus.c | 18 ++- arch/s390/pci/pci_irq.c | 304 ++++++++++++++++++++++++++++------------= ---- 4 files changed, 212 insertions(+), 115 deletions(-) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 778ce20d34046cad84dd4ef57cab5a662e5796d9..fc82dd4f893d78f12837f36ab82= a05f2c52e0501 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -251,6 +251,7 @@ config S390 select HOTPLUG_SMT select IOMMU_HELPER if PCI select IOMMU_SUPPORT if PCI + select IRQ_MSI_LIB if PCI select KASAN_VMALLOC if KASAN select LOCK_MM_AND_FIND_VMA select MMU_GATHER_MERGE_VMAS diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index a32f465ecf73a5cc3408a312d94ec888d62848cc..60abc84cf14fe6fb1ee149df688= eea94f0983ed0 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -109,6 +110,7 @@ struct zpci_bus { struct list_head resources; struct list_head bus_next; struct resource bus_resource; + struct irq_domain *msi_parent_domain; int topo; /* TID if topo_is_tid, PCHID otherwise */ int domain_nr; u8 multifunction : 1; @@ -310,6 +312,8 @@ int zpci_dma_exit_device(struct zpci_dev *zdev); /* IRQ */ int __init zpci_irq_init(void); void __init zpci_irq_exit(void); +int zpci_create_parent_msi_domain(struct zpci_bus *zbus); +void zpci_remove_parent_msi_domain(struct zpci_bus *zbus); =20 /* FMB */ int zpci_fmb_enable_device(struct zpci_dev *); diff --git a/arch/s390/pci/pci_bus.c b/arch/s390/pci/pci_bus.c index be8c697fea0cc755cfdb4fb0a9e3b95183bec0dc..2d7b389f36e8682c3f0a10befe8= 7698751596584 100644 --- a/arch/s390/pci/pci_bus.c +++ b/arch/s390/pci/pci_bus.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -199,19 +200,27 @@ static int zpci_bus_create_pci_bus(struct zpci_bus *z= bus, struct zpci_dev *fr, s zbus->multifunction =3D zpci_bus_is_multifunction_root(fr); zbus->max_bus_speed =3D fr->max_bus_speed; =20 + if (zpci_create_parent_msi_domain(zbus)) + goto out_free_domain; + /* * Note that the zbus->resources are taken over and zbus->resources * is empty after a successful call */ bus =3D pci_create_root_bus(NULL, ZPCI_BUS_NR, ops, zbus, &zbus->resource= s); - if (!bus) { - zpci_free_domain(zbus->domain_nr); - return -EFAULT; - } + if (!bus) + goto out_remove_msi_domain; =20 zbus->bus =3D bus; + dev_set_msi_domain(&zbus->bus->dev, zbus->msi_parent_domain); =20 return 0; + +out_remove_msi_domain: + zpci_remove_parent_msi_domain(zbus); +out_free_domain: + zpci_free_domain(zbus->domain_nr); + return -ENOMEM; } =20 static void zpci_bus_release(struct kref *kref) @@ -232,6 +241,7 @@ static void zpci_bus_release(struct kref *kref) mutex_lock(&zbus_list_lock); list_del(&zbus->bus_next); mutex_unlock(&zbus_list_lock); + zpci_remove_parent_msi_domain(zbus); kfree(zbus); } =20 diff --git a/arch/s390/pci/pci_irq.c b/arch/s390/pci/pci_irq.c index e73be96ce5fe6473fc193d65b8f0ff635d6a98ba..eb374dd8213b8d517580c36ffdc= b700b9d32d1b4 100644 --- a/arch/s390/pci/pci_irq.c +++ b/arch/s390/pci/pci_irq.c @@ -7,6 +7,7 @@ #include #include #include +#include #include =20 #include @@ -126,27 +127,38 @@ static int zpci_clear_irq(struct zpci_dev *zdev) static int zpci_set_irq_affinity(struct irq_data *data, const struct cpuma= sk *dest, bool force) { - struct msi_desc *entry =3D irq_data_get_msi_desc(data); - struct msi_msg msg =3D entry->msg; - int cpu_addr =3D smp_cpu_get_cpu_address(cpumask_first(dest)); + irq_data_update_affinity(data, dest); + return IRQ_SET_MASK_OK; +} + +static void zpci_compose_msi_msg(struct irq_data *data, struct msi_msg *ms= g) +{ + struct msi_desc *desc =3D irq_data_get_msi_desc(data); + struct zpci_dev *zdev =3D to_zpci_dev(desc->dev); =20 - msg.address_lo &=3D 0xff0000ff; - msg.address_lo |=3D (cpu_addr << 8); - pci_write_msi_msg(data->irq, &msg); + if (irq_delivery =3D=3D DIRECTED) { + int cpu =3D cpumask_first(irq_data_get_affinity_mask(data)); =20 - return IRQ_SET_MASK_OK; + msg->address_lo =3D zdev->msi_addr & 0xff0000ff; + msg->address_lo |=3D (smp_cpu_get_cpu_address(cpu) << 8); + } else { + msg->address_lo =3D zdev->msi_addr & 0xffffffff; + } + msg->address_hi =3D zdev->msi_addr >> 32; + msg->data =3D data->hwirq & 0xffffffff; } =20 static struct irq_chip zpci_irq_chip =3D { .name =3D "PCI-MSI", - .irq_unmask =3D pci_msi_unmask_irq, - .irq_mask =3D pci_msi_mask_irq, + .irq_compose_msi_msg =3D zpci_compose_msi_msg, }; =20 static void zpci_handle_cpu_local_irq(bool rescan) { struct airq_iv *dibv =3D zpci_ibv[smp_processor_id()]; union zpci_sic_iib iib =3D {{0}}; + struct irq_domain *msi_domain; + irq_hw_number_t hwirq; unsigned long bit; int irqs_on =3D 0; =20 @@ -164,7 +176,9 @@ static void zpci_handle_cpu_local_irq(bool rescan) continue; } inc_irq_stat(IRQIO_MSI); - generic_handle_irq(airq_iv_get_data(dibv, bit)); + hwirq =3D airq_iv_get_data(dibv, bit); + msi_domain =3D (struct irq_domain *)airq_iv_get_ptr(dibv, bit); + generic_handle_domain_irq(msi_domain, hwirq); } } =20 @@ -229,6 +243,8 @@ static void zpci_floating_irq_handler(struct airq_struc= t *airq, struct tpi_info *tpi_info) { union zpci_sic_iib iib =3D {{0}}; + struct irq_domain *msi_domain; + irq_hw_number_t hwirq; unsigned long si, ai; struct airq_iv *aibv; int irqs_on =3D 0; @@ -256,7 +272,9 @@ static void zpci_floating_irq_handler(struct airq_struc= t *airq, break; inc_irq_stat(IRQIO_MSI); airq_iv_lock(aibv, ai); - generic_handle_irq(airq_iv_get_data(aibv, ai)); + hwirq =3D airq_iv_get_data(aibv, ai); + msi_domain =3D (struct irq_domain *)airq_iv_get_ptr(aibv, ai); + generic_handle_domain_irq(msi_domain, hwirq); airq_iv_unlock(aibv, ai); } } @@ -278,7 +296,9 @@ static int __alloc_airq(struct zpci_dev *zdev, int msi_= vecs, zdev->aisb =3D *bit; =20 /* Create adapter interrupt vector */ - zdev->aibv =3D airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK, = NULL); + zdev->aibv =3D airq_iv_create(msi_vecs, + AIRQ_IV_PTR | AIRQ_IV_DATA | AIRQ_IV_BITLOCK, + NULL); if (!zdev->aibv) return -ENOMEM; =20 @@ -290,146 +310,207 @@ static int __alloc_airq(struct zpci_dev *zdev, int = msi_vecs, return 0; } =20 -int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) +bool arch_restore_msi_irqs(struct pci_dev *pdev) { - unsigned int hwirq, msi_vecs, irqs_per_msi, i, cpu; struct zpci_dev *zdev =3D to_zpci(pdev); - struct msi_desc *msi; - struct msi_msg msg; - unsigned long bit; - int cpu_addr; - int rc, irq; =20 + zpci_set_irq(zdev); + return true; +} + +static struct airq_struct zpci_airq =3D { + .handler =3D zpci_floating_irq_handler, + .isc =3D PCI_ISC, +}; + +/* + * Encode the hwirq number for the parent domain. The encoding must be uni= que + * for each IRQ of each device in the parent domain, so it uses the devfn = to + * identify the device and the msi_index to identify the IRQ within that d= evice. + */ +static inline u32 zpci_encode_hwirq(u8 devfn, u16 msi_index) +{ + return (devfn << 16) | msi_index; +} + +static void zpci_msi_teardown_directed(struct zpci_dev *zdev) +{ + airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->max_msi); + zdev->msi_first_bit =3D -1U; +} + +static void zpci_msi_teardown_floating(struct zpci_dev *zdev) +{ + airq_iv_release(zdev->aibv); + zdev->aibv =3D NULL; + airq_iv_free_bit(zpci_sbv, zdev->aisb); zdev->aisb =3D -1UL; zdev->msi_first_bit =3D -1U; +} + +static void zpci_msi_teardown(struct irq_domain *domain, msi_alloc_info_t = *arg) +{ + struct zpci_dev *zdev =3D to_zpci_dev(domain->dev); + + zpci_clear_irq(zdev); + + if (irq_delivery =3D=3D DIRECTED) + zpci_msi_teardown_directed(zdev); + else + zpci_msi_teardown_floating(zdev); +} + +static int zpci_msi_prepare(struct irq_domain *domain, + struct device *dev, int nvec, + msi_alloc_info_t *info) +{ + struct zpci_dev *zdev =3D to_zpci_dev(dev); + struct pci_dev *pdev =3D to_pci_dev(dev); + unsigned long bit; + int msi_vecs, rc; =20 msi_vecs =3D min_t(unsigned int, nvec, zdev->max_msi); if (msi_vecs < nvec) { - pr_info("%s requested %d irqs, allocate system limit of %d", + pr_info("%s requested %d IRQs, allocate system limit of %d\n", pci_name(pdev), nvec, zdev->max_msi); } =20 rc =3D __alloc_airq(zdev, msi_vecs, &bit); - if (rc < 0) + if (rc) { + pr_err("Allocating adapter IRQs for %s failed\n", pci_name(pdev)); return rc; + } =20 - /* - * Request MSI interrupts: - * When using MSI, nvec_used interrupt sources and their irq - * descriptors are controlled through one msi descriptor. - * Thus the outer loop over msi descriptors shall run only once, - * while two inner loops iterate over the interrupt vectors. - * When using MSI-X, each interrupt vector/irq descriptor - * is bound to exactly one msi descriptor (nvec_used is one). - * So the inner loops are executed once, while the outer iterates - * over the MSI-X descriptors. - */ - hwirq =3D bit; - msi_for_each_desc(msi, &pdev->dev, MSI_DESC_NOTASSOCIATED) { - if (hwirq - bit >=3D msi_vecs) - break; - irqs_per_msi =3D min_t(unsigned int, msi_vecs, msi->nvec_used); - irq =3D __irq_alloc_descs(-1, 0, irqs_per_msi, 0, THIS_MODULE, - (irq_delivery =3D=3D DIRECTED) ? - msi->affinity : NULL); - if (irq < 0) - return -ENOMEM; + zdev->msi_first_bit =3D bit; + zdev->msi_nr_irqs =3D msi_vecs; + rc =3D zpci_set_irq(zdev); + if (rc) { + pr_err("Registering adapter IRQs for %s failed\n", + pci_name(pdev)); + + if (irq_delivery =3D=3D DIRECTED) + zpci_msi_teardown_directed(zdev); + else + zpci_msi_teardown_floating(zdev); + return rc; + } + return 0; +} =20 - for (i =3D 0; i < irqs_per_msi; i++) { - rc =3D irq_set_msi_desc_off(irq, i, msi); - if (rc) - return rc; - irq_set_chip_and_handler(irq + i, &zpci_irq_chip, - handle_percpu_irq); - } +static int zpci_msi_domain_alloc(struct irq_domain *domain, unsigned int v= irq, + unsigned int nr_irqs, void *args) +{ + struct msi_desc *desc =3D ((msi_alloc_info_t *)args)->desc; + struct zpci_dev *zdev =3D to_zpci_dev(desc->dev); + struct zpci_bus *zbus =3D zdev->zbus; + unsigned int cpu, hwirq; + unsigned long bit; + int i; =20 - msg.data =3D hwirq - bit; - if (irq_delivery =3D=3D DIRECTED) { - if (msi->affinity) - cpu =3D cpumask_first(&msi->affinity->mask); - else - cpu =3D 0; - cpu_addr =3D smp_cpu_get_cpu_address(cpu); + bit =3D zdev->msi_first_bit + desc->msi_index; + hwirq =3D zpci_encode_hwirq(zdev->devfn, desc->msi_index); =20 - msg.address_lo =3D zdev->msi_addr & 0xff0000ff; - msg.address_lo |=3D (cpu_addr << 8); + if (desc->msi_index + nr_irqs > zdev->max_msi) + return -EINVAL; =20 + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &zpci_irq_chip, zdev, + handle_percpu_irq, NULL, NULL); + + if (irq_delivery =3D=3D DIRECTED) { for_each_possible_cpu(cpu) { - for (i =3D 0; i < irqs_per_msi; i++) - airq_iv_set_data(zpci_ibv[cpu], - hwirq + i, irq + i); + airq_iv_set_ptr(zpci_ibv[cpu], bit + i, + (unsigned long)zbus->msi_parent_domain); + airq_iv_set_data(zpci_ibv[cpu], bit + i, hwirq + i); } } else { - msg.address_lo =3D zdev->msi_addr & 0xffffffff; - for (i =3D 0; i < irqs_per_msi; i++) - airq_iv_set_data(zdev->aibv, hwirq + i, irq + i); + airq_iv_set_ptr(zdev->aibv, bit + i, + (unsigned long)zbus->msi_parent_domain); + airq_iv_set_data(zdev->aibv, bit + i, hwirq + i); } - msg.address_hi =3D zdev->msi_addr >> 32; - pci_write_msi_msg(irq, &msg); - hwirq +=3D irqs_per_msi; } =20 - zdev->msi_first_bit =3D bit; - zdev->msi_nr_irqs =3D hwirq - bit; + return 0; +} =20 - rc =3D zpci_set_irq(zdev); - if (rc) - return rc; +static void zpci_msi_domain_free(struct irq_domain *domain, unsigned int v= irq, + unsigned int nr_irqs) +{ + irq_hw_number_t hwirq; + struct irq_data *d; + int i; + + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + hwirq =3D d->hwirq; + irq_domain_reset_irq_data(d); + } +} =20 - return (zdev->msi_nr_irqs =3D=3D nvec) ? 0 : zdev->msi_nr_irqs; +static const struct irq_domain_ops zpci_msi_domain_ops =3D { + .alloc =3D zpci_msi_domain_alloc, + .free =3D zpci_msi_domain_free +}; + +static bool zpci_init_dev_msi_info(struct device *dev, struct irq_domain *= domain, + struct irq_domain *real_parent, + struct msi_domain_info *info) +{ + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + info->ops->msi_prepare =3D zpci_msi_prepare; + info->ops->msi_teardown =3D zpci_msi_teardown; + + return true; } =20 -void arch_teardown_msi_irqs(struct pci_dev *pdev) +static struct msi_parent_ops zpci_msi_parent_ops =3D { + .supported_flags =3D MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX | + MSI_FLAG_MULTI_PCI_MSI, + .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS, + .init_dev_msi_info =3D zpci_init_dev_msi_info +}; + +int zpci_create_parent_msi_domain(struct zpci_bus *zbus) { - struct zpci_dev *zdev =3D to_zpci(pdev); - struct msi_desc *msi; - unsigned int i; - int rc; + char fwnode_name[18]; =20 - /* Disable interrupts */ - rc =3D zpci_clear_irq(zdev); - if (rc) - return; + sprintf(fwnode_name, "ZPCI_MSI_DOM_%04x", zbus->domain_nr); + struct irq_domain_info info =3D { + .fwnode =3D irq_domain_alloc_named_fwnode(fwnode_name), + .ops =3D &zpci_msi_domain_ops + }; =20 - /* Release MSI interrupts */ - msi_for_each_desc(msi, &pdev->dev, MSI_DESC_ASSOCIATED) { - for (i =3D 0; i < msi->nvec_used; i++) { - irq_set_msi_desc(msi->irq + i, NULL); - irq_free_desc(msi->irq + i); - } - msi->msg.address_lo =3D 0; - msi->msg.address_hi =3D 0; - msi->msg.data =3D 0; - msi->irq =3D 0; + if (!info.fwnode) { + pr_err("Failed to allocate fwnode for MSI IRQ domain\n"); + return -ENOMEM; } =20 - if (zdev->aisb !=3D -1UL) { - zpci_ibv[zdev->aisb] =3D NULL; - airq_iv_free_bit(zpci_sbv, zdev->aisb); - zdev->aisb =3D -1UL; - } - if (zdev->aibv) { - airq_iv_release(zdev->aibv); - zdev->aibv =3D NULL; + if (irq_delivery =3D=3D FLOATING) + zpci_msi_parent_ops.required_flags |=3D MSI_FLAG_NO_AFFINITY; + zbus->msi_parent_domain =3D msi_create_parent_irq_domain(&info, &zpci_msi= _parent_ops); + if (!zbus->msi_parent_domain) { + irq_domain_free_fwnode(info.fwnode); + pr_err("Failed to create MSI IRQ domain\n"); + return -ENOMEM; } =20 - if ((irq_delivery =3D=3D DIRECTED) && zdev->msi_first_bit !=3D -1U) - airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs); + return 0; } =20 -bool arch_restore_msi_irqs(struct pci_dev *pdev) +void zpci_remove_parent_msi_domain(struct zpci_bus *zbus) { - struct zpci_dev *zdev =3D to_zpci(pdev); + struct fwnode_handle *fn; =20 - zpci_set_irq(zdev); - return true; + fn =3D zbus->msi_parent_domain->fwnode; + irq_domain_remove(zbus->msi_parent_domain); + irq_domain_free_fwnode(fn); } =20 -static struct airq_struct zpci_airq =3D { - .handler =3D zpci_floating_irq_handler, - .isc =3D PCI_ISC, -}; - static void __init cpu_enable_directed_irq(void *unused) { union zpci_sic_iib iib =3D {{0}}; @@ -466,6 +547,7 @@ static int __init zpci_directed_irq_init(void) * is only done on the first vector. */ zpci_ibv[cpu] =3D airq_iv_create(cache_line_size() * BITS_PER_BYTE, + AIRQ_IV_PTR | AIRQ_IV_DATA | AIRQ_IV_CACHELINE | (!cpu ? AIRQ_IV_ALLOC : 0), NULL); --=20 2.48.1