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Fri, 21 Nov 2025 02:36:28 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34727be2fa7sm5122890a91.6.2025.11.21.02.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 02:36:28 -0800 (PST) From: Abhinaba Rakshit Date: Fri, 21 Nov 2025 16:06:04 +0530 Subject: [PATCH v2 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-enable-ufs-ice-clock-scaling-v2-1-66cb72998041@oss.qualcomm.com> References: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> In-Reply-To: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. 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Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=ELgLElZC c=1 sm=1 tr=0 ts=692040ae cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BuG_O9g0V-cG3JJ2DZcA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDA4MSBTYWx0ZWRfX/ZvFVer3svyM yk2DBiafO5OqadNwkpCpMHUQ1TzhxduXamoVem91N2OZYtoBHfrX6r4cLWaxpk2B3luo4wKlS7t FMvt3F8gv1KSZ5nmR/ScjyDUH9TkQHKr623ynJrNuyT7REhp3uw5EHVmn05lKgtnYe2Rx8vmmB7 ZjYZQ/2XRmdT66Kt6GHzdjpZmvARCJAufnOuikc1OX+LMOVr6OE1ggb5sN4jibXFwrW4kdGyF2V dUPWXimc1ERl8rzGm3Tt+PgB2I7U3stz5nMjxuhDuXOmvWvl18ZIrh2et+Y3AiyJyIbRj8z7A8b EX5vvHWJXVJjDdufgPpU/tJLSwUTCJYm/phvNggEXd/D5QrOoiNAa7SUiN+fjokYEq36yLyMjWO uRrc2BRpCD2bsywSeBQpspuSNyg2/w== X-Proofpoint-GUID: 8vSxZIGENqSYB5T6gAXKbdFJjyu3utb7 X-Proofpoint-ORIG-GUID: 8vSxZIGENqSYB5T6gAXKbdFJjyu3utb7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210081 Register optional operation-points-v2 table for ICE device and aquire its minimum and maximum frequency during ICE device probe. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock if valid (non-zero) frequencies are obtained from OPP-table. Zero min and max (default values) frequencies depicts clock scaling is disabled. When an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. For legacy targets without an ICE-device specific OPP table, fall back to the standard clock framework APIs to set the frequency. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 106 ++++++++++++++++++++++++++++++++++++++++++++-= ---- include/soc/qcom/ice.h | 1 + 2 files changed, 96 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd21d6f96eb1799963a13db4b2b72..c352446707ab5e90e6baf159c86= a0914ff4bfc53 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -111,6 +112,14 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long max_freq; + unsigned long min_freq; + bool has_opp; +}; + +static const char * const legacy_ice_clk_names[] =3D { + "ice_core_clk", + "ice", }; =20 static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -549,10 +558,29 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); =20 +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up) +{ + int ret =3D 0; + + if (scale_up && ice->max_freq) + ret =3D (ice->has_opp) ? dev_pm_opp_set_rate(ice->dev, ice->max_freq) + : clk_set_rate(ice->core_clk, ice->max_freq); + else if (!scale_up && ice->min_freq) + ret =3D (ice->has_opp) ? dev_pm_opp_set_rate(ice->dev, ice->min_freq) + : clk_set_rate(ice->core_clk, ice->min_freq); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { struct qcom_ice *engine; + u32 clk_index; + struct dev_pm_opp *opp; + int err; + unsigned long rate; =20 if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -571,18 +599,74 @@ static struct qcom_ice *qcom_ice_create(struct device= *dev, =20 /* * Legacy DT binding uses different clk names for each consumer, - * so lets try those first. If none of those are a match, it means - * the we only have one clock and it is part of the dedicated DT node. - * Also, enable the clock before we check what HW version the driver - * supports. + * so lets try those first. Also get its corresponding clock index. + */ + for (int i =3D 0; i < ARRAY_SIZE(legacy_ice_clk_names); i++) { + engine->core_clk =3D devm_clk_get_optional(dev, legacy_ice_clk_names[i]); + if (!engine->core_clk) + continue; + + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + + /* Get the ICE clk index */ + clk_index =3D of_property_match_string(dev->of_node, + "clock-names", + legacy_ice_clk_names[i]); + if (clk_index < 0) + return ERR_PTR(clk_index); + + break; + } + + /* When it does not match the legacy DT bindings + * it must have only one clock and it is part of + * decicated DT node */ - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice_core_clk"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(engine->core_clk)) - return ERR_CAST(engine->core_clk); + if (!engine->core_clk) { + engine->core_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + + /* OPP table is optional */ + err =3D devm_pm_opp_of_add_table(dev); + if (err && err !=3D -ENODEV) { + dev_err(dev, "Invalid OPP table in Device tree\n"); + return ERR_PTR(err); + } + engine->has_opp =3D (err =3D=3D 0); + + /* Since, there is only one clock + * index can be set as 0 + */ + clk_index =3D 0; + } + + /* Find the ICE core clock min and max frequencies */ + rate =3D 0; + opp =3D dev_pm_opp_find_freq_ceil_indexed(dev, &rate, clk_index); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock min freq\n"); + } else { + engine->min_freq =3D rate; + dev_pm_opp_put(opp); + } + + rate =3D ULONG_MAX; + opp =3D dev_pm_opp_find_freq_floor_indexed(dev, &rate, clk_index); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock max freq\n"); + } else { + engine->max_freq =3D rate; + dev_pm_opp_put(opp); + } + + /* Enable the clock before we check what HW version the driver supports */ + err =3D clk_prepare_enable(engine->core_clk); + if (err) { + dev_err(dev, "Failed to enable ICE core clock\n"); + return ERR_PTR(err); + } =20 if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..b701ec9e062f70152f6dea8bf6c= 4637ab6ef20f1 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -30,5 +30,6 @@ int qcom_ice_import_key(struct qcom_ice *ice, const u8 *raw_key, size_t raw_key_size, u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up); =20 #endif /* __QCOM_ICE_H__ */ --=20 2.34.1