From nobody Tue Dec 2 01:28:39 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 923233451AE for ; Fri, 21 Nov 2025 10:36:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721393; cv=none; b=VL+GaClFRsIYa+uzXVcthQ06Yp49xz93IYgPx77x+TcIdJx+kHFd8T5B4+9jYav7mOfZbMdFj9S+Y2FBBId+idkqOkHkRLj6NKjc8Y9OnMqWO1oSTW28vusk9XjJ7j+E7HuHdAKzXZfQovHTdx7LlOV/Unbf+p1sydl50RAgAXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721393; c=relaxed/simple; bh=wpQN7UC1/g2YsCJcn4Wn3sB8Jm+UDAok6ndDubzSCaw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sTBUr1JAqpIXu0/LwaUH/kcmaYU4JJkhUpbRfuohHQM5YBQfVAEw+MMHNwBO7C9+RDw4PL8DWirDhQs/Kk6M5SM2thjMJpK1QGOtRJekaXOG7lCtphOLLX45ypgj6D+ogL9CoJXxEt+euCErNWn/fuGodlIQ956O90sEJcArmHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cfK6nZja; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ay0AK+PS; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cfK6nZja"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ay0AK+PS" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AL8rpE23676366 for ; Fri, 21 Nov 2025 10:36:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sHzgYhJ00ZqazENyTafSfehJgnteKbfrSvWtSFDScSc=; b=cfK6nZjaQv2G7++t 1HLnY24kTwN8kbSsSX+XLpuPfwM6isI4haT8CmmNqqynHpjPaXfhjjtMevBy6iME inrXqjdL8PjKmcsuCmKc2LMg/i6HYRjlfh2bWoStJv3Re6nrxhB6O7IZNmP1XUWv UChBLKnf7NZlSnpmJ2ONBOC3NQMvuFTZzintiCQGh6B3jTRmKpveayOqMjnsGPH5 GvJxrasB2VU7K26q9AGvk2VckwDsRkxYSCa0YLoo2BLknJ5wg9L9T6c1IdOdJId5 xjm/ot4hKJdMnjJDcp3/0jMASWX2aiJ1X10IKhf07W30jVqVUQiimCnn2cK/lTFT bf57bg== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ajmyj8ehf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Nov 2025 10:36:30 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-34385d7c4a7so1379166a91.0 for ; Fri, 21 Nov 2025 02:36:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763721389; x=1764326189; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sHzgYhJ00ZqazENyTafSfehJgnteKbfrSvWtSFDScSc=; b=ay0AK+PSxOkL2SsiMBqrdFqYTrl58txwvxGTKdlskbP4niWPd+yoj1ao43+dBxM8hg ucO+qDp0lSPXq+mvvzfMPt3knnYar6Ham9Wo3732iqnMgCWSoiUOuvN9d1SxYwIME8WE /fspE3ftisBCLQ+2b7GCXMIC1FTmN8n9Om3kODTTrWQ0iGKhd8QrZVBWJVjSKBoq6Iea DWDjIIlPYoq8MWqU9Z+jJPMlV4BjDnVFZrhrRjNj9taB7hNpsZf9xBYangceBTpIaZm2 3RM8YBlxF3gUQsDuhdBPpmyRjUw2JZJalOFigJ9D9DdYoG7I2l0UwHW7+v0nogvPuHwX oGPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763721389; x=1764326189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sHzgYhJ00ZqazENyTafSfehJgnteKbfrSvWtSFDScSc=; b=t+xmx4yWoLVSDyRTsRyCJPLiCLxMVgtuLO8L4jhWuqt3YhFFeK4WgmypLfgqwvLrbk y2iOAqC8KGQKnol+40qqBCvyQk1W/wxPuP25v3SW4dXbS3ktFib/cPQIK+D49rZMFWYs 8ZowgPTUgeQUDYWTlvQcCUGGRWCm5W3PKaYj6orA6hmtJ6YvxHgM61SdvIIlsMi52elt Yn/BD2OoBQHL1aogZs1B/mFF9bQx8nepWCHEgEnj5xsATdzsuiQj+6Oa6uFGHlW8Llu5 uvZb2pJWCtg2GCsobdEy9aQqRdRS01kcM3YH0SP3vP10ZmYIW5/iE52Vvj8R6CSsPcSl 8Qxw== X-Forwarded-Encrypted: i=1; AJvYcCUiK0vmIuBoWEDb8biHW1atbAA+JHp7oOmAOn9wwxNSn6kt/rjUM7Pa1Fn0RR3npDKbNEZZdG0Te6FCqvE=@vger.kernel.org X-Gm-Message-State: AOJu0YxrYY0rbodnk8xgoW06zfmTYwn/AiaRJH6U81BERCpMjb8AwZsv xmyH4ySftU8NOvIEkzYtlFJDcU6YT6+AeZkiU2neD/Sysk0KrE4RZ1Z5xCVp1WnkfdYSlgYTx/1 YmLdLTNy8rRXlcebwx6QrvgqIKecHfsQhoHwFf0rFWLtr6cKQqMylA7oHuyrqWe7gYlWX4n1Zi2 Y= X-Gm-Gg: ASbGncsbiDjznzqW7sYHLPPgZyLPCBV/K1SfrgYNmp8cCXXfNESjR4+MoRNzdW+K27a oWWN6q+FDmh420c1Ux8cFVL1u1Mpni3ZTEu2Y3ThXeW3RyG61W/K1EwnhAhTT1TR+mYmPKVMsa1 setDTfJvJVMQzUpS6+ZkTsQOA1dLhTIcW/tYaQ3jaVmvKcnF1Siy4kbfn7oOHoAtelLnfm41x+R ByaSvVTH8y1k5aV+vBZJBXWpJKj6KBHXD0Sq7ouuE2YLFrj2xnaKfB7hAIjgnZh3xENDguBI3MH MGP6zVFGiFjYNXQiqENxC/LCvj4klCb6ibyIry1WnxsGwhwigKiWhyG+LLgvDt+CsaryNRA8zEv ykQHo4OaT/QjLumyYSYW6sYAWPe1ynSn6elH6QU2qtgdVFEM= X-Received: by 2002:a17:90b:5144:b0:343:72d5:2c18 with SMTP id 98e67ed59e1d1-347298a950dmr6061471a91.12.1763721389022; Fri, 21 Nov 2025 02:36:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IE96BaIvXWpv4sL4F+JmwyTCe1/pr4N9tBzQDFb8EEWvRt7SAa1qn7Je0pHZOR2x9XHXKxGvg== X-Received: by 2002:a17:90b:5144:b0:343:72d5:2c18 with SMTP id 98e67ed59e1d1-347298a950dmr6061440a91.12.1763721388546; Fri, 21 Nov 2025 02:36:28 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34727be2fa7sm5122890a91.6.2025.11.21.02.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 02:36:28 -0800 (PST) From: Abhinaba Rakshit Date: Fri, 21 Nov 2025 16:06:04 +0530 Subject: [PATCH v2 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-enable-ufs-ice-clock-scaling-v2-1-66cb72998041@oss.qualcomm.com> References: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> In-Reply-To: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=ELgLElZC c=1 sm=1 tr=0 ts=692040ae cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BuG_O9g0V-cG3JJ2DZcA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDA4MSBTYWx0ZWRfX/ZvFVer3svyM yk2DBiafO5OqadNwkpCpMHUQ1TzhxduXamoVem91N2OZYtoBHfrX6r4cLWaxpk2B3luo4wKlS7t FMvt3F8gv1KSZ5nmR/ScjyDUH9TkQHKr623ynJrNuyT7REhp3uw5EHVmn05lKgtnYe2Rx8vmmB7 ZjYZQ/2XRmdT66Kt6GHzdjpZmvARCJAufnOuikc1OX+LMOVr6OE1ggb5sN4jibXFwrW4kdGyF2V dUPWXimc1ERl8rzGm3Tt+PgB2I7U3stz5nMjxuhDuXOmvWvl18ZIrh2et+Y3AiyJyIbRj8z7A8b EX5vvHWJXVJjDdufgPpU/tJLSwUTCJYm/phvNggEXd/D5QrOoiNAa7SUiN+fjokYEq36yLyMjWO uRrc2BRpCD2bsywSeBQpspuSNyg2/w== X-Proofpoint-GUID: 8vSxZIGENqSYB5T6gAXKbdFJjyu3utb7 X-Proofpoint-ORIG-GUID: 8vSxZIGENqSYB5T6gAXKbdFJjyu3utb7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210081 Register optional operation-points-v2 table for ICE device and aquire its minimum and maximum frequency during ICE device probe. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock if valid (non-zero) frequencies are obtained from OPP-table. Zero min and max (default values) frequencies depicts clock scaling is disabled. When an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. For legacy targets without an ICE-device specific OPP table, fall back to the standard clock framework APIs to set the frequency. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 106 ++++++++++++++++++++++++++++++++++++++++++++-= ---- include/soc/qcom/ice.h | 1 + 2 files changed, 96 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd21d6f96eb1799963a13db4b2b72..c352446707ab5e90e6baf159c86= a0914ff4bfc53 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -111,6 +112,14 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long max_freq; + unsigned long min_freq; + bool has_opp; +}; + +static const char * const legacy_ice_clk_names[] =3D { + "ice_core_clk", + "ice", }; =20 static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -549,10 +558,29 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); =20 +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up) +{ + int ret =3D 0; + + if (scale_up && ice->max_freq) + ret =3D (ice->has_opp) ? dev_pm_opp_set_rate(ice->dev, ice->max_freq) + : clk_set_rate(ice->core_clk, ice->max_freq); + else if (!scale_up && ice->min_freq) + ret =3D (ice->has_opp) ? dev_pm_opp_set_rate(ice->dev, ice->min_freq) + : clk_set_rate(ice->core_clk, ice->min_freq); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { struct qcom_ice *engine; + u32 clk_index; + struct dev_pm_opp *opp; + int err; + unsigned long rate; =20 if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -571,18 +599,74 @@ static struct qcom_ice *qcom_ice_create(struct device= *dev, =20 /* * Legacy DT binding uses different clk names for each consumer, - * so lets try those first. If none of those are a match, it means - * the we only have one clock and it is part of the dedicated DT node. - * Also, enable the clock before we check what HW version the driver - * supports. + * so lets try those first. Also get its corresponding clock index. + */ + for (int i =3D 0; i < ARRAY_SIZE(legacy_ice_clk_names); i++) { + engine->core_clk =3D devm_clk_get_optional(dev, legacy_ice_clk_names[i]); + if (!engine->core_clk) + continue; + + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + + /* Get the ICE clk index */ + clk_index =3D of_property_match_string(dev->of_node, + "clock-names", + legacy_ice_clk_names[i]); + if (clk_index < 0) + return ERR_PTR(clk_index); + + break; + } + + /* When it does not match the legacy DT bindings + * it must have only one clock and it is part of + * decicated DT node */ - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice_core_clk"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(engine->core_clk)) - return ERR_CAST(engine->core_clk); + if (!engine->core_clk) { + engine->core_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + + /* OPP table is optional */ + err =3D devm_pm_opp_of_add_table(dev); + if (err && err !=3D -ENODEV) { + dev_err(dev, "Invalid OPP table in Device tree\n"); + return ERR_PTR(err); + } + engine->has_opp =3D (err =3D=3D 0); + + /* Since, there is only one clock + * index can be set as 0 + */ + clk_index =3D 0; + } + + /* Find the ICE core clock min and max frequencies */ + rate =3D 0; + opp =3D dev_pm_opp_find_freq_ceil_indexed(dev, &rate, clk_index); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock min freq\n"); + } else { + engine->min_freq =3D rate; + dev_pm_opp_put(opp); + } + + rate =3D ULONG_MAX; + opp =3D dev_pm_opp_find_freq_floor_indexed(dev, &rate, clk_index); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock max freq\n"); + } else { + engine->max_freq =3D rate; + dev_pm_opp_put(opp); + } + + /* Enable the clock before we check what HW version the driver supports */ + err =3D clk_prepare_enable(engine->core_clk); + if (err) { + dev_err(dev, "Failed to enable ICE core clock\n"); + return ERR_PTR(err); + } =20 if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..b701ec9e062f70152f6dea8bf6c= 4637ab6ef20f1 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -30,5 +30,6 @@ int qcom_ice_import_key(struct qcom_ice *ice, const u8 *raw_key, size_t raw_key_size, u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up); =20 #endif /* __QCOM_ICE_H__ */ --=20 2.34.1 From nobody Tue Dec 2 01:28:39 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC8BC345733 for ; Fri, 21 Nov 2025 10:36:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721396; cv=none; b=AUsa/FPilSyQwy23u6QMiXm+iRg572UDzZ9ScP4VXjemHM+mCQ0HlOcxCD9eGBJUK+2gFctRvjSTv1NrZYN3+1uMnNJ+duipsgBruTgrO9GEa5lCNTAdvX4YuvOKqh088q0U2Q/EJrzvNSdd0yfT+EiS2F9ULCVdt3AQERL6pi4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721396; c=relaxed/simple; bh=42Oia7LlBi+H523Rmn2IIOy7T1zt6E32yOR956DWeLM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yq0wkpYQ+RUUtHOaWr3UAC1WjizataGVY/txIChcmMrJR3JGgNNlVIH8n+O44IrrIKF8vfqkjBRWVswHb5UflelK9QpP0cfshAxbUtej+P25ZpR83AKc3mrB/j1pSgPsv3EZnVue7RBUcFCSkt5eNSBuG/MZ/d67NS9QUoIK6FY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=I4V2CI6t; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KwoC9oj1; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="I4V2CI6t"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KwoC9oj1" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ALAPamY2746815 for ; Fri, 21 Nov 2025 10:36:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CAqEF9ipkGXaLh8o6lQtStQbpT65DW2PvBWxy9J0Ebs=; b=I4V2CI6tH46zktrr AMctmO70+V+tncBeTPb2fYgTUGa9SDDjafYAW15/DncqXiuxaWDnY+Bev2a6t1a5 Ug/lX2b8L8xdRskXKq0pE8Xy0AXl+hsUJfaPSLqVqAjeTRPEBlgsrZQYtpPZX2mf FS9axJ3tTuBdNfhAEpKQvCksSTOAt8SM0k7knAL/1i+F5/3Gm57FT06hiV+VLTYS Eo6iHFei9NueZtgl3oPcSvvmWI81zb6PoHOGZYOhDUJ2UW8YPwIRDzvjwXkFu+nP 5i/CNIQYm8OLrxM1Wg567DVTpLcPyTYkPipXMEOflRIvXgxLnTLQGLpx9MZkp0MN tQc/og== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ajgeh1aqt-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Nov 2025 10:36:33 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-298389232c4so48782785ad.2 for ; Fri, 21 Nov 2025 02:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763721392; x=1764326192; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CAqEF9ipkGXaLh8o6lQtStQbpT65DW2PvBWxy9J0Ebs=; b=KwoC9oj1WK3O+Q8Ei3N987P8iw5Jhxodjsdd/XbWWCp8EswgPy+wC7zltCz5l4ZMPg q36pWEZmaNw0aZkGEBCuseX2K9kqIh3tPU1vRItr7IMJ0EAuR+6uvqwtga3hLPj+H0eq FQ7v8oEHW/UQKAh2RdKBbsYTjgqNqJLSxTfhDcb9E24RnjMjK9eNleCIXZBK3hucnxZ5 /2AbdQHcNOriijwliPV3JEmn7ME9n81+aklJSHQRZQ8mKuLY63MgJfvwDIhDlsBOqw5d 2XECAhFDPcjZ6Om9x8QqCZt0jWSA7QlZnySKNg3/s5jnHwt6N0i4GTuiUAWSAFoHDUZS kNRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763721392; x=1764326192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CAqEF9ipkGXaLh8o6lQtStQbpT65DW2PvBWxy9J0Ebs=; b=wxFu/3dC8M/JHNztY69iR21oOOj2UMd2rPJ890i5LMKXN72e0/3B4Noy8bV56z7fLv aC/xQMI0DRuUtza+GEWEkgmWl8ixLJrlavgFdIHyvdQ8FB75jv1NsA1rf5Kz+ILIwDSA LjO2zbHNx4gKKE35Svk63WUym8bbrI0OZ94n6UKh/Gf9zg7bpBztyLrD17R4SgLKBH+H Xjjzrr29/JOyo4jTPDVaQIJ84UOsj0COQvgLuUpurZ3GeviBM7ixMzCyul4OOdMsgv7N KcBLqkkOoGTInZ9ZPR7hlBC6MH7DaDCzbHe+WuE3RhrldPeanxKYj6PfBc6i05aDI56a jeBg== X-Forwarded-Encrypted: i=1; AJvYcCVwas5SU3cnReTkoypGDJhQYT3CXB5uf8HnweBPxvwaeBftxlWfqi+eq/EtICDzoU51UdiJVqaOaICDZcE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw7Qqb6qOYHDhAZS8Xm1Y9jNqSaxJK9ucft7StIzzgW/2bQNmXA LT2lmX49pcZgHkx7WBt+59tEKp2ROPK5nzXnziz+Rw/wDgCtl6G7HbaPz0RCbLx7nzeyF5vFBNV rXRovSotTxP05QdYKwLPK/LKlWXrjDMvslwz3SFdljlhJ1kdCYwwAVRiVjYCgQInpEX8ZRG1MJr w= X-Gm-Gg: ASbGnctKIcn2SaFd1/snsn4Rms8tXj+pxtt7AF8Nn5irlTv0TsZEB/s//XN7pTCXHmb aEYG1PRGfcFyBhS9ZqnaFrjHDfDfnvWn/N4SUWPGUxKMyu78zLcZpQk8yfQ+CKtWQl3Fyy+HKFD 8y1x4T1jEId6PkywKOeO/pJBo1mIZoe0NJDLnZ86LHOTyKkV9DN2xOeXxhHgF/ELSkTau6xhKYa gt+478Fc3A2PS2/QvR/8wsy8TAJ41xhpL/LzbiQk3xfQXYRSRFqKNcKfRqteA54uITD9gSXm0Pt LOfMEw+oXSVfpvwWcNIFh4AzS3yzmMZIiEX+bduqynS6FLC/9JTtYNcdtmXBz1JVKOUxPlZ0ODF CJuEEPW4D8AX+uWW8fP5sbfdH+yZ0/VdlYqMiPv8SIs0+pVI= X-Received: by 2002:a17:903:17c3:b0:295:275d:21d8 with SMTP id d9443c01a7336-29b6c0b7a66mr27378935ad.0.1763721392277; Fri, 21 Nov 2025 02:36:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IHzI2I3tYOltXt6IQ+cQ7O0lEpR29UhlkbO4Q4v1RIxYR2odAeCBqzRY1eNhIS9gX6eXHxi9A== X-Received: by 2002:a17:903:17c3:b0:295:275d:21d8 with SMTP id d9443c01a7336-29b6c0b7a66mr27378655ad.0.1763721391829; Fri, 21 Nov 2025 02:36:31 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34727be2fa7sm5122890a91.6.2025.11.21.02.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 02:36:31 -0800 (PST) From: Abhinaba Rakshit Date: Fri, 21 Nov 2025 16:06:05 +0530 Subject: [PATCH v2 2/3] ufs: host: Add ICE clock scaling during UFS clock changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-enable-ufs-ice-clock-scaling-v2-2-66cb72998041@oss.qualcomm.com> References: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> In-Reply-To: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDA4MSBTYWx0ZWRfXxKLz8FfY45lK H+0zxvXrx7I3IVmydjPEwJ4w95F/t6+D3tRjbQSFyvQFjYTah6lWBWdYE0rsCjDMrn2LhvUAAYg 9yKt9uwPPpZ0K8jQYqScj9ZTida1Rsipr4FLlG46PpYtuxTKy5ssBcXPAox8Y/X/XxT+wx6pnWr VnuI4lm6Ngkq3/iwb2qwt2UNHARQ8EZ5PXqrWa486QDVeIoT9D+YW1nG05DHd8oK74wIysuSRJb fYQvbKrPhn3QCeubE8J81QOj33OrPMXdowrWT4WYOpyX62Cjpk3DQWRNY5mDWmKJ883U71CbiD0 WDMFxtCQcdETEsxN/XCU+vMmOfLcFGUD6FKDxCgWUqMAoHVFMWOIwPiF8X4P0i/ndZGW/UohtY6 SfaRC9cLilo/cDfEqC936NBvgTafuQ== X-Proofpoint-GUID: LLYU48Eay62G6E7QFfJRY3xiYAzJTcd_ X-Authority-Analysis: v=2.4 cv=AubjHe9P c=1 sm=1 tr=0 ts=692040b1 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=lzHOrk3F_0XHYG_XrgYA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: LLYU48Eay62G6E7QFfJRY3xiYAzJTcd_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210081 Implement ICE (Inline Crypto Engine) clock scaling in sync with UFS controller clock scaling. This ensures that the ICE operates at an appropriate frequency when the UFS clocks are scaled up or down, improving performance and maintaining stability for crypto operations. Signed-off-by: Abhinaba Rakshit --- drivers/ufs/host/ufs-qcom.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8d119b3223cbdaa3297d2beabced0962a1a847d5..a60b60eb777a674fb4345fd393b= de0eab3571a23 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -305,6 +305,14 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_= profile *profile, return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); } =20 +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, bool scale_u= p) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + return qcom_ice_scale_clk(host->ice, scale_up); + + return 0; +} + static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops =3D { .keyslot_program =3D ufs_qcom_ice_keyslot_program, .keyslot_evict =3D ufs_qcom_ice_keyslot_evict, @@ -339,6 +347,11 @@ static void ufs_qcom_config_ice_allocator(struct ufs_q= com_host *host) { } =20 +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, bool scale_u= p) +{ + return 0; +} + #endif =20 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) @@ -1646,6 +1659,8 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, bool scale_up, else err =3D ufs_qcom_clk_scale_down_post_change(hba, target_freq); =20 + if (!err) + err =3D ufs_qcom_ice_scale_clk(host, scale_up); =20 if (err) { ufshcd_uic_hibern8_exit(hba); --=20 2.34.1 From nobody Tue Dec 2 01:28:39 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9A00345CC0 for ; Fri, 21 Nov 2025 10:36:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721399; cv=none; b=CBAsu/uYV1w/n23ogmwOojaA3qH880SlzLR8h5pz+qM8cetsDRvvScyp39fwyvd1P4PrjN5zU/8mLk3YlGQkAk5YZBwy/ACElQXsjlDaTlaQ5PVRs03shD4mWHyMpBw/x8RDQswsP8oz9OPQnIzT0pjwDZpsldoTRvFWfnjdPAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763721399; c=relaxed/simple; bh=Sz1vlOSV0D+xZIKhfYfVDh8pgF70ZFS+nkZyzuLd+Nw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p/z4RUTrk+gZUK0o47vpfbJRkq9cFr7wojtX8zNJsiB3bNY0MGPyR97mQwfaxRr6Ic1lj+PVvhqSWbryUIt0g8Mk2Sv4faxCRJHYqPINR6I63OzWIVYcwAEuGo0v13Ik1Sdk6fWI8Hy2Z0kakCOkb18mrvq/wCGo60O2H2cre+o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mG01GSaO; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bl3L/+MJ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mG01GSaO"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bl3L/+MJ" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AL53DPk3007861 for ; Fri, 21 Nov 2025 10:36:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4LUtc/dFuaKo7IYHuZGMVu8mLcTAVi9XHB3HqrpmlT0=; b=mG01GSaOAMm65hDM KYNUT4JZqaZ5aaG9uNqsTX//2J7lIblVeDNPr3f9HBlLU8aUcGSBbRIySAZEBO9x QTIokWi1lHP8/Ft5t1N1bwnLM2xMuWhOCh2MBXgk2hCe8zQsMfB3YCiyPe0rXK7y AzMDG0ZSB5jFfGyuAwV5jvrh5uA1tGMbOdPkNlnT1G+yt+ZfmGKjyFG5peINhQJ+ tLeoCU49B+YoW0dIngMECcKmmsf5avqSNJzpA6FSFhVDxiM+WwcQrL8si46XJWo1 K8wjII0HFidLdiOD/Wl8MS3BwfDzi1RSv9H4wtcKD/fbowPRA52L7GBocszkhXCN DaNvng== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ajhkf13m6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 21 Nov 2025 10:36:36 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-343823be748so2077643a91.0 for ; Fri, 21 Nov 2025 02:36:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763721395; x=1764326195; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4LUtc/dFuaKo7IYHuZGMVu8mLcTAVi9XHB3HqrpmlT0=; b=bl3L/+MJZ/UMzM7dhNX77WlG4nHGOjEoqR8p71Kiv6ZRIcrKlZcbcfx0lF5cDab4xD IXKuqwDCSEplUPYP5XtXMVY4ApNXXrEoki34LgbAKEDh9K9BONxQ3o1Le/KRkJ3/ytH6 ytyN0wy5rgU/YYtzAdijiyZXQRJuZb2rHoVdyZiZrLiwZNbVOktaeTB3ni4C+WFDyNDj 7DGX61DbvCZHPdmoPb+sPLQseLvKs2qQLBdz2be3jPcGhu7DekqIrOd5inrkyi74HEcC b35yLFIY8d9xVHwae+UoeZAQM88Ej7ZjZd2VJiUvehCPt3fMZeG4VRkli/T8pl240vb2 VSDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763721395; x=1764326195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4LUtc/dFuaKo7IYHuZGMVu8mLcTAVi9XHB3HqrpmlT0=; b=o0Y7SMqOg8pAagEiRUwR5ewFv9AES8CYN17ewSi4rnunNWL6qynI+obV7XjqNaErtK exQylsLq0oaWh8Zcqh9d40SWSDNchF/xg/WMVaiXtuVpwU8nS8w2g/gydOaANcKs7RTz Ud418Yb8XnI3qG2zzIFqlbNCgGBXCvLX1a89geyBVfmGN6kU6y3/3wvzJINFOYNss/HY 8ocPtujWYWxdQH0dmuK7fItI6kanPgRjIRfuDyQk8BufttBZEMxkpktccE/TGv5luQ3W LEUJw78iVX3kgMIHez3h+SdzItZ5zdMXx6SeOvGDmjvLzcOUQgtmCd88pPIZ4YK8MrvV 0ezw== X-Forwarded-Encrypted: i=1; AJvYcCWF8ZWiULCJfWM5hUDtMTxy4HMRuWrXnQPlYIKviaZZuiNGyTL+oIWsvwvdQmf0c4/3+PXJ/DNmLtPiqKg=@vger.kernel.org X-Gm-Message-State: AOJu0YxgzmEDqC0UN1/HYm+MHYZZ9Gc+U63mbbYKKJrDNNuk7M4n/1kx u/O0d+3TCQ5CuqnT40N+OCZTKkIok+ViZcBhis2m7A3orvXSZByqBkqGg8e0UJ69/6WqfOoitKW e8/xuOd/nJ4ANmw6p6PuS7JisbD7Ha07+rwBypnJZv5sEsFHjg2nxTAeQMnKv2zerII6uRvQHtS 8= X-Gm-Gg: ASbGnctToHFc0JsdgFagZYD7DpzYOCadAmtH0JIe1+S+lEgH9PF5jQi5Cuf6e9zDvKk tuK7IR9bmyacTCLqxcGtLZ2CVtn/o5TbodLxSQFpoAcMmYTr9FTYYSXo8bTLSftelpCbFpIyDd9 LOswL0eTonH5GWjBtf9C5wU8xHQqNppjkYzPsj/dqb+EvRh9uT+DEThJXBMuBYxUjfRskonTnTD 2uI2/TfhAzIjg6N4PoiIW/WqxtuOqkNzPwacQweFIZCPGON8zFhW9FdwiMzhRyk/YvRI/PT/nIF 9Lg6NxC7WPxYEtuiDapTwDhBzifxHDPHhXEQzpCibhhgw7p1mORWiLXEfUnX/4+7xzodRMSjiUE EhIrCkNTwoeRLNTHQYzd6nhDDx/My2ay7Fd1tjJF+J1/X7Vs= X-Received: by 2002:a17:90b:5291:b0:343:7714:4ca6 with SMTP id 98e67ed59e1d1-34733f006a9mr2006815a91.22.1763721395445; Fri, 21 Nov 2025 02:36:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFyRidwSlFOnbJRIIYJwVdp1bjncHdnam+AEc2s9XEeF7HVt0aV3t296lfLC+14ccvC8iEszg== X-Received: by 2002:a17:90b:5291:b0:343:7714:4ca6 with SMTP id 98e67ed59e1d1-34733f006a9mr2006786a91.22.1763721394994; Fri, 21 Nov 2025 02:36:34 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34727be2fa7sm5122890a91.6.2025.11.21.02.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 02:36:34 -0800 (PST) From: Abhinaba Rakshit Date: Fri, 21 Nov 2025 16:06:06 +0530 Subject: [PATCH v2 3/3] soc: qcom: ice: Set ICE clk to TURBO on probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251121-enable-ufs-ice-clock-scaling-v2-3-66cb72998041@oss.qualcomm.com> References: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> In-Reply-To: <20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Proofpoint-GUID: WSMjn4VHcRYdunkK5k4cGvZZVXSVEdMj X-Authority-Analysis: v=2.4 cv=ApPjHe9P c=1 sm=1 tr=0 ts=692040b4 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=u1bwIIJuvd_SIhYoViIA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: WSMjn4VHcRYdunkK5k4cGvZZVXSVEdMj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDA4MSBTYWx0ZWRfX7K2CJTUJ3lS/ 0o2ln91jBP4oR74GlfqNuKLG4DKRuoiG3gFIELn05QWK9dZd75FrmngXD/P5Mu+DoDeD5ejQYEM 26CVn0XeKK9GPvhcOWhxcSbFynpE/qRRRT3bscjdNWP4CxO6h0DHiQuzXFqGHH+wLERWzzdA8bw YYT6ojCr3Wm8J9jjdBEaR0dQxs6NZ4tXo9YlaN44GYQe8IwWcfRXfJhAkQygK/IikJI7kXoOplu eHoz8+Y6Pb0VL06ZqCYhqS1ZlG3GV6togX+84/srD8z9AGy1RmeDV4fmKS8tLna0evAF86nbfEg egEr2eLFXhJk8QtuW4e2AIxGqId/vmAg5ZwJ3BYZBVpkXV2SnrTSyvbMDkdX6aCkHrVGocB3sYE KDAyBbNfI0FKDt1P1Pl0l20Tafo7NA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210081 MMC controller lacks a clock scaling mechanism, unlike the UFS controller. By default, the MMC controller is set to TURBO mode during probe, but the ICE clock remains at XO frequency, leading to read/write performance degradation on eMMC. To address this, set the ICE clock to TURBO during probe to align it with the controller clock. This ensures consistent performance and avoids mismatches between the controller and ICE clock frequencies. For platforms where ICE is represented as a separate device, use the OPP framework to vote for TURBO mode, maintaining proper voltage and power domain constraints. For legacy targets where ICE is integrated with the storage controller, fall back to using standard clock APIs to set the frequency. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index c352446707ab5e90e6baf159c86a0914ff4bfc53..fd1ae680c64370ae6cc8f999fba= b20e4e875be03 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -616,6 +616,11 @@ static struct qcom_ice *qcom_ice_create(struct device = *dev, if (clk_index < 0) return ERR_PTR(clk_index); =20 + /* Vote for maximum clock rate for maximum performance */ + err =3D clk_set_rate(engine->core_clk, INT_MAX); + if (err) + dev_warn(dev, "Failed boosting the ICE clk to TURBO\n"); + break; } =20 @@ -636,6 +641,11 @@ static struct qcom_ice *qcom_ice_create(struct device = *dev, } engine->has_opp =3D (err =3D=3D 0); =20 + /* Vote for maximum clock rate for maximum performance */ + err =3D dev_pm_opp_set_rate(dev, INT_MAX); + if (err) + dev_warn(dev, "Failed boosting the ICE clk to TURBO\n"); + /* Since, there is only one clock * index can be set as 0 */ --=20 2.34.1